SiC MOSFET device with double auxiliary gates

Abstract

The invention relates to an SIC MOSFET device with double auxiliary gates, and belongs to the technical field of semiconductors. A grid electrode auxiliary trench gate and a source electrode auxiliary trench gate are integrated in the device, a P-connect region is arranged, and a P-type barrier region regulated and controlled by the grid electrode auxiliary trench gate is formed. When the device is in forward conduction, the grid electrode auxiliary trench gate and the source electrode auxiliary trench gate jointly deplete and pinch off the P-connect in the P-type barrier region, the connection between the P + source region and the P-well is cut off, the P-well floats, and the specific on-resistance is reduced; in the blocking state, the P-connect is not pinched off, and the potential barrier between the P-well and the P + source region is almost zero, so that good grounding is formed. When the device is in reverse freewheeling, a reverse conducting channel with a low potential barrier is introduced beside the source electrode auxiliary trench gate, the bipolar degeneration effect is eliminated through the inhibition effect of the reverse conducting channel on the body diode, and the reverse recovery rate of the device is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to a SiC MOSFET device with double auxiliary gates. Background Art

[0002] With the transformation of the global energy structure and the rapid development of power electronics technology, power semiconductor devices, as the core components of power conversion, have a performance that directly determines the efficiency, reliability and integration of the energy system. Especially in the fields of new energy vehicles, smart grids, industrial inverters and renewable energy power generation, more stringent requirements are placed on the high-voltage tolerance, high-frequency switching characteristics, high-temperature stability and low-loss characteristics of power devices. Traditional power devices represented by silicon (Si)-based materials are limited by their physical properties (such as narrow bandgap width, low critical breakdown electric field, limited thermal conductivity, etc.), and are gradually facing performance bottlenecks in high-voltage, high-temperature and high-switching frequency application scenarios. For example, the on-resistance of silicon-based devices rises sharply under high voltage, resulting in increased conduction losses; the carrier mobility decreases at high temperatures, exacerbating the risk of thermal runaway; the parasitic capacitance effect is significant during high-frequency switching, which limits the switching speed and generates additional losses. Therefore, wide-bandgap semiconductor materials represented by silicon carbide (SiC) have become an ideal choice for the new generation of power devices due to their excellent physical properties, namely wider bandgap width, higher breakdown voltage and lower on-resistance.

[0003] As a typical representative of SiC power devices, silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET) combines MOS gate control with vertical conductive structure, showing significant advantages in high-voltage blocking capability, on-resistance, switching speed, etc. However, with the complexity of application scenarios and the improvement of performance requirements, existing SiC MOSFET technology still faces challenges, including:

[0004] 1) On-resistance (R on,sp ) and the breakdown voltage (BV)

[0005] Traditional SiC MOSFET uses a vertical trench gate structure to reduce the on-resistance, but the trench gate design introduces the JFET effect. Specifically, when the device is forward-conducting, the current flows through the JFET region between the drift region and the channel region. The doping concentration and geometric dimensions of this region directly affect the on-resistance. To optimize the on-resistance, it is necessary to increase the lateral size of the JFET region or increase the doping concentration, but this will lead to a decrease in the breakdown voltage. On the other hand, if the breakdown voltage is increased by reducing the size of the JFET region or reducing the doping concentration, the on-resistance will increase significantly. This contradiction limits the performance of the device in high-efficiency applications, especially in high-voltage scenarios requiring low conduction losses, and it is difficult to achieve excellent static and dynamic characteristics at the same time.

[0006] 2) Bipolar degeneration effect of body diode during reverse freewheeling

[0007] In applications such as inverter circuits and motor drives, SiC MOSFETs need to withstand reverse freewheeling conditions. At this time, the parasitic body diode (composed of P-well and N-drift) inside the device is forced to turn on. However, when the body diode is turned on, a minority carrier injection effect will occur, leading to bipolar degradation: on the one hand, the injected holes and electrons generate heat when they recombine in the drift region, exacerbating the temperature rise of the device and reducing reliability; on the other hand, the rapid release of stored charge during reverse recovery will cause current spikes and voltage oscillations, increase switching losses and may damage peripheral circuits. In addition, the conduction voltage drop of the body diode is relatively high, which further increases the conduction loss during reverse freewheeling. In the prior art, although the body diode conduction can be suppressed by optimizing the doping distribution or introducing Schottky contacts, these methods often sacrifice the forward characteristics of the device or increase the process complexity.

[0008] In summary, although SiC MOSFET has performed well in many fields, it still faces some technical bottlenecks, especially the compromise between on-resistance and breakdown voltage and the conduction loss and bipolar degradation effect of the body diode during reverse freewheeling, which affects its performance in high-efficiency and high-frequency applications. Summary of the invention

[0009] In view of this, the purpose of the present invention is to provide a SiC MOSFET device with dual auxiliary gates, which further reduces the on-resistance and accelerates the reverse recovery rate of the diode by optimizing the structural design and doping process of the device, thereby improving the performance of the device in high-frequency and high-efficiency applications.

[0010] In order to achieve the above object, the present invention provides the following technical solutions:

[0011] A SiC MOSFET device with dual auxiliary gates, comprising:

[0012] A drift region formed on a surface of a substrate;

[0013] a drain electrode formed on the other surface of the substrate;

[0014] An N-CSL formed on a surface of the drift region;

[0015] A P-base formed on the surface of the N-CSL;

[0016] A first P-well and a second P-well formed on the surface of the N-CSL and distributed on both sides of the P-base;

[0017] A source auxiliary trench gate (Auxiliary Source) and a gate auxiliary trench gate (Auxiliary Gate) formed on the surface of the first P-well;

[0018] A barrier switch formed on the surface of the first P-well and located between the source auxiliary trench gate and the gate auxiliary trench gate, the barrier switch is controlled by the source auxiliary trench gate and the gate auxiliary trench gate, and is used to regulate the floating or grounding of the first P-well;

[0019] A gate trench gate formed on the surface of the N-CSL and the second P-well;

[0020] A P-base formed on the surface of the N-CSL and located between the gate auxiliary trench gate and the gate trench gate;

[0021] A first source N+ region and a second source P+ region formed on the surface of the P-base;

[0022] A second source N+ region is formed on the surface of the P-base and the second P-well respectively, and the second source N+ region is distributed on both sides of the gate trench gate;

[0023] And a gate electrode is formed on the top of the device, and the gate electrode is in contact with the first source P+ region, the second source P+ region, the first source N+ region and the second source N+ region respectively.

[0024] Furthermore, the barrier switch includes a P-connect and a first source P+ region. The P-connect is formed on the surface of the first P-well, and the first source P+ region is formed on the surface of the P-connect. The barrier switch and the first P-well form a P-type barrier region located between two auxiliary trench gates, and the barrier height of the barrier region can be controlled by the gate auxiliary trench gate.

[0025] When the device is forward-conducting, the source auxiliary trench gate and the gate auxiliary trench gate together deplete and pinch off the P-connect to disconnect the first P-well from the first source P+ region, thereby floating the first P-well, reducing the JFET effect and the on-resistance of the device. When the device is in blocking condition, the P-connect is not pinched off, the potential barrier between the first P-well and the first source P+ region is almost zero, and a good grounding can be formed.

[0026] Furthermore, the source auxiliary trench gate, the first source N+ region and the P-base constitute a source-controlled MOS channel structure. When the device is reversely conducting, a positive voltage is applied to the source auxiliary trench gate to form a low-barrier reverse conducting channel on the P-base, which can avoid the bipolar degradation effect caused by the conduction of the body diode and improve the reverse recovery rate.

[0027] Furthermore, the gate trench gate, the source auxiliary trench gate and the gate auxiliary trench gate are respectively wrapped by a trench gate oxide layer.

[0028] By adjusting the thickness of the trench gate oxide layer, the capacitive coupling between the gate and source of the device can be regulated, thereby improving the device performance.

[0029] The beneficial effects of the present invention are as follows: the present invention achieves the following beneficial effects by embedding a source auxiliary trench gate and an auxiliary gate trench gate and setting a P-connect area:

[0030] (1) By setting the P-connect region, a P-type barrier region consisting of a first source P+ region, a P-connect region and a P-well is formed in the source auxiliary trench gate and the auxiliary gate trench gate, and the barrier region is controlled by the P-connect to float or ground the P-well. During forward conduction, the gate auxiliary trench gate is connected to a 15V positive voltage, and together with the source auxiliary trench gate, the P-connect region is depleted and pinched off, so that the P-well is disconnected from the source, so that the P-well region is floating, reducing the JFET effect, and reducing the on-resistance without losing the breakdown voltage. Compared with the traditional asymmetric trench SiC MOSFET, the R on,sp It can be reduced by 12.5%. In the blocking state, the P-connect is not cut off, and the potential barrier between the P-well and the source P+ region is almost zero, which can form a good grounding.

[0031] (2) Through the embedded source auxiliary trench gate, a MOS channel structure controlled by the source auxiliary trench gate, which is composed of the source auxiliary trench gate, the trench gate oxide layer, the first source N+ region and the P-base, is formed. Based on the MOS channel structure, when the device is reversely flowing, the source auxiliary trench gate is positively voltageed to form a low-barrier reverse conducting channel at the P-base. The turn-on voltage V cut-in It is about 1.9V, which is 29.6% lower than the body diode turn-on voltage (about 2.7-3V), thus avoiding the bipolar degradation effect caused by the conduction of the body diode and improving the reverse recovery rate.

[0032] In summary, the present invention reduces the specific on-resistance of the device and improves the reverse recovery rate of the device by designing a SiC MOSFET device with a double auxiliary gate.

[0033] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0035] Figure 1 A schematic diagram of the overall structure of a SiC MOSFET with dual auxiliary gates provided in an embodiment of the present invention;

[0036] Figure 2 for Figure 1 Equivalent circuit diagram of the device shown;

[0037] Figure 3 Schematic diagram of the structure of a traditional asymmetric trench SiC MOSFET;

[0038] Figure 4 A comparison diagram of the output characteristic curves of the device of the present invention and the conventional asymmetric trench SiC MOSFET when the gate voltage is 15V and a current path diagram of the SiC MOSFET of the present invention when working in the first quadrant;

[0039] Figure 5 It is the total current density distribution diagram of the device of the present invention and the traditional asymmetric trench SiC MOSFET when forward conducting;

[0040] Figure 6 A comparison diagram of breakdown characteristic curves of the device of the present invention and a conventional asymmetric trench SiC MOSFET;

[0041] Figure 7 Schematic diagram of the breakdown electric field distribution of the device of the present invention and the traditional asymmetric trench SiC MOSFET;

[0042] Figure 8 is a valence band barrier height curve between ab and b in the device of the present invention when it is turned on and blocked;

[0043] Fig. 9The third quadrant curves of the device of the present invention and the conventional asymmetric trench SiC MOSFET are compared when the gate voltage is -5V for reverse conduction and the reverse current is 200A / cm 2 The total current density distribution diagram when ;

[0044] Fig.10 For reverse conduction, the hole current curves of the device of the present invention and the conventional asymmetric trench SiC MOSFET are compared when the gate voltage is -5V, and the reverse current is 200A / cm 2 Hole current density distribution at ;

[0045] Fig.11 The figure is a comparison of the reverse recovery current of the device of the present invention and the conventional asymmetric trench SiC MOSFET;

[0046] Fig.12 Capacitance comparison curve of the device of the present invention and the conventional asymmetric trench SiC MOSFET;

[0047] Fig.13 A comparison diagram of gate charge characteristics between the device of the present invention and a conventional asymmetric trench SiC MOSFET;

[0048] Fig.14 : Switching characteristic curves of the device of the present invention and the conventional asymmetric trench SiC MOSFET;

[0049] Fig.15 This is a comparison chart of switching losses between the device of the present invention and the traditional asymmetric trench SiC MOSFET.

[0050] Figure symbols: 1-drain, 2-N+SUB, 3-N-Drift, 4-N-CSL, 5-P-well, 6-gate trench gate, 7-gate auxiliary trench gate, 8-source auxiliary trench gate, 9-P-connect, 10-first source P+ region, 11-P-base, 12-trench gate oxide layer, 13-first source N+ region, 14-second source P+ region, 15-second source N+ region, 16-source. DETAILED DESCRIPTION

[0051] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0052] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0053] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0054] like Figure 1 As shown, a SiC MOSFET device with dual auxiliary gates is provided in one embodiment of the present invention. The device can be divided into three parts according to the structural characteristics, namely a traditional MOSFET structure, a source-controlled MOS channel structure, and a P-type barrier region controlled by a gate-assisted trench gate.

[0055] The device provided in this embodiment includes a drain 1, N+SUB 2, N-Drift 3, N-CSL 4, P-well 5, a gate trench gate 6, a gate auxiliary trench gate 7, a source auxiliary trench gate 8, P-connect 9, a first source P+ region 10, a P-base 11, a trench gate oxide layer 12, a first source N+ region 13, a second source P+ region 14, a second source N+ region 15 and a source 16.

[0056] Among them, the traditional MOSFET structure consists of a source 16, a second source P+ region 14, a second source N+ region 15, a P-base 11, a trench gate oxide layer 12, a gate trench gate 6, a P-well 5, an N-CSL 4, a drain 1, an N+SUB 2 and an N-Drift 3.

[0057] The drain 1 is located at the lower surface of N+SUB2.

[0058] The N+SUB2 is located at the lower surface of N-Drift3 and the upper surface of drain 1, and its thickness is 3 μm. SiC is doped with N-type impurity nitrogen (N) with a doping concentration of 1×10 19 cm -3 .

[0059] The N-Drift3 is located on the upper surface of N+SUB2 and the lower surface of N-CSL4, and its thickness is 11 μm. SiC is doped with N-type impurity nitrogen (N) with a doping concentration of 7×10 15 cm -3 .

[0060] The N-CSL4 is located on the upper surface of N-Drift3 and the lower surface of P-base11, and the left side is in contact with the left P-well5, and the right side is in contact with the trench gate oxide layer 12 and the right P-well5. The shape of N-CSL4 is an irregular rectangle with a thickness of 1.5 μm, a lower width of 2.7 μm, a middle width of 0.9 μm, and an upper width of 0.6 μm. SiC is doped with N-type impurity nitrogen (N) with a doping concentration of 2.5×10 16 cm -3 .

[0061] The P-well 5 is divided into left and right parts. The left P-well 5 is located on the lower surface of the gate auxiliary trench gate 7, the source auxiliary trench gate 8 and the P-connect 9, and the right P-well 5 is located on the lower surface of the source 16 and is in L-shape and in contact with the gate trench gate 6. The thickness of the left P-well 5 is 1.4 μm and the width is 1.1 μm. The thickness of the right P-well 5 is 1.7 μm and the width is 0.7 μm. SiC is doped with P-type impurity aluminum (AL) with a doping concentration of 1×10 19 cm -3 .

[0062] The gate trench gate 6 is wrapped in a trench gate oxide layer 12, and its left side is separated from P-base 11, P-well 5 and the second source N+ region 15 on the left side by the trench gate oxide layer 12, and its right side is separated from the second source N+ region 15 and P-well 5 on the right side by the trench gate oxide layer 12. The gate trench gate 6 has a thickness of 1.0 μm and a width of 0.5 μm, and is made of pure polysilicon. Among them, the thickness of the left, right and bottom sides of the trench gate oxide layer 12 wrapping the gate trench gate 6 is 0.05 μm.

[0063] The P-base 11 is located on the upper surface of the N-CSL 4, and the lower surfaces of the first source N+ region 13, the second source P+ region 14 and the second source N+ region 15 on the left. The thickness of the left side of the P-base 11 is 0.15 μm, the thickness of the right side is 0.35 μm, and the width is 0.6 μm. SiC is doped with P-type impurity aluminum (AL) with a doping concentration of 2.5×10 17 cm -3 .

[0064] The second source P+ region 14 is located on the upper surface of P-base 11, and the right side contacts the second source N+ region 15 on the left side. The second source P+ region 14 has a thickness of 0.3 μm and a width of 0.2 μm. SiC is doped with P-type impurity aluminum (AL) with a doping concentration of 1×10 19 cm -3 .

[0065] The second source N+ region 15 is divided into two parts, which are respectively located on the left and right sides of the gate trench gate 6. The second source N+ region 15 on the left is located on the upper surface of P-base11, and the left side is in contact with the second source P+ region 14, and the right side is separated from the gate trench gate 6 by the trench gate oxide layer 12; the right and lower sides of the second source N+ region 15 on the right are in contact with the P-well5 on the right, and the left side is separated from the gate trench gate 6 by the trench gate oxide layer 12. The second source N+ region 15 SiC is doped with N-type impurity nitrogen (N), and the doping concentration is 1×10 19 cm -3 .

[0066] The source control MOS channel structure is composed of a source auxiliary trench gate 8, a trench gate oxide layer 12, a first source N+ region 13 and a P-base 11.

[0067] The source auxiliary trench gate 8 is wrapped in a trench gate oxide layer 12, and the left, right and bottom thicknesses of the trench gate oxide layer 12 wrapping the source auxiliary trench gate 8 are all 0.05 μm. The left side of the source auxiliary trench gate 8 is separated from the P-connect 9 and the first source P+ region 10, and the right side is separated from the first source N+ region 13, P-base 11 and N-CSL 4 by the trench gate oxide layer 12. The thickness of the source auxiliary trench gate 8 is 0.7 μm, the width is 0.4 μm, and the material is pure polysilicon.

[0068] The first source N+ region 13 is located on the left upper surface of the P-base 11 and is separated from the source auxiliary trench gate 8. The first source N+ region 13 has a thickness of 0.2 μm and a width of 0.2 μm. SiC is doped with N-type impurity nitrogen (N) with a doping concentration of 1×10 19 cm -3 .

[0069] The P-type barrier region controlled by the gate-assistant trench gate is composed of P-well 5 , gate-assistant trench gate 7 , source-assistant trench gate 8 , P-connect 9 and the left source P+ region 10 .

[0070] The gate auxiliary trench gate 7 is located on the left side of the P-connect 9 and the first source P+ region 10, on the upper side of the P-well 5 and on the lower side of the source 16. It is wrapped by the trench gate oxide layer 12, and the right oxide layer thickness of the trench gate oxide layer 12 wrapping the gate auxiliary trench gate 7 is 0.03μm, and the thickness of the left and lower sides is 0.05μm. The gate auxiliary trench gate 7 has a thickness of 0.7μm and a width of 0.4μm, and is made of pure polysilicon.

[0071] The P-connect 9 is located at the lower surface of the first source P+ region 10 and the upper surface of the left P-well 5, and is between the gate auxiliary trench gate 7 and the source auxiliary trench gate 8. The thickness of the P-connect 9 is 0.4 μm, the width is 0.1 μm, and the SiC is doped with P-type impurity aluminum (AL) with a doping concentration of 6×10 17 cm -3 .

[0072] The first source P+ region 10 is located on the upper surface of P-connect 9 and is connected to the source 16. The thickness of the first source P+ region 10 is 0.2 μm and the width is 0.1 μm. SiC is doped with P-type impurity aluminum (AL) with a doping concentration of 1×10 19 cm -3 Among them, the P-well 5, the P-connect 9 and the first source P+ region 10 are arranged vertically to form a P-type barrier region.

[0073] Figure 2 The equivalent circuit diagram of the device of the present invention is shown in FIG. 1 , from which it can be seen that the SiC MOSFET device of the present invention actually integrates a P-type barrier region regulated by an auxiliary gate, which is similar to the floating and grounding of the P-well controlled by a switch. In addition, the SiC MOSFET device also integrates a reverse-conducting MOSFET controlled by a source auxiliary trench gate.

[0074] like Figure 4 The figure shows the difference between the device of the present invention and the conventional asymmetric trench SiC MOSFET (whose structure is shown in FIG. 1 ) when the gate voltage is 15V and the forward conduction is performed. Figure 3 The output characteristic curves are compared with the current path of the SiC MOSFET device of the present invention when it works in the first quadrant. ds =200A / cm 2 , and the on-resistance is 2.65mΩ·cm 2 and 3.03 mΩ·cm 2 The device of the present invention has a smaller on-resistance than the traditional asymmetric trench SiC MOSFET.

[0075] like Figure 5The figure shows the total current density distribution comparison between the device of the present invention and the conventional asymmetric trench SiC MOSFET during forward conduction. Figure 5 It can be seen that when forward conduction occurs, in the J-FET region, the current width of the device of the present invention is 0.41μm, while the current width of the conventional asymmetric trench SiC MOSFET is 0.34μm. This is because when the gate is connected to a 15V positive voltage, the P-type barrier region depletes P-connect9, disconnecting the first source P+ region 10 connected to the source from P-well5, making P-well5 floating, reducing the JFET effect, reducing the width of the depletion region, and thus increasing the width of the current flow path, so that the device of the present invention can achieve a lower on-resistance.

[0076] like Figure 6 The figure shows the comparison of the breakdown characteristic curves of the device of the present invention and the conventional asymmetric trench SiC MOSFET. It can be seen that the two devices exhibit similar BV characteristics. Figure 5 The leakage current of the two devices in the breakdown state is also shown. It can be seen from the combined curve that the P-connect area 9 introduced in the device of the present invention can well ground the P-well 5 under blocking conditions, showing good BV characteristics.

[0077] like Figure 7 The breakdown electric field distribution of the device of the present invention and the traditional asymmetric trench SiC MOSFET is shown. It can be seen that the maximum breakdown electric field of both devices is at Pwell5, and the gate oxide layer electric field is less than 3MV / cm, which is conducive to enhancing the long-term reliability of the gate oxide layer.

[0078] like Figure 8 The figure shows the valence band barrier height curve between a and b (i.e., P-well 5, P-connect 9 and the first source P+ region 10 are arranged vertically to form a P-type barrier region) of the device of the present invention when it is turned on and off. Figure 8 It can be seen that in the on state, P-well5 can be depleted and disconnected through P-connect9, thereby achieving good floating and reducing the on-resistance. In the blocking state, P-well5 can be grounded through P-connect9, showing excellent BV characteristics.

[0079] like Fig. 9 The third quadrant curves of the device of the present invention and the conventional asymmetric trench SiC MOSFET are shown as follows when the gate voltage is -5V and the reverse current is 200A / cm 2 It can be seen that when the device is reversely conducting, the reverse channel of the device of the present invention is turned on at about 1.9V, while the body diode of the conventional device is turned on at about 2.7V. Fig. 9 It can be seen that when the reverse current is 200A / cm2 The device of the present invention suppresses the conduction of the body diode and avoids the bipolar degradation effect.

[0080] like Fig.10 The figure shows the hole current curve comparison between the device of the present invention and the conventional asymmetric trench SiC MOSFET when the gate voltage is -5V and the reverse current is 200A / cm 2 It can be seen that when the reverse voltage is close to -3.1V, the body diode of the device of the present invention begins to conduct, changing from unipolar conduction to bipolar conduction. Before this, the hole current is almost 0, which completely suppresses the conduction of the body diode and avoids the bipolar degradation effect.

[0081] like Fig.11 The figure shows the relationship between the reverse recovery current of the device of the present invention and the traditional asymmetric trench SiC MOSFET. Due to the existence of the low barrier channel, the body diode can be inhibited from turning on during the reverse recovery process, thereby greatly reducing the hole injection efficiency of the body diode device, thereby reducing the reverse recovery charge, reverse peak current and reverse recovery time, and ultimately improving the reverse recovery performance of the device. Fig.11 As can be seen from the figure, the reverse recovery time (T rr ) is 13ns, while the reverse recovery time of the device of the present invention is 6ns, which is reduced by 53.8% compared with the conventional device; the reverse recovery current peak value (I rr ) is 423A / cm 2 , while the peak reverse recovery current of the device of the present invention is 346A / cm 2 , compared with traditional devices, it is reduced by 18.8%; the reverse recovery charge Q of traditional SiC MOSFET devices rr 2.76μC / cm 2 , the reverse recovery charge Q of the device of the present invention rr 0.96μC / cm 2 , compared with traditional devices, it is reduced by 65.2%.

[0082] like Fig.12 The figure shows the capacitance comparison between the device of the present invention and the conventional asymmetric trench SiC MOSFET. Fig.12 It can be seen that the feedback capacitance (C rss ) and output capacitor (C oss ) is slightly lower than the conventional asymmetric trench SiC MOSFET, but the input capacitance (C iss) is increased by 40.8%. This is because the auxiliary trench gate introduced into the device of the present invention increases the overlap area of ​​the gate and the source, increases the capacitive coupling between the gate and the source, and can reduce the capacitive coupling between the gate and the source by adjusting the thickness of the oxide layer, thereby improving the device performance.

[0083] like Fig.13 The figure shows the comparison of gate charge characteristics between the device of the present invention and the conventional asymmetric trench SiC MOSFET. gd ) and total gate charge (Q at VGS = 0 to 15V g ) are 56.7nC / cm 2 and 780nC / cm 2 , and the traditional asymmetric trench SiC MOSFET is 58.2nC / cm2 and 610nC / cm2. This is because the device C of the present invention gs The capacitance increases, and the gate current after the plateau period is mainly C gs The total gate charge of the device of the present invention is therefore higher.

[0084] like Fig.14 The switching characteristic curves of the device of the present invention and the conventional asymmetric trench SiC MOSFET are shown. It can be seen that during the shutdown process, the performance of the two devices is almost the same, but during the startup process, the device of the present invention takes a slightly longer time due to its larger input capacitance.

[0085] like Fig.15 The figure shows the switching loss comparison between the device of the present invention and the conventional asymmetric trench SiC MOSFET. Fig.15 It can be seen that the on and off losses of the device of the present invention and the traditional asymmetric trench SiC MOSFET are 1.32 mJ / cm 2 , 0.85mJ / cm 2 and 0.90mJ / cm 2 、0.78mJ / cm 2 It can be seen that the turn-off performance of the two devices is basically the same, but in the turn-on performance, the input capacitance of the device of the present invention is larger and the loss is greater. As an improvement, the thickness of the oxide layer in the device of the present invention can be adjusted to shield and reduce the capacitive coupling and improve the device performance.

[0086] The relevant parameters of the SiC MOSFET device described in the present invention and the traditional asymmetric trench SiC MOSFET device are compared as shown in Table 1 below:

[0087] Table 1

[0088] Device of the present invention Traditional devices <![CDATA[R on,sp ]]> <![CDATA[2.65mΩ·cm 2 ]]> <![CDATA[3.03mΩ·cm 2 ]]> <![CDATA[Q gd ]]> <![CDATA[56.7nC / cm 2 ]]> <![CDATA[58.2nC / cm 2 ]]> BV 1265V 1229V <![CDATA[V cut-in ]]> 1.9V 2.7V <![CDATA[Q rr ]]> 0.96μC 2.76μC <![CDATA[T rr ]]> 6ns 13ns <![CDATA[I rr ]]> <![CDATA[346A / cm 2 ]]> <![CDATA[423A / cm 2 ]]> <![CDATA[E on ]]> <![CDATA[1.32mJ / cm 2 ]]> <![CDATA[0.90mJ / cm 2 <!-- 7 -->]]> <![CDATA[E off ]]> <![CDATA[0.85mJ / cm 2 ]]> <![CDATA[0.78mJ / cm 2 ]]>

[0089] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A SiC MOSFET device with dual auxiliary gates, characterized in that: The device includes: A drift region formed on a surface of a substrate; An N-CSL formed on a surface of the drift region; A P-base formed on the surface of the N-CSL; A first P-well and a second P-well formed on the surface of the N-CSL and distributed on both sides of the P-base; A source auxiliary trench gate and a gate auxiliary trench gate formed on the surface of the first P-well; A barrier switch formed on the surface of the first P-well and located between the source auxiliary trench gate and the gate auxiliary trench gate, the barrier switch is controlled by the source auxiliary trench gate and the gate auxiliary trench gate, and is used to regulate the floating or grounding of the first P-well; A gate trench gate formed on the surface of the N-CSL and the second P-well; A P-base formed on the surface of the N-CSL and located between the gate auxiliary trench gate and the gate trench gate; A first source N+ region and a second source P+ region formed on the surface of the P-base; A second source N+ region is formed on the surface of the P-base and the second P-well respectively, and the second source N+ region is distributed on both sides of the gate trench gate.

2. The SiC MOSFET device according to claim 1, characterized in that: The barrier switch located between the source auxiliary trench gate and the gate auxiliary trench gate includes a P-connect and a first source P+ region; the P-connect is formed on the first P-well surface, and the first source P+ region is formed on the P-connect surface.

3. The SiC MOSFET device according to claim 2, characterized in that: When the device is forward-conducted, the source auxiliary trench gate and the gate auxiliary trench gate jointly deplete and pinch off the P-connect to disconnect the first P-well from the first source P+ region, thereby making the first P-well float.

4. The SiC MOSFET device according to claim 1, characterized in that: The source auxiliary trench gate, the first source N+ region and the P-base constitute a source-controlled MOS channel structure. When the device is reversely freewheeling, a positive voltage is applied to the source auxiliary trench gate to form a low-barrier reverse conducting channel on the P-base to avoid the bipolar degradation effect and improve the reverse recovery rate of the device.

5. The SiC MOSFET device according to claim 1, characterized in that: The gate trench gate, the source auxiliary trench gate and the gate auxiliary trench gate are respectively wrapped by trench gate oxide layers.

6. The SiC MOSFET device according to claim 5, characterized in that: By adjusting the thickness of the trench gate oxide layer, the capacitive coupling between the gate and source of the device is regulated, thereby improving the device performance.

7. The SiC MOSFET device according to any one of claims 1 to 6, characterized in that: The device also includes a gate electrode at the top and a drain electrode at the bottom; The gate electrode is in contact with the first source P+ region, the second source P+ region, the first source N+ region and the second source N+ region respectively; The drain electrode is located on a surface of the substrate away from the drift region.

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