A shield-gate field-effect transistor for eliminating voltage clamping and a manufacturing method thereof

Abstract

A shield-gate field-effect transistor for eliminating voltage clamping and a manufacturing method thereof. The shield-gate field-effect transistor includes a shield gate, a control gate, and a source metal. The shield gate and the control gate are located in a trench. The shield gate includes a gate body portion and an extension portion. The gate body portion is located below the control gate. The extension portion extends upward from the gate body portion and is led out from both sides of the control gate to the top of the trench, or the extension portion is led out from one side of the control gate to the top of the trench. The top of the extension portion is in direct contact with the source metal through a configured contact hole structure. Compared with the up-and-down structure of the shield gate and the control gate in a traditional SGT, the present invention can open a whole contact hole at the top of the extended shield gate extension portion to be in direct contact with the source metal, eliminating the shield gate resistance, thereby avoiding the shield gate current voltage, eliminating the voltage clamping problem introduced by the shield, and at the same time improving the charge balance effect and the electric field distribution of the overall chip and reducing the current concentration.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, relates to medium and low voltage power devices, and is a shield gate field effect transistor for eliminating voltage clamping and a preparation method thereof. Background Art

[0002] In the field of medium and low voltage power devices, trench MOSFETs are widely used in medium and low voltage high-performance DC / DC converters, low voltage system motor control, motor drive and other fields due to their advantages such as low on-resistance and fast switching speed. With the continuous development of technology, higher system response speed, circuit conversion efficiency, lower power consumption and electromagnetic interference are required in terminal applications. All of these point to the need for shorter turn-on and turn-off times in circuit requirements. Selecting components with fast switching characteristics can significantly improve the switching speed.

[0003] In the medium and low voltage field, as one of the most competitive power MOSFET devices at present, it is necessary to improve the switching speed of shield gate trench (SGT) MOSFET devices and the performance of SGT devices at high switching speeds. Among them, the voltage clamping problem is a problem that is easily encountered at high switching speeds. Solving the voltage clamping problem is also an important topic in the development of SGTs.

[0004] There are two common structures of shield gate MOSFETs. One is the left-right structure, where the shield gate extends to the top of the trench, and the control gate is arranged on the left and right sides of the shield gate in the top region of the trench, that is, the control gate is split into two and placed on the left and right sides of the shield gate. The disadvantage of this structure is that there is a large overlap area between the control gate and the shield gate, thus introducing a large input capacitance and easily causing mis-turn-on of the gate.

[0005] The second is the up-down structure, that is, the shield gate is entirely placed under the control gate. The disadvantage of this structure is that it is not easy to lead out the shield gate, resulting in uneven potential of the shield gate and affecting the switching speed of the device. As Figures 1-4As shown, the shielding gate 101 is used as a field plate and buried inside the trench. A gate oxide layer IPO with a certain thickness and a control gate 102 are covered on it. From the perspective of looking down at the field effect transistor, the shielding gate can only be led out from the interlayer dielectric ILD through contact hole contact structures configured at both the upper and lower ends and connected to the source metal 103. Thus, a parasitic resistance Rsp and a parasitic capacitance Csp are generated in the shielding gate. The farther the distance between the contact holes led out from the upper and lower longitudinal shielding gates, the greater the generated parasitic resistance Rsp. In the application of SGT switches, when the drain voltage Vd changes, it will cause a displacement current Idif = Csp * dv / dt in the parasitic capacitance Csp. This current will increase through the parasitic resistance Rsp of the shielding gate and flow to the contact hole, thereby generating a voltage drop Vsp on Rsp, that is, the voltage difference between the drain end and the SG node, Vsp = Rsp * Idif = Rsp * Csp * dv / dt. The time for Vsp to decrease to 0 during the device turn-off process will become longer due to the increase in Rsp, which buffers the reduction process of Vds and affects the device turn-off speed. In fast-switching applications, a voltage clamping phenomenon appears, bringing additional direct conduction losses. In severe cases, when the avalanche current of other already turned-off cells flows to the non-turn-off cells and the current concentrates on the turned-off cells, it will cause device failure. Summary of the Invention

[0006] The technical problem to be solved by the present invention is that the shielding gate trench power MOSFET needs to improve the switching speed, and the voltage clamping problem affects the improvement of the switching speed, while the existing structure of the shielding gate trench power MOSFET cannot overcome the generation of voltage clamping.

[0007] The technical solution of the present invention is: a shielding gate field effect transistor for eliminating voltage clamping, including a shielding gate, a control gate, and a source metal. The shielding gate and the control gate are located in the trench. The shielding gate includes a gate body part and an extending part. The gate body part is located below the control gate. The extending part extends upward from the gate body part and is led out from both the left and right sides of the control gate to the top of the trench. The shielding gate forms a "concave" shape. The control gate is sandwiched in the middle of the extending part. The top of the extending part is in contact with the source metal through a configured contact hole contact structure.

[0008] Further, as another implementation manner, the extending part extends upward from the gate body part and is led out from one side of the left or right side of the control gate to the top of the trench. The top of the extending part is in contact with the source metal through a configured contact hole contact structure.

[0009] Further, the extending part of the shielding gate is arranged side by side with the control gate, and the contact hole contact structure is arranged along the top surface of the extending part, presenting a side-by-side long strip shape.

[0010] The preparation method of the above-mentioned shielding gate field effect transistor for eliminating voltage clamping includes the following steps:

[0011] 1) Prepare a raw wafer;

[0012] 2) Perform trench etching and grow an oxide layer in the trench;

[0013] 3) Etch the oxide layer to form a first trench, and fill polysilicon in the first trench to form a shielding gate;

[0014] 4) Etch the shielding gate to form a second trench. During etching, retain the shielding gate on the left and right sides or one side to form an extended portion, and the unetched portion forms a gate body portion;

[0015] 5) Deposit an oxide layer on the second trench obtained by etching in step 4), then etch the oxide layer to form a filling space for the control gate and a gate oxide layer. After filling gate polysilicon, a control gate is obtained. Then, through subsequent electrode processes of the shielding gate field-effect transistor, the shielding gate field-effect transistor for eliminating voltage clamping is obtained.

[0016] Furthermore, the shielding gate extended portion and the control gate form a side-by-side structure in the trench. Under the condition that the top width of the extended portion meets the required space for the control gate, retain as large a width as possible to facilitate the preparation process of the contact hole.

[0017] In the present invention, compared with the up-and-down structure of the shielding gate and the control gate in the traditional SGT, a whole contact can be opened at the top of the extended shielding gate extended portion to directly contact the source metal, as Figure 6 shown. Since there is no distance for the contact hole contact on the shielding gate, the shielding gate resistance Rsp is eliminated at this time, thereby avoiding the shielding gate current voltage, eliminating the voltage clamping problem introduced by the shielding, and at the same time improving the overall chip charge balance effect and electric field distribution, and reducing current concentration.

[0018] In the present invention, the structure in which the shielding gate extended portion is led out on one side of the control gate reduces the input capacitance by half and can further improve the switching speed. At the same time, compared with the scheme of leading out the extended portion on both sides, the scheme of leading out only on one side of the control gate can reduce the trench space occupied by the extended portion, which is beneficial to reducing the trench width. Or when the trench size is fixed, compared with the scheme of leading out on both the left and right sides, leading out on one side is beneficial to increasing the width of the led-out shielding gate. In this regard, on the one hand, the lower the device voltage, the narrower the gate pitch and trench width, and the scheme of leading out on one side is more suitable for low-voltage SGT devices. On the other hand, compared with the scheme of leading out on both sides, the increase in the top width of the shielding gate extended portion is beneficial to the subsequent contact hole and metal filling processes, and can alleviate the process difficulty. Description of the Drawings

[0019] Figure 1 It is a three-dimensional structure schematic diagram of a traditional SGT MOSFET in the prior art.

[0020] Figure 2 It is a top view of a conventional SGT MOSFET structure of the prior art.

[0021] Figure 3 It corresponds to Figure 2 a schematic cross-sectional view of the SGT MOSFET cell structure of the AA section in

[0022] Figure 4 It corresponds to Figure 2 a schematic cross-sectional view of the SGT MOSFET cell structure of the BB section in

[0023] Figure 5 It is a schematic structural diagram of the first embodiment of the shielded gate field effect transistor of the present invention.

[0024] Figure 6 It is a three-dimensional structural diagram of the first embodiment of the shielded gate field effect transistor of the present invention.

[0025] Figure 7 It is a schematic structural diagram of the second embodiment of the shielded gate field effect transistor of the present invention.

[0026] Figure 8 It is a schematic structural diagram of the third embodiment of the shielded gate field effect transistor of the present invention.

[0027] Figure 9 It is a schematic diagram of the manufacturing process of the first embodiment of the shielded gate field effect transistor of the present invention.

[0028] Figure 10 It is a schematic diagram of the manufacturing process of the second embodiment of the shielded gate field effect transistor of the present invention.

[0029] Figure 11 It is a simulation schematic diagram of the first embodiment of the shielded gate field effect transistor of the present invention.

[0030] Figure 12 It is the simulated electrical property result of the drain-source breakdown voltage BVDSS of the first embodiment of the shielded gate field effect transistor of the present invention, showing the curve of drain current Id - drain-source voltage Vds.

[0031] Figure 13 It is a simulation schematic diagram of the second embodiment of the shielded gate field effect transistor of the present invention.

[0032] Figure 14 It is the simulated electrical property result of the drain-source breakdown voltage BVDSS of the second embodiment of the shielded gate field effect transistor of the present invention, showing the curve of drain current Id - drain-source voltage Vds.

[0033] The reference numerals in the figure are: 101 - shielding gate, 102 - control gate, 103 - source metal, 104 - contact hole contact, 105 - interlayer dielectric ILD, 106 - N+ source region, 107 - P-type body region Pbody, 108 - N-type epitaxial layer Nepi, 109 - N-type substrate Nsub. Detailed implementation manners

[0034] The present invention provides a shield gate field effect transistor for eliminating voltage clamping. By extending the shield gate of the traditional up-and-down structure to the surface, the shield gate and the source metal are more easily contacted, thereby avoiding the potential non-uniformity caused by the too long contact distance between the shield gate and the source metal in the traditional SGT up-and-down structure, and further avoiding the clamping problem in the application, which affects the use effect, and solves the clamping problem in fast switching applications.

[0035] The implementation of the present invention will be described below with reference to the accompanying drawings.

[0036] As Figure 5 shown, the SGT of Embodiment 1 of the present invention includes a shielding gate 101, a control gate 102 and a source metal 103. The shielding gate 101 and the control gate 102 are located in the trench. The shielding gate 101 includes a gate body part and an extending part. The gate body part is located below the control gate 102. The extending part extends upward from the gate body part and is led out from the left and right sides of the control gate 102 to the top of the trench. The shielding gate 101 forms a "concave" shape. The control gate 102 is sandwiched between the extending parts. The top of the extending part is directly contacted with the source metal 103 through the configured contact hole contact 104 structure. From Figure 6 it can be seen that in the structure of Embodiment 1 of the present invention, the extending part of the shielding gate is arranged side by side with the control gate, so that the shielding gate extends to the surface of the trench. The contact hole contact structure is arranged along the top surface of the extending part, and a whole contact is opened on the extending part of the shielding gate. Compared with Figure 1 the prior art in which the contact can only be configured on the shielding gate led out from both ends, the resistance Rsp of the shielding gate is eliminated, thereby avoiding the current voltage of the shielding gate and eliminating the voltage clamping problem introduced by the shielding. Based on the conditions of a common SGT 60V device, from Figure 11 and Figure 12 the simulation results can be seen that the shielding gate structure of Embodiment 1 can achieve the lateral charge coupling effect and reach the same blocking effect as the traditional SGT. The above Embodiment 1 of the present invention describes the main structural features of the field effect transistor. The finished product of the shield gate field effect transistor of the present invention mainly includes a shielding gate, a control gate and a source metal, and also includes the structures of a conventional shield gate field effect transistor such as gate oxide, field oxide, P+ region, N+ region, dielectric layer, passivation layer, etc.

[0037] As Figure 9The following is a schematic diagram of the preparation process of Example 1.

[0038] 1) Prepare the wafer original;

[0039] 2) Trench etching, growing an oxide layer in the trench;

[0040] 3) etching the oxide layer to form a first trench, and filling the first trench with polysilicon to form a shield gate;

[0041] 4) Etching the shield gate to a certain depth to form a second trench. During etching, a certain width of the shield gate is retained on both sides to form an extension portion. The unetched portion forms the gate body, and the shield gate is formed into a "concave" shape. The certain width is retained according to the process conditions, and the width and depth of the second trench are set according to the size parameters of the control gate;

[0042] 5) Depositing an oxide layer in the second trench etched in step 4) and then etching the oxide layer to form a fill space for the control gate and a gate oxide layer. After filling with gate polysilicon, the control gate is formed. Subsequent electrode processing for the shielded gate field-effect transistor is then performed to obtain the shielded gate field-effect transistor with voltage clamping eliminated. For example, after forming the shield gate and control gate, the process is followed by P+ implantation and annealing, N+ implantation and annealing, interlayer oxide deposition, contact hole formation (electrode the oxide layer and Si), metal filling, and passivation layer deposition, ultimately resulting in a complete SGT.

[0043] Among them, when preparing the extension part, due to the limited width of the trench, space for the control gate must be left, and the width of the shield gate drawn out must be divided into two sides, which is relatively narrow, and has high requirements for filling, etching and packaging processes, such as Figure 11 As shown in the expanded diagram, under the two-side lead-out solution, the width of the top side of the extended part is 0.14um~0.16um, which places high requirements on the process.

[0044] The structure of the first embodiment can eliminate the problem of clamping voltage, but due to the large overlap area between the control gate and the shield gate extensions on both sides, a large input capacitance is introduced, which can easily cause the gate to be turned on by mistake. The present invention further proposes a single-side lead-out solution, and proposes the second and third embodiments. Figure 7 and Figure 8 As shown, the extension portion of the shield gate 101 extends upward from the gate body portion and is led out from the left or right side of the control gate 102. The top of the extension portion is directly in contact with the source metal 103 through a contact hole contact104 structure.

[0045] The preparation process of Examples 2 and 3 is as follows Figure 10 As shown, the following steps are included:

[0046] 1) Prepare the wafer original;

[0047] 2) Trench etching is performed, and an oxide layer is grown in the trench;

[0048] 3) The oxide layer is etched to form a first trench, and polysilicon is filled in the first trench to form a shielding gate;

[0049] 4) The shielding gate is etched to a certain depth to form a second trench. During etching, a certain width of the shielding gate is reserved on one side, and on the opposite side, it is etched to the oxide layer in step 2) to form an extended portion extending unidirectionally. The unetched portion at the lower part forms a gate body portion. The certain width is reserved according to the process conditions, and the width and depth of the second trench are set according to the size parameters of the control gate;

[0050] 5) An oxide layer is deposited on the second trench obtained by etching in step 4), and then the oxide layer is etched to form a filling space for the control gate and a gate oxide layer. After filling the gate polysilicon, the control gate is obtained. Then, through the subsequent electrode process of the shielding gate field effect transistor, the shielding gate field effect transistor with eliminated voltage clamping is obtained. For example, after preparing the shielding gate and the control gate, then through P+ implantation and annealing → N+ implantation and annealing → interlayer oxide layer deposition → making contact holes (etching the oxide layer and Si) → filling metal → depositing a passivation layer, finally a complete SGT is obtained.

[0051] Compared with the structure of Embodiment 1, the structures of the unidirectional extended portions in Embodiments 2 and 3 reduce the input capacitance by half, and can further improve the switching speed. At the same time, the extended shielding gate is placed on one side of the control gate, which is beneficial to increasing the width of the extended shielding gate. For example, Figure 13 , on the one hand, it is more suitable for low-voltage SGT devices. On the other hand, since only unidirectional extension is required, under the limited trench width, the increased width of the top of the shielding gate can alleviate the process difficulties of subsequent contact hole and metal filling. Compared with Embodiment 1, the requirements for subsequent filling, etching, and packaging processes of the SGT device can be reduced. At the same time, based on the conditions of ordinary SGT60V devices, such as Figure 14 it can be seen that the unidirectional extension scheme can also achieve the effect of lateral charge coupling and reach the same blocking effect as the traditional SGT.

[0052] Figure 11 and Figure 13 also shows the strength of the device impact ionization rate, which is represented by color. The impact ionization rate is the number of electron-hole pairs generated by carrier impact ionization per unit distance. Impact ionization occurs when the electric field in the semiconductor junction is strong enough, and electrons or holes obtain sufficient kinetic energy to excite valence band electrons to the conduction band through collision, forming electron-hole pairs. This process will cause the avalanche multiplication effect and affect the breakdown voltage of the power device. The improved design of the SGT structure of the present invention does not affect the device impact ionization situation, and the impact ionization situation is similar to that of the traditional SGT.

[0053] Furthermore, under the condition of meeting the space required for the control gate and achievable by the process, the wider the top width of the extended part of the present invention, the more beneficial it is to the subsequent contact hole preparation process. Preferably, as large a width as possible is retained during preparation.

[0054] For the design of the shield gate field effect transistor of the present invention, leading out the shield gate can reduce the clamping problem caused by potential non-uniformity, and can avoid abnormalities in fast switching applications, affecting the terminal use effect. The present invention can eliminate the influence of voltage clamping under the condition of achieving the same lateral charge coupling effect as the traditional SGT.

Claims

1. A shield gate field effect transistor for eliminating voltage clamping, characterized in that It includes a shielding gate, a control gate and a source metal. The shielding gate and the control gate are located in a trench. The shielding gate includes a gate body part and an extending part. The gate body part is located below the control gate. The extending part extends upward from the gate body part and leads out to the top of the trench from the left and right sides of the control gate. The shielding gate forms a "concave" shape. The control gate is sandwiched in the middle of the extending part. The top of the extending part contacts the source metal through a configured contact hole contact structure. The extending part of the shielding gate is arranged side by side with the control gate. The contact hole contact structure is arranged along the top surface of the extending part and presents as a long strip arranged side by side.

2. The depletion-mode shield-gate field-effect transistor according to claim 1, wherein The extending part extends upward from the gate body part and leads out to the top of the trench from one side of the left or right side of the control gate. The top of the extending part contacts the source metal through a configured contact hole contact structure. The extending part of the shielding gate is arranged side by side with the control gate. The contact hole contact structure is arranged along the top surface of the extending part and presents as a long strip arranged side by side.

3. The manufacturing method of a shield gate field effect transistor for eliminating voltage clamping according to claim 1 or 2, characterized in that It includes the following steps: 1) Prepare a wafer blank; 2) Etch the trench and grow an oxide layer in the trench; 3) Etch the oxide layer to form a first trench and fill polysilicon in the first trench to form a shielding gate; 4) Etch the shielding gate to form a second trench. When etching, retain the shielding gate on the left and right sides or one side to form an extending part, and the unetched part forms a gate body part; 5) Deposit an oxide layer on the second trench etched in step 4), then etch the oxide layer to form a filling space for the control gate and a gate oxide layer. After filling gate polysilicon, a control gate is obtained. Then, through the subsequent electrode process of the shielding gate field effect transistor, the shielding gate field effect transistor with voltage clamping eliminated is obtained.

4. The manufacturing method of the shield gate field effect transistor for eliminating voltage clamping according to claim 3, characterized in that The extending part of the shielding gate and the control gate form a side-by-side structure in the trench. Under the condition of meeting the required space for the control gate, the top width of the extending part retains the largest possible width to facilitate the preparation process of the contact hole.

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