Semiconductor device and manufacturing method, power module, power conversion circuit and vehicle

Abstract

The present invention discloses a semiconductor device and a manufacturing method, a power module, a power conversion circuit, and a vehicle. The semiconductor device includes a first semiconductor body, a first region disposed on a first surface, and a well region disposed on a side of the first region away from the first surface; the first region and the well region have opposite conductivity types; a second semiconductor body partially covering the first region and the well region; a gate structure disposed on the first surface or extending from the first surface into the first semiconductor body; the gate structure includes a gate oxide layer and a gate, the gate oxide layer being disposed on a side of the second semiconductor body away from the first semiconductor body and covering a side surface of the second semiconductor body, the gate being disposed on a side of the gate oxide layer away from the second semiconductor body; a source electrode disposed on the first surface; and a drain electrode disposed on the second surface. The present invention improves the flatness of the channel surface and enhances the conductivity of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] In recent years, silicon carbide device products have been continuously developing towards smaller cell size, lower on-resistance, lower switching loss and higher reliability. For example, the planar gate structure of silicon carbide metal-oxide field-effect transistor (MOSFET) has the characteristics of simple process, good crystal orientation consistency of the conduction channel, and relatively high avalanche energy, and has always occupied the mainstream.

[0003] At present, the planar gate structure of the silicon carbide metal-oxide field-effect transistor has a first region and a well region. Since the first region is a heavily doped region, the silicon carbide oxidation rate on the surface of the first region is fast during the gate oxidation process. The well region is a lightly doped region, and the silicon carbide oxidation rate on the surface of the well region is slow, resulting in inconsistent surface heights between the first region and the well region, poor channel flatness, and affecting the electrical properties of the silicon carbide MOSFET. Summary of the Invention

[0004] The present invention provides a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, so as to increase the flatness of the channel surface and improve the conductive performance of the semiconductor device.

[0005] According to one aspect of the present invention, an embodiment of the present invention provides a semiconductor device, including:

[0006] a first semiconductor body comprising a first surface and a second surface disposed opposite to each other, the first semiconductor body further comprising a well region and a first region, the first region being disposed on the first surface, the well region being disposed on a side of the first region away from the first surface, the first region and the well region being of opposite conductivity types; and a second semiconductor body, the second semiconductor body partially covering the first region and the well region.

[0007] a gate structure, the gate structure being located on the first surface or extending from the first surface into the first semiconductor body; the gate structure comprising a gate oxide layer and a gate, the gate oxide layer being located on a side of the second semiconductor body away from the first semiconductor body and covering a side surface of the second semiconductor body, and the gate being located on a side of the gate oxide layer away from the second semiconductor body;

[0008] a source electrode, located on the first surface;

[0009] The drain is located on the second surface.

[0010] Optionally, the second semiconductor body is located on the first surface;

[0011] The gate structure is located on a side of the second semiconductor body away from the first surface.

[0012] Optionally, a gate trench is provided on the first surface, and the gate trench extends from the first surface into the first semiconductor body;

[0013] The second semiconductor body is located on the sidewalls and bottom surface of the gate trench;

[0014] The gate structure is located in the gate trench, wherein the gate oxide layer is located on the side of the second semiconductor body in the gate trench away from the first semiconductor body and the bottom surface of the gate trench, and the gate is located on the side of the gate oxide layer in the gate trench away from the first semiconductor body.

[0015] Optionally, the first semiconductor body includes a silicon carbide semiconductor body, and the second semiconductor body includes a silicon carbide semiconductor body.

[0016] Optionally, the doping concentration of the second semiconductor body is lower than the doping concentration of the first region;

[0017] The doping type of the second semiconductor body is the same as the doping type of the well region.

[0018] According to another aspect of the present invention, an embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising:

[0019] A first semiconductor body is provided; wherein the first semiconductor body includes a first surface and a second surface disposed opposite to each other, and further includes a well region and a first region, wherein the first region is disposed on the first surface, and the well region is disposed on a side of the first region away from the first surface; and the first region and the well region have opposite conductivity types;

[0020] forming a second semiconductor body, wherein the second semiconductor body covers a portion of the first region and the well region;

[0021] A gate structure is formed on the first surface, the gate structure being located on the first surface or extending from the first surface into the semiconductor body; the gate structure comprising a gate oxide layer and a gate, the gate oxide layer being located on a side of the second semiconductor body away from the first semiconductor body and covering a side surface of the second semiconductor body, and the gate being located on a side of the gate oxide layer away from the second semiconductor body;

[0022] forming a source electrode on one side of the first surface;

[0023] A drain electrode is formed on the second surface side.

[0024] Optionally, forming the second semiconductor body and forming the gate structure on the first surface includes: forming the second semiconductor body on the first surface, the second semiconductor body covering a portion of the first region and the well region;

[0025] forming a gate oxide layer on a side of the second semiconductor body away from the first semiconductor body and on a side surface of the second semiconductor body;

[0026] A gate is formed on a side of the gate oxide layer away from the second semiconductor body.

[0027] Optionally, forming the second semiconductor body and forming the gate structure on the first surface includes:

[0028] forming a gate trench on the first surface, wherein the gate trench extends from the first surface into the first semiconductor body;

[0029] forming a second semiconductor body on sidewalls of the gate trench;

[0030] forming a gate oxide layer on a side of the second semiconductor body in the gate trench away from the first semiconductor body and on a bottom surface of the gate trench;

[0031] A gate is formed on a side of the gate oxide layer in the gate trench away from the first semiconductor body.

[0032] Optionally, providing the first semiconductor body includes:

[0033] Providing a silicon carbide semiconductor body;

[0034] Forming the second semiconductor body includes:

[0035] A silicon carbide semiconductor body is formed.

[0036] Optionally, forming the second semiconductor body includes:

[0037] A second semiconductor body is formed, the doping concentration of which is lower than the doping concentration of the first region and the doping type of which is the same as the doping type of the well region.

[0038] According to another aspect of the present invention, an embodiment of the present invention provides a power module, including a substrate and at least one semiconductor device provided by an embodiment of the present invention, wherein the substrate is used to support the semiconductor device.

[0039] According to another aspect of the present invention, an embodiment of the present invention provides a power conversion circuit, the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction;

[0040] The power conversion circuit includes a circuit board and at least one semiconductor device provided by an embodiment of the present invention, wherein the semiconductor device is electrically connected to the circuit board.

[0041] In an embodiment of the present invention, the second semiconductor body is located on the first surface, and the first semiconductor body covers a portion of the first region and the well region. The second semiconductor body is used to oxidize a portion of the second semiconductor body through a thermal oxidation process during the oxidation process, while also forming a gate oxide layer on the side of the second semiconductor body away from the first surface. There is no need to consume the first region and the well region, thereby ensuring that the silicon carbide oxidation rates on the surfaces of the first region and the well region are consistent, and avoiding the height inconsistency between the surface of the first region and the surface of the well region due to different doping concentrations in the first region and the well region, thereby improving the flatness of the channel surface and improving the conductivity of the semiconductor device.

[0042] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0044] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0045] Figure 2 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0046] Figure 3 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0047] Figure 4 yes Figure 3 Schematic diagram of the structure corresponding to step S110;

[0048] Figure 5 is a schematic structural diagram of a well region formed on a first surface of a first semiconductor provided by an embodiment of the present invention;

[0049] Figure 6 is a schematic structural diagram of a first region formed on a first surface of a first semiconductor provided by an embodiment of the present invention;

[0050] Figure 7 is a schematic structural diagram of forming a third mask plate on the first area according to an embodiment of the present invention;

[0051] Figure 8 yes Figure 3Schematic diagram of the structure corresponding to step S120;

[0052] Figure 9 is a structural schematic diagram of removing the third mask provided by an embodiment of the present invention;

[0053] Figure 10 is a schematic structural diagram of forming a gate oxide layer on a side of the first region away from the first surface provided by an embodiment of the present invention;

[0054] Figure 11 yes Figure 3 Schematic diagram of the structure corresponding to step S130;

[0055] Figure 12 is a schematic structural diagram of forming an interlayer insulating layer on a side of the gate away from the first surface, provided by an embodiment of the present invention;

[0056] Figure 13 yes Figure 3 Schematic diagram of the structure corresponding to step S140;

[0057] Figure 14 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0058] Figure 15 is a flow chart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0059] Figure 16 This is a flow chart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0060] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0061] It should be noted that the terms "first," "second," and the like in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the numbers used in this manner are interchangeable where appropriate so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, any variations of the terms "including" and "having" are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatus.

[0062] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention, Figure 2 is a structural diagram of another semiconductor device provided by an embodiment of the present invention, Figure 1 shows a planar gate structure of a semiconductor device, Figure 2 A trench gate structure of a semiconductor device is shown. Figure 1 and Figure 2 The semiconductor device includes: a first semiconductor body 1, including a first surface 101 and a second surface 102 arranged opposite to each other, the first semiconductor body 1 also including a well region 15 and a first region 14, the first region 14 is arranged on the first surface 101, and the well region 15 is arranged on a side of the first region 14 away from the first surface 101; the first region 14 and the well region 15 have opposite conductivity types; a second semiconductor body 2, the second semiconductor body 2 partially covering the first region 14 and the well region 15; a gate structure 3, the gate structure 3 is located on the first surface 101 or extends from the first surface 101 into the first semiconductor body 1; the gate structure 3 includes a gate oxide layer 30 and a gate 31, the gate oxide layer 30 is located on a side of the second semiconductor body 2 away from the first semiconductor body 1 and covers a side surface of the second semiconductor body 2, and the gate 31 is located on a side of the gate oxide layer 30 away from the second semiconductor body 2; a source electrode 4 is located on the first surface 101; and a drain electrode 5 is located on the second surface 102.

[0063] The first semiconductor body 1 includes a substrate 11 and an epitaxial layer 12. In some embodiments of the present invention, the first semiconductor body 1 may also include only the epitaxial layer 12. In other embodiments of the present invention, the first semiconductor body 1 may also include a substrate 11 and a semiconductor layer formed by other processes. The epitaxial layer 12 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 11, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE). The second semiconductor body 2 includes an epitaxial layer, which is a semiconductor layer formed by a single epitaxial process on the basis of the first semiconductor body 1.

[0064] In an embodiment of the present invention, the MOSFET semiconductor device includes an N-type MOSFET semiconductor device or a P-type MOSFET semiconductor device. Taking the N-type MOSFET semiconductor device as an example, the first semiconductor body 1 is an N-type semiconductor body, the first region 14 is an N+ doped region, the second region 13 is a P+ doped region, and the well region 15 is a P-well region. In other optional embodiments of the present invention, the first semiconductor body 1 also includes a second region 13, the second region 13 is connected to the first region 14, the second region 13 and the well region 15 have the same conductivity type, the doping concentration of the second region 13 is greater than the doping concentration of the well region 15, and the second region 13 is located on the first surface 101, which can form a better ohmic contact with the first semiconductor body 1. Taking the N-type MOSFET semiconductor device as an example, the second region 13 includes a P+ doped region.

[0065] In other optional embodiments of the present invention, an interlayer insulating layer 32 is further provided to insulate the gate 31 and the source 4 .

[0066] in, Figure 1 The middle gate structure 3 is located on the first surface 101, the second semiconductor body 2 covers part of the first region 14 and the well region 15, and the gate oxide layer 30 is located on the side of the second semiconductor body 2 away from the first semiconductor body 1 and covers the side surface of the second semiconductor body 2, thereby improving the flatness of the planar channel on the surface of the well region 15. Figure 2 The middle gate structure 3 extends from the first surface 101 into the first semiconductor body 1, the second semiconductor body 2 covers part of the first region 14 and the well region 15, and the gate oxide layer 30 is located on the side of the second semiconductor body 2 away from the first semiconductor body 1 and covers the side surface of the second semiconductor body 2, thereby improving the flatness of the vertical channel on the surface of the well region 15.

[0067] In the semiconductor device provided by an embodiment of the present invention, the second semiconductor body 2 is located on one side of the first surface 101 and covers the well region 15 and a portion of the first region 14, so that the well region 15 and a portion of the first region 14 are protected by the second semiconductor body 2. In the process of forming the gate oxide layer 30, a portion of the silicon in the second semiconductor body 2 is consumed through a thermal oxidation process to form the gate oxide layer 30, and there is no need to consume the silicon in the first region 14 and the well region 15. This ensures that the silicon carbide oxidation rate on the surfaces of the first region 14 and the well region 15 is consistent, and avoids the height inconsistency between the surface of the first region 14 and the surface of the well region 15 due to the different doping concentrations of the first region 14 and the well region 15, thereby improving the flatness of the channel on the surface of the well region 15, thereby reducing the on-resistance of the semiconductor device.

[0068] See also Figure 1 Optionally, based on the above embodiment, the second semiconductor body 2 is located on the first surface 101 ; the gate structure 3 is located on a side of the second semiconductor body 2 away from the first surface 101 .

[0069] Figure 1 The middle gate structure 3 is located on the first surface 101, the second semiconductor body 2 covers part of the first region 14 and the well region 15, and the gate oxide layer 30 is located on the side of the second semiconductor body 2 away from the first semiconductor body 1 and covers the side surface of the second semiconductor body 2, thereby improving the flatness of the planar channel on the surface of the well region 15.

[0070] See also Figure 2 Optionally, based on the above embodiment, a gate trench 19 is provided on the first surface 101, and the gate trench 19 extends from the first surface 101 into the first semiconductor body 1; the second semiconductor body 2 covers the first region 14 and the well region 15 located on the sidewall of the gate trench 19; the gate structure 3 is located in the gate trench 19, wherein the gate oxide layer 30 is located in the gate trench 19 on the side of the second semiconductor body 2 away from the first semiconductor body 1 and the bottom surface of the gate trench 19, and the gate 31 is located in the gate trench 19 on the side of the gate oxide layer 30 away from the first semiconductor body 1.

[0071] Figure 2 In the figure, the gate structure 3 extends from the first surface 101 into the first semiconductor body 1, the second semiconductor body 2 covers the first region 14 and the well region 15 located on the sidewall of the gate trench 19, and the gate oxide layer 30 is located on the side of the second semiconductor body 2 away from the first semiconductor body 1 and covers the side of the second semiconductor body 2, thereby improving the flatness of the vertical channel on the surface of the well region 15.

[0072] See also Figure 1 or Figure 2Optionally, based on the above embodiment, the first semiconductor body 1 includes a silicon carbide semiconductor body, and the second semiconductor body 2 includes a silicon carbide semiconductor body.

[0073] Specifically, the first semiconductor body 1 includes a silicon carbide semiconductor body, and the second semiconductor body 2 includes a silicon carbide semiconductor body. The corresponding silicon carbide metal-oxide field effect transistor semiconductor device has wide bandgap width, high critical breakdown field strength, high thermal conductivity and high carrier saturation rate characteristics, and the silicon carbide metal-oxide field effect transistor semiconductor device has high voltage resistance, low on-resistance and high stability.

[0074] See also Figure 1 or Figure 2 Optionally, based on the above embodiment, the doping concentration of the second semiconductor body 2 is less than the doping concentration of the first region 14 ; the doping type of the second semiconductor body 2 is the same as the doping type of the well region 15 .

[0075] In the embodiment of the present invention, by setting the doping concentration of the second semiconductor body 2 to be lower than the doping concentration of the first region 14, the slow switching state transition of the semiconductor device due to the excessively high doping concentration of the second semiconductor body 2 is avoided, thereby improving the transient response of the switch of the semiconductor device.

[0076] Figure 3 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention, see Figure 3 , an embodiment of the present invention provides a method for manufacturing a semiconductor device, the specific steps of which are as follows:

[0077] S110 , providing a first semiconductor body.

[0078] For details, see Figure 4 , forming an epitaxial layer 12 on the substrate 11 by an epitaxial process, patterning the first surface 101, and forming a second region 13 on the first surface 101 by an ion implantation process, see Figure 5 A first mask plate 16 is formed on the first surface 101 by a physical vapor deposition process or a chemical vapor deposition process, and the first surface 101 is patterned. A well region 15 is formed on the first surface 101 by an ion implantation process.

[0079] See also Figure 6A second mask 17 is formed on both sides of the first mask 16 and on the side of the second region 13 away from the first surface 101 by physical vapor deposition or chemical vapor deposition. An ion implantation process is then performed to form the first region 14 on the side of the well region 15 closer to the first surface 101. The first region 14 and the well region 15 have opposite conductivity types. The first and second masks 16 and 17 are removed by a wet etching process or an etching process, followed by a high-temperature annealing process to activate the implanted ions and repair the crystal lattice.

[0080] S120 , forming a second semiconductor body.

[0081] The process of the second semiconductor body 2 covering a portion of the first region 14 and the well region 15 is as follows:

[0082] See also Figure 7 , a third mask plate 18 is formed on a portion of the first region 14 by a physical vapor deposition process or a chemical vapor deposition process. Figure 8 , a second semiconductor body 2 is formed in the area where the third mask plate 18 does not cover the first surface 101 by an epitaxial process, see Figure 9 , the third mask plate 18 is removed by using a wet etching process or an etching process.

[0083] S130 , forming a gate structure on the first surface.

[0084] For details, see Figure 10 A gate oxide layer 30 is formed on the second semiconductor body 2 and the side of the first region 14 away from the first surface 101 by a thermal oxidation process. Figure 11 , a gate 31 is formed on a side of the gate oxide layer 30 away from the second semiconductor body 2 by a physical vapor deposition process or a chemical vapor deposition process, and the gate 31 is patterned, see Figure 12 An interlayer insulating layer 32 is formed on a side of the gate 31 away from the first surface 101 , wherein the interlayer insulating layer 32 covers the gate 31 .

[0085] S140 , forming a source electrode on one side of the first surface.

[0086] See also Figure 12 , a portion of the gate oxide layer 30 located in the first region 14 is etched by an etching process, and the source ohmic contact region is exposed on the first surface 101, see Figure 13 The source electrode 4 is formed on the first surface 101 side and the side of the gate structure 3 away from the first surface 101 by metal sputtering or metal lift-off process.

[0087] S150 , forming a drain on one side of the second surface.

[0088] See also Figure 1 , a drain electrode 5 is formed on one side of the second surface 102 by a metal sputtering process.

[0089] In an embodiment of the present invention, the second semiconductor body is located on the first surface, and the first semiconductor body covers a portion of the first region and the well region. The second semiconductor body is used to oxidize a portion of the second semiconductor body through a thermal oxidation process during the oxidation process, while also forming a gate oxide layer on the side of the second semiconductor body away from the first surface. There is no need to consume the first region and the well region, thereby ensuring that the silicon carbide oxidation rates on the surfaces of the first region and the well region are consistent, and avoiding the height inconsistency between the surface of the first region and the surface of the well region due to different doping concentrations in the first region and the well region, thereby improving the flatness of the channel surface and improving the conductivity of the semiconductor device.

[0090] Optionally, based on the above embodiment, providing the first semiconductor body includes: providing a silicon carbide semiconductor body; and forming the second semiconductor body includes: forming a silicon carbide semiconductor body.

[0091] Figure 14 This is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention. Figure 3 The semiconductor device manufacturing method shown is based on forming a second semiconductor body on a first surface, such as Figure 14 As shown, the specific steps of the method for preparing the semiconductor device are as follows:

[0092] S210 , providing a first semiconductor body.

[0093] S220 , forming a second semiconductor body on the first surface.

[0094] S230 , forming a gate oxide layer on a side of the second semiconductor body away from the first semiconductor body and on a side surface of the second semiconductor body.

[0095] S240 , forming a gate on a side of the gate oxide layer away from the second semiconductor body.

[0096] S250 , forming a source electrode on one side of the first surface.

[0097] S260 , forming a drain on one side of the second surface.

[0098] The preparation process and effects of S210-S260 refer to S110-S150 and will not be repeated here.

[0099] Figure 15 This is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention. Figure 14 The semiconductor device manufacturing method shown is based on forming a second semiconductor body on the first surface and the sidewalls and bottom of the gate trench, as Figure 15As shown, the specific steps of the method for preparing the semiconductor device are as follows:

[0100] S310 , providing a first semiconductor body.

[0101] The preparation process and effect of S310 refer to S210 and will not be described in detail here.

[0102] S320 , forming a gate trench on the first surface.

[0103] Among them, see Figure 2 A gate trench 19 is formed on the first surface 101 by an etching process, and the gate trench 19 extends from the first surface 101 into the first semiconductor body 1 .

[0104] S330 , forming a second semiconductor body on the sidewalls and bottom of the gate trench.

[0105] See also Figure 2 A third mask is formed on a portion of the first region 14 by a physical vapor deposition process or a chemical vapor deposition process, a second semiconductor body 2 is formed in the gate trench 19 and in the area where the third mask does not cover the first surface 101, and the third mask is removed by a wet etching process or an etching process.

[0106] S340 , forming a gate oxide layer on a side of the second semiconductor body in the gate trench away from the first semiconductor body and on a bottom surface of the gate trench.

[0107] See also Figure 2 A gate oxide layer 30 is formed in the gate trench 19 and on a side of the first region 14 away from the substrate 11 by a thermal oxidation process.

[0108] S350 , forming a gate on a side of the gate oxide layer in the gate trench away from the first semiconductor body.

[0109] See also Figure 2 A gate 31 is formed on a side of the gate oxide layer 30 in the gate trench 19 away from the first semiconductor body 1. The gate 31 may be a polysilicon gate.

[0110] S360 , forming a source electrode on one side of the first surface.

[0111] S370 , forming a drain on one side of the second surface.

[0112] The preparation process and effects of S360-S370 refer to S250-S260 and will not be repeated here.

[0113] Figure 16 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention. Figure 14Based on the method for preparing the semiconductor device shown, a second semiconductor body is formed, which has a doping concentration lower than that of the first region and a doping type identical to that of the well region. Figure 16 As shown, the specific steps of the method for preparing the semiconductor device are as follows:

[0114] S210 , providing a first semiconductor body.

[0115] S2101 , forming a second semiconductor body having a doping concentration lower than that of the first region and a doping type the same as that of the well region.

[0116] S130 , forming a gate structure on the first surface.

[0117] S140 , forming a source electrode on one side of the first surface.

[0118] S150 , forming a drain on one side of the second surface.

[0119] The method for preparing the semiconductor device of the embodiment of the present invention and the semiconductor device provided by any embodiment of the present invention belong to the same inventive concept and have corresponding beneficial effects. For technical details not detailed in this embodiment, please refer to the semiconductor device provided by any embodiment of the present invention.

[0120] An embodiment of the present invention provides a power module comprising a substrate and at least one semiconductor device according to any embodiment of the present invention, wherein the substrate is configured to support the semiconductor device. Therefore, the beneficial effects of the power module including the semiconductor device according to any embodiment of the present invention are not further elaborated here.

[0121] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device described in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0122] Therefore, the power conversion circuit includes the beneficial effects of the semiconductor device described in any embodiment of the present invention, which will not be repeated here.

[0123] An embodiment of the present invention further provides a vehicle, comprising a load and the power conversion circuit described in any embodiment of the present invention, wherein the power conversion circuit is used to convert AC and / or DC power into AC and / or DC power and then input the converted power into the load.

[0124] Therefore, the vehicle includes the power conversion circuit of any embodiment of the present invention. Therefore, the beneficial effects of the vehicle including the power conversion circuit described in any embodiment of the present invention are not repeated here.

[0125] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0126] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A first semiconductor body comprising a first surface and a second surface disposed opposite to each other, the first semiconductor body further comprising a well region and a first region, the first region being disposed on the first surface, the well region being disposed on a side of the first region away from the first surface; the first region and the well region having opposite conductivity types; a second semiconductor body, wherein the second semiconductor body covers a portion of the first region and the well region; a gate structure, the gate structure being located on the first surface or extending from the first surface into the first semiconductor body; the gate structure comprising a gate oxide layer and a gate, the gate oxide layer being located on a side of the second semiconductor body away from the first semiconductor body and covering a side surface of the second semiconductor body, and the gate being located on a side of the gate oxide layer away from the second semiconductor body; a source electrode, located on the first surface; a drain electrode, located on the second surface; The doping concentration of the second semiconductor body is lower than the doping concentration of the first region; The doping type of the second semiconductor body is the same as the doping type of the well region.

2. The semiconductor device according to claim 1, wherein The second semiconductor body is located on the first surface; The gate structure is located on a side of the second semiconductor body away from the first surface.

3. The semiconductor device according to claim 1, wherein The first surface is provided with a gate trench, and the gate trench extends from the first surface into the first semiconductor body; The second semiconductor body covers the first region and the well region located on the sidewall of the gate trench; The gate structure is located in the gate trench, wherein the gate oxide layer is located on a side of the second semiconductor body in the gate trench away from the first semiconductor body and on the bottom surface of the gate trench, and the gate is located on a side of the gate oxide layer in the gate trench away from the first semiconductor body.

4. The semiconductor device according to claim 1, wherein The first semiconductor body includes a silicon carbide semiconductor body, and the second semiconductor body includes a silicon carbide semiconductor body.

5. A method for preparing a semiconductor device, characterized in that: include: A first semiconductor body is provided; wherein the first semiconductor body includes a first surface and a second surface disposed opposite to each other, the first semiconductor body further including a well region and a first region, the first region being disposed on the first surface, the well region being disposed on a side of the first region away from the first surface; the first region and the well region having opposite conductivity types; forming a second semiconductor body, wherein the second semiconductor body covers a portion of the first region and the well region; forming the second semiconductor body includes: forming a second semiconductor body with a doping concentration lower than that of the first region and a doping type the same as that of the well region; forming a gate structure on the first surface, the gate structure being located on the first surface or extending from the first surface into the semiconductor body; the gate structure comprising a gate oxide layer and a gate, the gate oxide layer being located on a side of the second semiconductor body away from the first semiconductor body and covering a side surface of the second semiconductor body, and the gate being located on a side of the gate oxide layer away from the second semiconductor body; forming a source electrode on one side of the first surface; A drain electrode is formed on one side of the second surface.

6. The method for preparing a semiconductor device according to claim 5, wherein: Forming a second semiconductor body and forming a gate structure on the first surface includes: forming a second semiconductor body on the first surface, wherein the second semiconductor body covers a portion of the first region and the well region; forming a gate oxide layer on a side of the second semiconductor body away from the first semiconductor body and on a side surface of the second semiconductor body; A gate is formed on a side of the gate oxide layer away from the second semiconductor body.

7. The method for preparing a semiconductor device according to claim 5, wherein: Forming the second semiconductor body and forming a gate structure on the first surface includes: forming a gate trench on the first surface, wherein the gate trench extends from the first surface into the first semiconductor body; forming a second semiconductor body on the sidewall of the gate trench, wherein the second semiconductor body covers the first region and the well region located on the sidewall of the gate trench; forming a gate oxide layer on a side of the second semiconductor body in the gate trench away from the first semiconductor body and on a bottom surface of the gate trench; A gate is formed on a side of the gate oxide layer in the gate trench away from the first semiconductor body.

8. The method for preparing a semiconductor device according to claim 5, wherein: Providing a first semiconductor body includes: Providing a silicon carbide semiconductor body; Forming the second semiconductor body includes: A silicon carbide semiconductor body is formed.

9. A power module, characterized in that: The invention comprises a substrate and a semiconductor device according to any one of claims 1 to 4, wherein the substrate is used for carrying the semiconductor device.

10. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1 to 4, wherein the semiconductor device is electrically connected to the circuit board.

11. A vehicle, characterized in that: The invention comprises a load and a power conversion circuit as claimed in claim 10, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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