Two-dimensional semiconductor transistor and preparation method thereof

Abstract

The invention relates to the field of electronic devices, in particular to a two-dimensional semiconductor transistor and a preparation method thereof. The two-dimensional semiconductor transistor comprises a substrate, a two-dimensional semiconductor layer, a semi-metal layer and a metal covering layer, the two-dimensional semiconductor layer, the semi-metal layer and the metal covering layer are sequentially arranged on the substrate, the semi-metal layer is made of bismuth or antimony, and the metal covering layer is made of gold; wherein when the material of the semimetal layer is bismuth, the thickness ratio of the semimetal layer to the metal covering layer is greater than 1.05: 1; when the semi-metal layer is made of antimony, the thickness ratio of the semi-metal layer to the metal covering layer is larger than 3.58: 1. By designing the thickness ratio between the semimetal layer and the gold covering layer, atoms of the semimetal layer are in an excessive state, so that after the device is subjected to heat treatment, the semimetal layer is still reserved after the interface alloying reaction of the semimetal layer and the gold covering layer; and the contact of the device can still maintain the contact interface of the semi-metal Bi / Sb-two-dimensional semiconductor material, so that the thermal stability of the two-dimensional semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to the field of electronic devices, and in particular to a two-dimensional semiconductor transistor and a preparation method thereof. Background Art

[0002] Semimetals (bismuth Bi and antimony Sb) can form good ohmic contacts with two-dimensional semiconductors, becoming ideal contact materials for high-performance two-dimensional semiconductor transistors. Patent application CN115064588A proposes depositing semimetal Sb or alloys containing semimetal Sb on a two-dimensional semiconductor layer to form an ohmic contact structure. Semimetal Sb as a contact electrode has strong van der Waals interaction and energy band hybridization with the two-dimensional semiconductor, realizing barrier-free carrier transmission at the contact interface; Sb has a high melting point and stability, which can enhance the reliability and stability of the device.

[0003] However, since the semi-metal (Bi and Sb) has low conductivity and is easily oxidized, in order to reduce the parasitic resistance caused by low conductivity and prevent device oxidation, an excess of gold covering layer with higher conductivity is usually evaporated on the semi-metal material to form a two-dimensional semiconductor-semi-metal-gold stacking structure. Previous studies have found that such a two-dimensional semiconductor-semi-metal-gold stacking structure has poor thermal stability. After heat treatment, the semi-metal contact performance of the device will decrease. X-ray diffraction experiments have found that the two-dimensional semiconductor-Bi-Au and two-dimensional semiconductor-Sb-Au stacking structures will undergo alloying reactions during heat treatment. The semi-metal layer and the excess gold covering layer will undergo alloying reactions to become Au2Bi or AuSb2, and there will be no excess semi-metal. This causes the semi-metal Bi / Sb-two-dimensional semiconductor contact interface to become Au2Bi / AuSb2-two-dimensional semiconductor contact interface, and the ohmic contact between the two-dimensional semiconductor material and the semi-metal is destroyed. Two-dimensional semiconductor devices usually need to go through many process flows including heat treatment steps, so it is necessary to solve the problem of poor thermal stability of two-dimensional semiconductor devices caused by the gold covering layer (Au) easily alloying with the semi-metal layer (Bi and Sb). Summary of the invention

[0004] In view of the above-mentioned deficiencies in the prior art, the object of the present invention is to provide a two-dimensional semiconductor transistor and a method for preparing the same, aiming to solve the problem of poor thermal stability of two-dimensional semiconductor devices caused by the existing gold covering layer (Au) being easily alloyed with the semi-metal layer (Bi and Sb).

[0005] The technical solution of the present invention is as follows:

[0006] A first aspect of the present invention provides a two-dimensional semiconductor transistor, comprising:

[0007] A substrate, a two-dimensional semiconductor layer, a semi-metal layer and a metal covering layer sequentially arranged on the substrate, wherein the semi-metal layer is made of bismuth or antimony, and the metal covering layer is made of gold;

[0008] When the material of the semi-metal layer is bismuth, the thickness ratio of the semi-metal layer to the metal covering layer is greater than 1.05:1; when the material of the semi-metal layer is antimony, the thickness ratio of the semi-metal layer to the metal covering layer is greater than 3.58:1.

[0009] Optionally, when the material of the semi-metal layer is bismuth, the thickness ratio of the semi-metal layer to the metal covering layer is 2:1 to 10:1; when the material of the semi-metal layer is antimony, the thickness ratio of the semi-metal layer to the metal covering layer is 5:1 to 20:1.

[0010] Optionally, when the material of the semi-metal layer is bismuth, the thickness ratio of the semi-metal layer to the metal covering layer is 2:1; when the material of the semi-metal layer is antimony, the thickness ratio of the semi-metal layer to the metal covering layer is 5:1.

[0011] Optionally, the thickness of the semi-metal layer is 10nm-100nm, and the thickness of the metal covering layer is 5nm-50nm.

[0012] A second aspect of the present invention provides a method for preparing a two-dimensional semiconductor transistor, comprising:

[0013] providing a substrate having a two-dimensional semiconductor layer;

[0014] Depositing a semi-metal layer and a metal covering layer in sequence on the two-dimensional semiconductor layer, wherein the material of the semi-metal layer is bismuth or antimony, and the material of the metal covering layer is gold, to obtain the two-dimensional semiconductor transistor;

[0015] When the material of the semi-metal layer is bismuth, the thickness ratio of the semi-metal layer to the metal covering layer is greater than 1.05:1; when the material of the semi-metal layer is antimony, the thickness ratio of the semi-metal layer to the metal covering layer is greater than 3.58:1.

[0016] Optionally, the semi-metal layer and the metal covering layer are deposited by electron beam vacuum coating technology, wherein the vacuum degree is less than or equal to 1×10 -4 Pa.

[0017] Optionally, the method for preparing the two-dimensional semiconductor transistor further includes:

[0018] Before the step of sequentially depositing the semi-metal layer and the metal covering layer on the two-dimensional semiconductor layer, a photoresist is coated on the two-dimensional semiconductor layer, and a preset patterning process is performed on the two-dimensional semiconductor layer by a photolithography process;

[0019] After the steps of sequentially depositing a semi-metal layer and a metal capping layer on the two-dimensional semiconductor layer, the photoresist is removed.

[0020] Beneficial effect: The present invention designs the thickness ratio between the semi-metal layer and the gold covering layer so that the atoms of the semi-metal layer are in an excess state, so that after the device is heat treated, the semi-metal layer and the gold covering layer undergo an interface alloying reaction and the semi-metal layer is still retained, and the contact of the device can still maintain the semi-metal Bi / Sb-two-dimensional semiconductor material contact interface, thereby improving the thermal stability of the two-dimensional semiconductor device, and allowing more process flows including heat treatment steps to be used to produce two-dimensional semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a schematic structural diagram of a two-dimensional semiconductor transistor provided by the present invention.

[0022] Figure 2 A schematic flow chart of a method for preparing a two-dimensional semiconductor transistor provided by the present invention.

[0023] Figure 3 A schematic diagram of a process flow for preparing a two-dimensional semiconductor transistor provided by the present invention.

[0024] Figure 4 This is a TEM image of the contact interface between Bi and MoS2 in the MoS2 transistor in Example 1 before annealing.

[0025] Figure 5 This is a TEM image of the contact interface between Bi and MoS2 in the MoS2 transistor in Example 1 after annealing.

[0026] Figure 6 This is the TEM image of the contact interface between Bi and MoS2 in the MoS2 transistor in Comparative Example 1 after annealing.

[0027] Figure 7 1 and 2 are output characteristic curves of the MoS2 transistors in Example 1 and Comparative Example 1 before and after thermal annealing.

[0028] Figure 8 This is the XRD diagram of the MoS2 transistor in Example 2 before and after annealing.

[0029] Fig. 9 This is the XRD diagram of the MoS2 transistor in Comparative Example 2 before and after annealing. DETAILED DESCRIPTION

[0030] The present invention provides a two-dimensional semiconductor transistor and a method for manufacturing the same. To make the purpose, technical solution and effect of the present invention clearer and more specific, the present invention is further described in detail below. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0031] According to one embodiment of the present invention, there is provided a two-dimensional semiconductor transistor, comprising:

[0032] A substrate, a two-dimensional semiconductor layer, a semi-metal layer and a metal covering layer sequentially arranged on the substrate, wherein the semi-metal layer is made of bismuth or antimony, and the metal covering layer is made of gold;

[0033] When the material of the semi-metal layer is bismuth, the thickness ratio of the semi-metal layer to the metal covering layer is greater than 1.05:1; when the material of the semi-metal layer is antimony, the thickness ratio of the semi-metal layer to the metal covering layer is greater than 3.58:1.

[0034] The embodiments of the present invention are aimed at the technical problem that the devices of the two-dimensional semiconductor-semimetal (Bi / Sb)-gold stacking structure in the prior art have poor thermal stability. By designing the thickness ratio between the semimetal layer and the gold covering layer, the atoms of the semimetal layer are in an excess state, so that after the device is heat treated, the semimetal layer and the gold covering layer undergo an interface alloying reaction, and the semimetal layer is still retained. The contact of the device can still maintain the contact interface of the semimetal Bi / Sb-two-dimensional semiconductor material, thereby improving the thermal stability of the two-dimensional semiconductor device.

[0035] In the embodiment of the present invention, the thickness of the semi-metal layer and the number of atoms it has, as well as the thickness of the gold covering layer and the number of atoms it has satisfy the following relationship:

[0036]

[0037] In formula 1, n is the number of atoms in the layer, and NA is the Avogadro constant (6.02×10 23 ), M is the molar mass of the material of the layer, m is the mass of the material of the layer, for the semi-metal layer and the gold covering layer, m can be expressed as density × area × thickness = ρSh. The relevant parameters of the semi-metal layer material Bi / Sb and the covering layer material Au are shown in Table 1:

[0038] Table 1

[0039] Material Name M(g / mol) <![CDATA[ρ(g / cm 3 )]]> Gold (Au) 196.97 19.32 Bismuth(Bi) 208.98 9.78 Antimony (Sb) 121.76 6.68

[0040] During the heat treatment of the two-dimensional semiconductor device, the semi-metal layer and the gold cover layer will undergo an alloying reaction, in which Bi in the semi-metal layer and Au in the cover layer will undergo an alloying reaction to generate Au2Bi, and Sb in the semi-metal layer and Au in the cover layer will undergo an alloying reaction to generate AuSb2. Therefore, for the process of Bi and Au generating Au2Bi, the atomic number ratio of Bi to Au is n Bi :n Au =1:2; Substituting the relevant parameters in Table 1 into Formula 1, the thickness ratio of the semi-metal layer Bi and the cover layer Au that fully participate in the alloy reaction can be obtained (the coverage area S of the two materials is the same):

[0041]

[0042] For the process of Sb and Au forming AuSb2, the atomic number ratio of Sb to Au is n Sb :n Au =2:1; Substituting the relevant parameters in Table 1 into Formula 1, the thickness ratio of the semi-metal layer Sb and the cover layer Au that fully participate in the alloy reaction can be obtained (the coverage area S of the two materials is the same):

[0043]

[0044] In the embodiment of the present invention, the thickness ratio of the semi-metal layer and the metal covering layer is determined according to the number of atoms in the semi-metal layer and the metal covering layer. It is necessary to ensure that there is still a semi-metal layer remaining after the semi-metal layer and the metal covering layer undergo interface alloying reaction, that is, the number of atoms in the semi-metal layer is relatively excessive, so that the contact of the device can still maintain the semi-metal Bi / Sb-two-dimensional semiconductor material contact interface. Therefore, when the material of the semi-metal layer is bismuth, the thickness ratio of the semi-metal layer to the metal covering layer should be greater than 1.05:1; when the material of the semi-metal layer is antimony, the thickness ratio of the semi-metal layer to the metal covering layer should be greater than 3.58:1.

[0045] According to one embodiment of the present invention, when the material of the semi-metal layer is bismuth, the thickness ratio of the semi-metal layer to the metal covering layer is 2:1 to 10:1; when the material of the semi-metal layer is antimony, the thickness ratio of the semi-metal layer to the metal covering layer is 5:1 to 20:1.

[0046] According to a preferred embodiment of the present invention, when the material of the semi-metal layer is bismuth, the thickness ratio of the semi-metal layer to the metal covering layer is 2:1 to 5:1; when the material of the semi-metal layer is antimony, the thickness ratio of the semi-metal layer to the metal covering layer is 5:1 to 10:1.

[0047] In the present invention, the thickness ratio of the semi-metallic layer to the metal covering layer is within the range described in the present invention. At this time, after annealing, the remaining semi-metallic layer of the device can maintain good contact with the interface of the two-dimensional material. At the same time, the metal covering layer can prevent the semi-metallic layer from being oxidized, which is beneficial to maintaining the thermal stability of the device while improving the oxidation resistance of the device.

[0048] According to a more preferred embodiment of the present invention, when the material of the semi-metal layer is bismuth, the thickness ratio of the semi-metal layer to the metal covering layer is 2:1; when the material of the semi-metal layer is antimony, the thickness ratio of the semi-metal layer to the metal covering layer is 5:1. Compared with other ratios, this thickness ratio is optimal, and the two-dimensional semiconductor transistor under such a thickness ratio can maintain good contact between the semi-metal layer and the two-dimensional material interface after annealing, and is more conducive to preventing the semi-metal layer from being oxidized, which is conducive to improving the thermal stability and oxidation resistance of the device.

[0049] According to one embodiment of the present invention, the material of the two-dimensional semiconductor layer can be selected from two-dimensional materials commonly used in the prior art, preferably two-dimensional materials such as MoS2, WSe2, WS2, etc., but not limited thereto.

[0050] According to one embodiment of the present invention, the thickness of the semi-metal layer is 10nm-100nm, for example, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, etc.; the thickness of the metal cover layer is 5nm-50nm, for example, 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, etc. Within this thickness range, the semi-metal layer can form a good contact with the interface of the two-dimensional material, and the metal cover layer can also prevent the semi-metal layer from being oxidized. After annealing, the semi-metal layer can also maintain a good contact with the interface of the two-dimensional material. This is conducive to improving the on-state current, thermal stability and oxidation resistance of the device.

[0051] According to an embodiment of the present invention, when the material of the semi-metal layer is bismuth, the thickness of the semi-metal layer is 20 nm, and the thickness of the metal covering layer is 10 nm.

[0052] According to an embodiment of the present invention, when the material of the semi-metal layer is antimony, the thickness of the semi-metal layer is 50 nm, and the thickness of the metal covering layer is 10 nm.

[0053] According to one embodiment of the present invention, after the two-dimensional semiconductor transistor is subjected to heat treatment, a semi-metal material-two-dimensional semiconductor material contact interface is maintained between the semi-metal layer and the two-dimensional semiconductor layer.

[0054] In the two-dimensional semiconductor transistor in an embodiment of the present invention, the material of the semi-metal layer is bismuth or antimony, and the material of the metal covering layer is gold. By designing the thickness ratio between the semi-metal layer and the gold covering layer, the atoms of the semi-metal layer are in an excess state. After heat treatment, there is still a remainder of the semi-metal layer, so that the contact interface between the semi-metal material and the two-dimensional semiconductor material can still be maintained, and a good ohmic contact is formed between the semi-metal layer and the two-dimensional semiconductor layer, thereby improving the thermal stability of existing two-dimensional semiconductor devices.

[0055] According to one embodiment of the present invention, a method for preparing a two-dimensional semiconductor transistor is provided, comprising:

[0056] providing a substrate having a two-dimensional semiconductor layer;

[0057] Depositing a semi-metal layer and a metal covering layer in sequence on the two-dimensional semiconductor layer, wherein the material of the semi-metal layer is bismuth or antimony, and the material of the metal covering layer is gold, to obtain the two-dimensional semiconductor transistor;

[0058] When the material of the semi-metal layer is bismuth, the thickness ratio of the semi-metal layer to the metal covering layer is greater than 1.05:1; when the material of the semi-metal layer is antimony, the thickness ratio of the semi-metal layer to the metal covering layer is greater than 3.58:1.

[0059] In the present invention, the two-dimensional semiconductor layer can be obtained by transferring to a substrate or growing directly on the surface of a substrate. The transfer or direct growth of two-dimensional semiconductor materials are both conventional techniques in the art and are not limited here. For example, the transfer of two-dimensional semiconductor materials can use a mechanical stripping method to strip and transfer two-dimensional semiconductor materials (MoS2, WSe2, WS2) on a substrate; or use a mechanical transfer method to transfer a single layer of two-dimensional semiconductor material grown by chemical vapor deposition (CVD) on a substrate.

[0060] According to one embodiment of the present invention, the deposition of the semi-metal layer and the metal covering layer may adopt a coating technology commonly used in the art, such as thermal evaporation coating technology, magnetron sputtering coating technology, electron beam vacuum coating technology, etc.

[0061] According to a preferred embodiment of the present invention, the semi-metal layer and the metal cover layer are deposited by electron beam vacuum coating technology, wherein the vacuum degree is less than or equal to 1×10 -4 Pa.

[0062] According to one embodiment of the present invention, the method for preparing the two-dimensional semiconductor transistor further includes:

[0063] Before the step of sequentially depositing the semi-metal layer and the metal covering layer on the two-dimensional semiconductor layer, a photoresist is coated on the two-dimensional semiconductor layer, and a preset patterning process is performed on the two-dimensional semiconductor layer by a photolithography process;

[0064] After the steps of sequentially depositing a semi-metal layer and a metal capping layer on the two-dimensional semiconductor layer, the photoresist is removed.

[0065] In the present invention, photoresist and photolithography can be used to prepare photolithography patterns at specific locations of a substrate having a two-dimensional semiconductor layer according to specific needs. The specific shape of the photolithography pattern can be set according to actual needs, and the specific shape is not limited here. After the steps of sequentially depositing a semi-metal layer and a covering layer on the two-dimensional semiconductor layer, it is necessary to remove the photoresist on the two-dimensional semiconductor layer to form a preset graphical semi-metal layer and covering layer. Using photoresist and photolithography (such as optical lithography, electron beam lithography and other technologies) to pattern the two-dimensional semiconductor layer, and subsequently removing the photoresist are all conventional techniques in the art and are not limited here.

[0066] Combination Figure 1 , Figure 2 and Figure 3 As shown, the present invention provides a two-dimensional semiconductor transistor and a method for manufacturing the same, comprising:

[0067] A substrate having a two-dimensional semiconductor layer is provided, and the two-dimensional semiconductor layer is patterned by using a photoresist and a photolithography process. Then, a semi-metal material is deposited on the two-dimensional semiconductor layer to form a semi-metal layer, and a covering layer material is deposited on the semi-metal layer to form a metal covering layer. Finally, the photoresist is removed to obtain the two-dimensional semiconductor transistor of the present invention.

[0068] The present invention will be further described below by means of specific examples.

[0069] Example 1

[0070] This embodiment provides a method for preparing a MoS2 transistor including a Bi(20nm) / Au(10nm) contact, as follows:

[0071] The SiO2 / Si (285nm SiO2) substrate was ultrasonically cleaned with acetone, anhydrous ethanol, and deionized water for 5 minutes. After drying with a nitrogen gun, the residual water and oxygen on the surface of the substrate were removed by plasma cleaning. MoS2 was prepared on the substrate by mechanical stripping. On the substrate with the MoS2 layer, a photoresist with a thickness of about 1μm was applied by spin coating. The substrate was pre-baked to evaporate the solvent in the photoresist and the film was dried and fixed. The preset electrode pattern was exposed on the substrate by a laser direct writing lithography machine, and a patterned substrate was obtained after development. An electron beam evaporation coating machine was used in a temperature of less than 10-4 Under a vacuum degree of 1.5 Pa, a Bi film (20 nm thick) and an Au film (10 nm thick) were sequentially deposited to form a semi-metal layer and a metal capping layer, respectively. The photoresist was removed by a lift-off process to obtain a MoS2 transistor containing a Bi (20 nm) / Au (10 nm) contact.

[0072] Comparative Example 1

[0073] The preparation method is the same as that of Example 1, except that a Bi film (with a thickness of 20 nm) and an Au film (with a thickness of 30 nm) are sequentially deposited to replace the Bi film and the Au film in Example 1 to form a semi-metallic layer and a metal covering layer, thereby obtaining a MoS2 transistor comprising a Bi (20 nm) / Au (30 nm) contact.

[0074] The MoS2 transistor prepared in Example 1 was subjected to thermal annealing at 200°C for 6 h, and the contact interface between Bi and MoS2 before and after annealing was characterized by transmission electron microscopy (TEM). Figure 4 This is the TEM image of the contact interface between Bi and MoS2 before annealing. It can be seen that the contact interface between Bi and MoS2 is clear before annealing. Figure 5 This is the TEM image of the contact interface between Bi and MoS2 after annealing. It can be seen that after annealing, Bi and Au undergo an alloying reaction to generate Au2Bi, but due to the retention of excess Bi, the contact interface between Bi and MoS2 is still intact in morphology and can form a good ohmic contact.

[0075] Similarly, the MoS2 transistor prepared in Comparative Example 1 was thermally annealed at 200°C for 6 hours, and the contact interface between Bi and MoS2 after annealing was characterized by transmission electron microscopy. Figure 6 This is the TEM image of the contact interface between Bi and MoS2 after annealing. It can be seen that after annealing, Bi and Au undergo an alloying reaction to completely generate Au2Bi, forming an Au2Bi-two-dimensional semiconductor contact interface, destroying the ohmic contact between the semi-metallic Bi and the two-dimensional semiconductor.

[0076] In addition, the electrical properties of the MoS2 transistors prepared in the above Example 1 and Comparative Example 1 were tested before and after thermal annealing. The Fs-Pro semiconductor parameter instrument of Prospect Electronics was used at a base voltage of 10 -6 The device output characteristic curve is measured in Torr's closed probe station. The voltage range between the source and drain of the device is -0.5V to 0.5V, and the gate voltage is 60V.

[0077] Figure 7The output characteristic curves of the MoS2 transistors prepared in Example 1 and Comparative Example 1 before and after thermal annealing show that the current of the MoS2 transistor containing Bi(20nm) / Au(30nm) contact in Comparative Example 1 drops more after annealing, and the current is 25% of the original current, while the current of the MoS2 transistor containing Bi(20nm) / Au(10nm) contact in Example 1 drops less after annealing, and the current is 98% of the original current. This shows that the thermal stability of the device has been significantly improved.

[0078] Example 2

[0079] This embodiment provides a method for preparing a MoS2 transistor including a Sb (50nm) / Au (10nm) contact, as follows:

[0080] The SiO2 / Si (285nm SiO2) substrate was ultrasonically cleaned with acetone, anhydrous ethanol, and deionized water for 5 minutes. After drying with a nitrogen gun, the residual water and oxygen on the surface of the substrate were removed by plasma cleaning. MoS2 was prepared on the substrate by mechanical stripping. On the substrate with the MoS2 layer, a photoresist with a thickness of about 1μm was applied by spin coating. The substrate was pre-baked to evaporate the solvent in the photoresist and the film was dried and fixed. The preset electrode pattern was exposed on the substrate by a laser direct writing lithography machine, and a patterned substrate was obtained after development. An electron beam evaporation coating machine was used in a temperature of less than 10 -4 Under a vacuum degree of 1.5 Pa, Sb thin film (50 nm thick) and Au thin film (10 nm thick) were sequentially deposited to form a semi-metal layer and a metal capping layer, respectively. The photoresist was removed by a lift-off process to obtain a MoS2 transistor containing Sb (50 nm) / Au (10 nm) contacts.

[0081] Comparative Example 2

[0082] The preparation method is the same as that of Example 2, except that Sb film (thickness is 20 nm) and Au film (thickness is 30 nm) are deposited in sequence to replace the Sb film and Au film in Example 2 to form a semi-metallic layer and a metal covering layer, thereby obtaining a MoS2 transistor comprising Sb (20 nm) / Au (30 nm) contact.

[0083] The MoS2 transistor prepared in Example 2 was subjected to thermal annealing at 200°C for 30 min, and the X-ray diffraction (XRD) patterns before and after annealing were tested to analyze the composition changes of the materials in the semi-metal layer and the covering layer. Figure 8This is the XRD diagram of the MoS2 transistor prepared in Example 2 before and after annealing. It can be seen that the Sb(50nm) / Au(10nm) film still has the characteristic peaks of Sb(003) and Sb(006) after annealing, proving that there is excess semi-metallic Sb retained, so that a good ohmic contact can be formed between the semi-metallic layer and the two-dimensional semiconductor layer.

[0084] Similarly, the MoS2 transistor prepared in Comparative Example 2 was thermally annealed at 200°C for 30 min, and the X-ray diffraction (XRD) patterns before and after annealing were tested. Fig. 9 This is the XRD diagram of the MoS2 transistor prepared in Comparative Example 2 before and after annealing. It can be seen that after annealing, only the characteristic peaks of Au and AuSb2 alloy exist in the Sb(20nm) / Au(30nm) film. The semi-metallic Sb has completely participated in the alloying reaction, thus destroying the ohmic contact between the semi-metallic layer and the two-dimensional semiconductor layer.

[0085] In summary, the present invention designs the thickness ratio between the semi-metal layer and the gold covering layer so that the atoms of the semi-metal layer are in an excess state. In this way, after the device is heat treated, the semi-metal layer and the gold covering layer undergo an interface alloying reaction and the semi-metal layer is still retained. The contact of the device can still maintain the semi-metal Bi / Sb-two-dimensional semiconductor material contact interface, thereby improving the thermal stability of the two-dimensional semiconductor device.

[0086] It should be understood that the application of the present invention is not limited to the above examples. For ordinary technicians in this field, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A two-dimensional semiconductor transistor, characterized in that: include: A substrate, a two-dimensional semiconductor layer, a semi-metal layer and a metal covering layer sequentially arranged on the substrate, wherein the semi-metal layer is made of bismuth or antimony, and the metal covering layer is made of gold; When the material of the semi-metal layer is bismuth, the thickness ratio of the semi-metal layer to the metal covering layer is greater than 1.05:1; when the material of the semi-metal layer is antimony, the thickness ratio of the semi-metal layer to the metal covering layer is greater than 3.58:

1.

2. The two-dimensional semiconductor transistor according to claim 1, characterized in that: When the material of the semi-metal layer is bismuth, the thickness ratio of the semi-metal layer to the metal covering layer is 2:1 to 10:1; when the material of the semi-metal layer is antimony, the thickness ratio of the semi-metal layer to the metal covering layer is 5:1 to 20:

1.

3. The two-dimensional semiconductor transistor according to claim 1, characterized in that: When the material of the semi-metal layer is bismuth, the thickness ratio of the semi-metal layer to the metal covering layer is 2:1; when the material of the semi-metal layer is antimony, the thickness ratio of the semi-metal layer to the metal covering layer is 5:

1.

4. The two-dimensional semiconductor transistor according to claim 1, characterized in that: The thickness of the semi-metal layer is 10nm-100nm, and the thickness of the metal covering layer is 5nm-50nm.

5. A method for preparing a two-dimensional semiconductor transistor, characterized in that: include: providing a substrate having a two-dimensional semiconductor layer; Depositing a semi-metal layer and a metal covering layer in sequence on the two-dimensional semiconductor layer, wherein the material of the semi-metal layer is bismuth or antimony, and the material of the metal covering layer is gold, to obtain the two-dimensional semiconductor transistor; When the material of the semi-metal layer is bismuth, the thickness ratio of the semi-metal layer to the metal covering layer is greater than 1.05:1; when the material of the semi-metal layer is antimony, the thickness ratio of the semi-metal layer to the metal covering layer is greater than 3.58:

1.

6. The method for preparing a two-dimensional semiconductor transistor according to claim 5, characterized in that: The semi-metal layer and the metal cover layer are deposited by electron beam vacuum coating technology, wherein the vacuum degree is less than or equal to 1×10 -4 Pa.

7. The method for preparing a two-dimensional semiconductor transistor according to claim 5, characterized in that: The preparation method further comprises: Before the step of sequentially depositing the semi-metal layer and the metal covering layer on the two-dimensional semiconductor layer, a photoresist is coated on the two-dimensional semiconductor layer, and a preset patterning process is performed on the two-dimensional semiconductor layer by a photolithography process; After the steps of sequentially depositing a semi-metal layer and a metal capping layer on the two-dimensional semiconductor layer, the photoresist is removed.

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