Semiconductor device and manufacturing method thereof

Abstract

Provided are a semiconductor device and a method of manufacturing the same, the semiconductor device including a first active region and a gate structure, the first active region extending in a first direction and including: a first outer corner edge at which a width of the first active region in a second direction changes gently along the first direction; and a first inner corner edge at which a width of the first active region varies less gently in a first direction than at the first outer corner edge, the gate structure extending in a second direction and overlapping with the first outer corner edge in a third direction, where the first direction and the second direction intersect horizontally, the third direction perpendicularly intersects with the first direction and the second direction.

Description

Technical Field

[0001] Apparatus and methods consistent with the present disclosure relate to a semiconductor device in which corner rounding between active regions of different widths is removed or reduced. Background Art

[0002] When forming a semiconductor cell block of a semiconductor device, the active area of ​​one cell can be formed to have a different width than the width of the active area of ​​an adjacent cell to implement different logic circuits based on device performance and device density. For example, although a cell of a high-performance logic circuit may require an active area with a larger width than a cell of a high-efficiency logic circuit, this can in turn allow additional elements (such as transistors, capacitors, additional contact structures or metal lines, etc.) to be formed to achieve increased device density.

[0003] However, when manufacturing semiconductor devices based on unit blocks, forming active regions of different widths in the unit blocks brings technical challenges. This challenge may be particularly evident in the context of 3D stacked semiconductor devices, where the need to have active regions with inconsistent widths within the unit blocks significantly increases the manufacturing challenges.

[0004] A 3D stacked semiconductor device or a multi-stacked semiconductor device may include one or more first transistors formed based on an active area at a first stack and one or more second transistors formed based on an active area at a second stack above the first stack, wherein each transistor may be a fin field effect transistor (FinFET), a nanosheet transistor, a forkplate transistor, or any other type of transistor.

[0005] The information disclosed in this background technology section is the technical information that the inventor has known or derived before or during the process of implementing the embodiments of the present application, or obtained in the process of implementing the embodiments. Therefore, it may contain information that does not constitute prior art known to the public. Summary of the invention

[0006] According to one aspect of an embodiment, a semiconductor device is provided, which may include: a first active region and a gate structure, wherein the first active region extends in a first direction and includes: a first outer corner edge, at which the width of the first active region in a second direction changes smoothly along the first direction; and a first inner corner edge, at which the width of the first active region changes less smoothly along the first direction at the first inner corner edge than at the first outer corner edge; and a gate structure, extending in the second direction and overlapping with the first outer corner edge in a third direction, wherein the first direction intersects the second direction horizontally, and the third direction intersects the first direction and the second direction vertically.

[0007] According to one aspect of an embodiment, a semiconductor device is provided, which may include: a first channel structure; a first source / drain region connected to the first channel structure; a second source / drain region connected to the first channel structure; and a gate structure configured to control the flow of current between the first source / drain region and the second source / drain region through the first channel structure, wherein the width of the first channel structure in the second direction varies smoothly along a first direction intersecting the second direction.

[0008] According to one aspect of an embodiment, a semiconductor device is provided, which may include: a first unit including a first active area; a second unit including a second active area, the second unit being adjacent to the first unit in a first direction, and the second active area being aligned with the first active area in the first direction; and a gate structure extending across at least one of the first active area and the second active area in a second direction, wherein the first active area has a first width in the second direction, and the second active area has a second width in the second direction that is smaller than the first width, wherein the first active area includes a first outer corner edge, the first width changes smoothly at the first outer corner edge, and the first outer corner edge overlaps with the gate structure in a third direction intersecting the first direction and the second direction, wherein the second active area includes a first inner corner edge, and the second width changes less smoothly at the first inner corner edge than at the first outer corner edge.

[0009] According to one aspect of the embodiment, a method for manufacturing a semiconductor device is provided. The method may include: providing a first active area on a substrate, the first active area including a first region, a second region and a first channel region arranged in a first direction, wherein the first region and the second region have a first width and a second width less than the first width in the second direction, respectively, and the first channel region has a first outer corner edge and a first inner corner edge, the first width gradually decreases at the first outer corner edge, and the second width gradually increases at the first inner corner edge; performing a cutting mask patterning on the first inner corner edge so that the curvature of the first inner corner edge increases; forming a dummy gate structure on the first active area so that the first outer corner edge overlaps with the dummy gate structure in a third direction; and forming a first source / drain region based on the channel region, wherein the first direction intersects horizontally with the second direction, and the third direction intersects vertically with the first direction and the second direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Example embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0011] Figures 1A to 1C A 3D stacked semiconductor device is shown in accordance with one or more embodiments, wherein active regions having different widths are formed.

[0012] Figure 2A 3D stacked semiconductor device according to one or more embodiments is illustrated, wherein rounded corners are formed in active regions having different widths in a plurality of cells.

[0013] FIG. 3A to FIG. 3C A semiconductor device obtained after various steps of manufacturing a 3D stacked semiconductor device according to one or more embodiments is shown, wherein rounded corners are removed or reduced in active regions having different widths in a plurality of cells.

[0014] FIG. 4A to FIG. 4C A semiconductor device obtained after various steps of manufacturing a 3D stacked semiconductor device according to one or more other embodiments is shown, wherein rounded corners are removed or reduced in active regions having different widths in a plurality of cells.

[0015] Figure 5 A flow chart of manufacturing a 3D stacked semiconductor device according to one or more other embodiments is shown, wherein rounded corners are removed or reduced in active regions having different widths in multiple cells.

[0016] Figure 6 is a schematic block diagram illustrating an electronic device including a semiconductor device according to one or more other embodiments, in which rounded corners are removed or reduced in active regions having different widths in a plurality of cells. DETAILED DESCRIPTION

[0017] The embodiments of the present disclosure described herein are example embodiments, and therefore, the present disclosure is not limited thereto and may be implemented in various other forms. Each embodiment provided in the following description does not exclude association with one or more features of another example or another embodiment that is also provided herein or is not provided herein but is consistent with the present disclosure. For example, even if the matter described in a specific example or embodiment is not described in an example or embodiment different therefrom, the matter may also be understood to be associated with or combined with different examples or embodiments, unless otherwise mentioned in its description. In addition, it should be understood that all descriptions of the principles, aspects, examples, and embodiments of the present disclosure are intended to cover their structural and functional equivalents. In addition, these equivalents should be understood to include not only currently known equivalents, but also equivalents to be developed in the future, that is, all devices invented to perform the same function, regardless of their structure. For example, the channel layer, sacrificial layer, and isolation layer described herein may be of different types or forms, as long as the present disclosure can be applied thereto.

[0018] It will be understood that when an element, component, layer, pattern, structure, region, etc. (hereinafter collectively referred to as an "element") of a semiconductor device is referred to as being "on" another element of the semiconductor device, "above" another element of the semiconductor device, "on" another element of the semiconductor device, "below" another element of the semiconductor device, "below" another element of the semiconductor device, "below" another element of the semiconductor device, "connected to" or "coupled to" another element of the semiconductor device, it may be directly on the other element, directly on the other element, directly below the other element, directly below the other element, directly connected to or coupled to other elements, or there may be intervening elements. Conversely, when an element of a semiconductor device is referred to as being "directly on" another element of the semiconductor device, "directly on" another element of the semiconductor device, "directly below" another element of the semiconductor device, "directly below" another element of the semiconductor device, "directly below" another element of the semiconductor device, "directly below" another element of the semiconductor device, "directly connected to" or "directly coupled to" another element of the semiconductor device, there are no intervening elements. Like reference numerals refer to like elements throughout the disclosure.

[0019] For ease of description, spatial relationship terms such as "above", "above", "on", "below", "below", "below", "under", "under", "left", "right", "lower left", "lower right", "upper left", "upper right", "center", "middle" and the like may be used herein to describe the relationship of one element to another element as shown in the figure. It will be understood that, in addition to the orientation depicted in the figure, the spatial relationship terms are intended to cover other different orientations of the semiconductor device in use or operation. For example, if the semiconductor device in the figure is turned over, the element described as "below" or "below" another element will be oriented "above" another element. Therefore, the term "below" can cover both the above and below orientations. The semiconductor device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relationship descriptors used herein are interpreted accordingly. As another example, the elements referred to as "left" elements and "right" elements can be "right" elements and "left" elements when the device or structure including these elements is oriented differently. Therefore, in the following description, the "left" element and the "right" element may also be referred to as the "first" element or the "second" element, respectively, as long as their structural relationship is clearly understood in the context of the description. Similarly, the terms "lower" element and "upper" element may be referred to as the "first" element and the "second" element, respectively, with the necessary description to distinguish the two elements.

[0020] It will be understood that although the terms "first", "second", "third", "fourth", "fifth", "sixth", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, a first element discussed in the description of the embodiment may be referred to as a second element in the claims without departing from the teachings of the present disclosure.

[0021] As used herein, expressions such as "at least one of..." when following a list of elements modify the entire list of elements and do not modify the individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. Herein, when the term "same" is used to compare the size of two or more elements, the term may encompass "substantially the same" sizes.

[0022] It will also be understood that even if a certain step or operation of manufacturing a device or structure is described as being performed later than another step or operation, the step or operation may be performed later than the other step or operation unless the other step or operation is described as being performed after the step or operation.

[0023] Many embodiments are described herein with reference to cross-sectional views, which are schematic illustrations of embodiments (and intermediate structures). Therefore, variations relative to the illustrated shapes as a result of, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments should not be interpreted as limited to the specific shapes of the regions shown herein, but should include deviations in shape, for example, due to manufacturing. The various regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the present disclosure. In addition, in the figures, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

[0024] For the sake of brevity, conventional elements, structures or layers of semiconductor devices including nanosheet transistors and the materials forming them may or may not be described in detail herein. For example, when a certain isolation layer or structure of a semiconductor device is not related to the novel features of an embodiment, the layer or structure and the materials forming them may be omitted herein. In addition, when the materials forming the known structural elements of the semiconductor device are not related to the novel features of the embodiment, the description of those materials may be omitted herein. In this article, the term "isolation" refers to electrical insulation or separation between structures, layers, components or regions in the corresponding device or structure.

[0025] Figures 1A to 1C A 3D stacked semiconductor device is shown in accordance with one or more embodiments, wherein active regions having different widths are formed.

[0026] Figure 1A is a top view of a unit block 10 in which a 3D stacked semiconductor device having active regions of different widths is formed, Figure 1B and Figure 1C They are taken along lines I-I' and II-II' respectively. Figure 1A 1 is a cross-sectional view of a 3D stacked semiconductor device in a unit block 10 shown in FIG. It should be understood here that Figure 1A is provided to illustrate the positional relationship between selected structural elements of a 3D stacked semiconductor device, and thus, Figure 1B and Figure 1C Some structural elements shown in FIG. 1 (such as substrate 101 and isolation structure 141) are not shown in FIG. Figure 1A Shown in.

[0027] like Figures 1A to 1C As shown, D1 direction is the channel length direction along which the current flows between two source / drain regions connected to each other by the channel structure, D2 direction is the channel width direction or the cell height direction intersecting with the D1 direction, and D3 direction is the channel height direction or the vertical direction intersecting with the D1 and D2 directions (both of which are horizontal directions).

[0028] Reference Figure 1A , the cell block 10 may include a first cell C1 and a second cell C2 arranged in the D1 direction and adjacent to each other. The boundary BR may separate the two cells C1 and C2. The first cell C1 may include a first lower active region 110 at a lower level (or stack) and a first upper active region 210 formed at an upper level (or stack) above the lower level, and the second cell C2 may include a second lower active region 120 at a lower level and a second upper active region 220 formed at an upper level.

[0029] The first lower active region 110 and the first upper active region 210 formed above the first lower active region 110 in the D3 direction may be aligned in the D1 direction with the second lower active region 120 and the second upper active region 220 formed above the second lower active region 120. Therefore, the active regions 110, 120, 210, and 220 may all extend in the D1 direction to form a plurality of channel structures and source / drain regions for respective transistors across the cells C1 and C2 thereon, as will be described later.

[0030] The active regions 110, 120, 210, and 220 may be formed from the substrate 101 ( Figure 1B and Figure 1C ) epitaxial growth, the substrate 101 may be, for example, a silicon (Si) substrate, but is not limited thereto. Therefore, the active regions 110, 120, 210, and 220 may also include silicon or an equivalent material.

[0031] In cells C1 and C2, the width of the lower active regions 110 and 120 may be different from the width of the upper active regions 210 and 220 to facilitate forming a contact structure on the lower source / drain region formed on the lower active region 110. The widths of the active regions of the first cell C1 and the second cell C2 may be different so that the two cells may accommodate logic circuits with different device performance and device density. The details of the width difference will be described later.

[0032] A plurality of gate structures 151-155 may be formed on the active regions 110, 120, 210, and 220, which extend in the D2 direction and are arranged in the D1 direction at a predetermined gate pitch or contact polysilicon pitch (CPP). Among the gate structures 151-155, the gate structure 153 may be formed along the boundary BR of the two cells C1 and C2, so that the virtual center line of the gate structure 153 in the D1 direction overlaps with the boundary BR. The gate structures 151-155 may each control the current flow in the active regions 110 and 120. The gate structures 151-155 may each include a metal or a metal compound, such as Cu, Al, Ti, Ta, W, Co, TiN, WN, TiAl, TiAlN, TaN, TiC, TaC, TiAlC, TaCN, TaSiN, or a combination thereof, but are not limited thereto. The gate structures 151-155 may be formed by replacing corresponding dummy gate structures at the same position in the unit block 10 during the process of manufacturing the 3D stacked semiconductor device herein. Therefore, when describing various embodiments below, the gate structures 151-155 may refer to the corresponding dummy gate structures.

[0033] The first lower active region 110 may include a first lower channel structure CH11 surrounded by each of the gate structures 151 and 152, and the first upper active region 210 may include a first upper channel structure CH21 surrounded by each of the gate structures 151 and 152. Similarly, the second lower active region 120 may include a second lower channel structure CH12 surrounded by each of the gate structures 154 and 155, and the second upper active region 220 may include a second upper channel structure CH22 surrounded by each of the gate structures 154 and 155. In addition, a third lower channel structure CH13 formed based on both the first lower active region 110 and the second lower active region 120 may be surrounded by the gate structure 153, and a third upper channel structure CH23 formed based on both the first upper active region 210 and the second upper active region 220 may be surrounded by the gate structure 153. Hereinafter, these channel structures may also be referred to as channel regions of the corresponding active regions.

[0034] The first lower source / drain region SD11 may be formed on each side of the first lower channel structure CH11 surrounded by the gate structure 152, and the first upper source / drain region SD21 may be formed on each side of the first upper channel structure CH21 surrounded by the gate structure 152. Similarly, the second lower source / drain region SD12 may be formed on each side of the second lower channel structure CH12 surrounded by the gate structure 154, and the second upper source / drain region SD22 may be formed on each side of the second upper channel structure CH22 surrounded by the gate structure 154. In contrast, the first lower source / drain region SD11 and the second lower source / drain region SD12 may be formed on each side of the third lower channel structure CH13, and the first upper source / drain region SD21 and the second upper source / drain region SD22 may be formed on each side of the third upper channel structure CH23.

[0035] Based on the above arrangement of the structural elements, three lower transistors and three upper transistors may be formed at the lower level and the upper level, respectively, to form a 3D stacked semiconductor device in the unit block 10. The first lower transistor LT1 may be formed by a first lower channel structure CH11, a first lower source / drain region SD11 connected to the first lower channel structure CH11, and a gate structure 152 surrounding the first lower channel structure CH11. The second lower transistor LT2 may be formed by a second lower channel structure CH12, a second lower source / drain region SD12 connected to the second lower channel structure CH12, and a gate structure 154 surrounding the second lower channel structure CH12. The third lower transistor LT3 may be formed by a third lower channel structure CH13, a first lower source / drain region SD11 and a second lower source / drain region SD12 connected to the third lower channel structure CH13, and a gate structure 153 surrounding the third lower channel structure CH13.

[0036] The first upper transistor UT1 may be formed of a first upper channel structure CH21, a first upper source / drain region SD21 connected to the first upper channel structure CH21, and a gate structure 152 surrounding the first upper channel structure CH21. The second upper transistor UT2 may be formed of a second upper channel structure CH22, a second upper source / drain region SD22 connected to the second upper channel structure CH22, and a gate structure 154 surrounding the second upper channel structure CH22. The third upper transistor UT3 may be formed of a third upper channel structure CH23, a first upper source / drain region SD21 and a second upper source / drain region SD22 connected to the third upper channel structure CH23, and a gate structure 153 surrounding the third upper channel structure CH23. Figure 1B As shown in , each of the transistors LT1 - LT3 and UT1 - UT3 may be a nanosheet transistor.

[0037] Each of the source / drain regions SD11, SD12, SD21, and SD22 may be epitaxially grown from at least two channel structures at both sides thereof. For example, the first lower source / drain region SD11 may be formed by applying epitaxy on the first lower channel structure CH11 surrounded by the gate structures 151 and 152, respectively. As another example, the second upper source / drain region SD22 may be formed by applying epitaxy on the second upper channel structure CH22 surrounded by the gate structure 154 and the third upper channel structure CH23 surrounded by the gate structure 153. Therefore, each of the source / drain regions SD11, SD12, SD21, and SD22 may be formed by epitaxy from the same material as that forming the corresponding channel structure.

[0038] For example, the lower active regions 110, 120 and the lower channel structures CH11, CH12, CH13 may be formed of silicon (Si), and the lower source / drain regions SD11 and SD12 may also be formed of silicon. In addition, the lower source / drain regions SD11 and SD12 may be injected or doped with n-type impurities such as phosphorus (P), arsenic (As), antimony (Sb), etc., so that the lower transistors LT1-LT3 may each form an n-type transistor. As another example, the upper active regions 210, 220 and the upper channel structures CH21, CH22, CH23 may be formed of silicon germanium (SiGe), and the upper source / drain regions SD21 and SD22 may also be formed of silicon germanium. In addition, the upper source / drain regions SD21 and SD22 may be injected or doped with p-type impurities such as boron (B), gallium (Ga), indium (In), etc., so that the upper transistors UT1-UT3 may each form a p-type transistor. However, the present disclosure is not limited thereto, and according to one or more embodiments, the lower transistors LT1-LT3 may each be formed as any one of a p-type transistor and an n-type transistor, and the upper transistors UT1-UT3 may each be formed as any one of a p-type transistor and an n-type transistor.

[0039] Each active region in cells C1 and C2 may be formed on substrate 101, and a bottom dielectric isolation (BDI) layer 105 may be formed on substrate 101 to isolate substrate 101 from gate structures 151-155 and lower source / drain regions SD11 and SD12, thereby preventing current from leaking from these structures to the substrate. BDI layer 105 may include silicon nitride (SiN, SiCN, SiBCN, etc.), but is not limited thereto. An intermediate dielectric isolation (MDI) layer 115 may be formed to isolate each of lower channel structures CH11, CH12, and CH13 from upper channel structures CH21, CH22, and CH23. The MDI layer may also include silicon nitride (SiN, SiCN, SiBCN, etc.). A shallow trench isolation (STI) structure 103 may be formed at the upper left and upper right corners of the substrate 101, which includes silicon oxide (e.g., SiO, SiO 2 For isolation purposes, an isolation structure 141 (which may also include silicon oxide (eg, SiO, SiO 2 etc.)) to surround the gate structures 151-155 and the source / drain regions SD11, SD12, SD21 and SD22.

[0040] The width difference between the lower active area and the upper active area

[0041] The first lower active region 110 may have a width W1 in the D2 direction that is consistent along the D1 direction, and the first upper active region 210 may have a width W2 in the D2 direction that is also consistent along the D1 direction. The width W1 may be greater than the width W2. Therefore, the left half of the third lower channel structure CH13 and the first lower channel structure CH11 (each of which is an extension of the first lower active region 110 and included in the first cell C1) may have a width W1, and the left half of the third upper channel structure CH23 and the first upper channel structure CH21 (each of which is an extension of the first upper active region 210 and included in the first cell C1) may each have a width W2. Therefore, Figure 1B It is shown that the first lower channel structure CH11 has a width W1 that is greater than a width W2 of the first upper channel structure CH21 .

[0042] Similarly, the second lower active region 120 may have a width W3 in the D2 direction that is consistent along the D1 direction, and the second upper active region 220 may have a width W4 in the D2 direction that is also consistent along the D1 direction. The width W3 may be greater than the width W4. Therefore, the right half of the third lower channel structure CH13 and the second lower channel structure CH12 (each of which is an extension of the second lower active region 120 and included in the second cell C2) may each have a width W3, and the right half of the third upper channel structure CH23 and the second upper channel structure CH22 (each of which is an extension of the second upper active region 220 and included in the second cell C2) may each have a width W4. Therefore, although not shown, the second lower channel structure CH12 has a width W3 greater than the width W4 of the second upper channel structure CH22.

[0043] Since, as described above, the lower channel structures CH11, CH12 and CH13 have a greater width in the D2 direction than the upper channel structures CH21, CH22 and CH23, the lower source / drain regions SD11 and SD12 epitaxially grown from the channel structures CH11, CH12 and CH13 may have a greater width in the D2 direction than the upper source / drain regions SD21 and SD22 epitaxially grown from the channel structures CH21, CH22 and CH23. Figure 1C It is shown that the first lower source / drain region SD11 has a greater width in the D2 direction than the first upper source / drain region SD21 .

[0044] The aforementioned width difference may be provided to provide a space at least on one side of each of the upper source / drain regions SD21 and SD22 above the lower source / drain regions SD11 and SD12, respectively, so that in a nanoscale 3D stacked semiconductor device, a contact structure connecting each of the lower source / drain regions SD11 and SD12 to a metal line in a back-end-of-line (BEOL) layer may be formed on a top surface of each of the lower source / drain regions SD11 and SD12 through the space.

[0045] When the upper channel structures CH21, CH22, and CH23 have a smaller width than the lower channel structures CH11, CH12, and CH13, respectively, the upper channel structures CH21, CH22, and CH23 may each have a larger number of channel layers (which are nanosheet semiconductor layers) than the lower channel structures CH11, CH12, and CH13, respectively. For example, the first lower channel structure CH11 may have two nanosheet semiconductor layers, and the first upper channel structure CH21 may have three nanosheet semiconductor layers. However, the number of these semiconductor nanosheet layers is only an example, and the present disclosure is not limited thereto.

[0046] Difference in width of active area between cells

[0047] As described above, the width W1 of the first lower active region 110 in the first cell C1 may be greater than the width W3 of the second lower active region 120 in the second cell C2. Similarly, the width W2 of the first upper active region 210 in the first cell C1 may be greater than the width W4 of the second upper active region 220 in the second cell C2. Figure 1A as shown in .

[0048] By differentiating the width of the active area across cells C1 and C2, one or more logic circuits formed in cell C1 may have device characteristics different from one or more logic circuits formed in cell C2. For example, since the first lower transistor LT1 and the first upper transistor UT1 in the first cell CE1 may have a larger width channel structure CH11, CH12 and source / drain regions SD11, SD21, a logic circuit or device with high performance and high power consumption may be formed in the first cell. In contrast, since the second lower transistor LT2 and the second upper transistor UT2 may have a smaller width channel structure CH12, CH22 and source / drain regions SD12, SD22, a highly efficient logic circuit or device may be formed in the second cell. For example, in a trigger circuit, a clock circuit may be formed in the first cell while a master latch or slave latch circuit may be formed in the second cell.

[0049] Due to the difference in width of the active region across the boundary BR between the cells C1 and C2, each of the third lower channel structure CH13 and the third upper channel structure CH23 may have a different width in the D2 direction along the D1 direction. Figure 1A As shown in , the left half of the third lower channel structure CH13 may have a width W1 greater than the width W3 of the right half of the third lower channel structure CH13, and the left half of the third upper channel structure CH23 may have a width W2 greater than the width W4 of the right half of the second upper channel structure CH23. Therefore, each of the third lower transistor LT3 including the third lower channel structure CH13 and the third upper transistor UT3 including the third upper channel structure CH23 may have source / drain regions of different widths.

[0050] Therefore, any one of the two transistors LT3 and UT3 or the combination of the two transistors LT3 and UT3 can form a transistor structure that can be customized for various purposes. For example, a logic circuit with a small resistance and a low gate threshold voltage that requires a large amount of source current to flow to the drain region can include the third lower transistor LT3 or the third upper transistor UT3.

[0051] At the same time, the second lower active region 120 and the second upper active region 220 can be formed by patterning an initial lower active region having a width W1 and an initial upper active region having a width W2, so that the widths W1 and W2 are reduced to widths W3 and W4, respectively, in the region corresponding to the second cell C2, while the widths W1 and W2 remain unchanged in the region corresponding to the first cell C1.

[0052] The patterning operation may be performed by performing photolithography, masking, and etching operations on the initial lower active region and the initial upper active region, respectively. For example, one or more hard mask patterns may be formed on the top surfaces of the initial lower active region and the initial upper active region at one or more locations to expose the region MR on the top surface (e.g., Figure 1A ), and dry etching or wet etching may be performed based on the hard mask pattern to remove the initial first lower active region and the initial first upper active region in the region MR, thereby forming a second lower active region 120 and a second upper active region 220 in addition to the first lower active region 110 and the first upper active region 210.

[0053] However, due to process variations and limitations of photolithography, masking, and etching operations, it may be difficult to form the first lower active region 110 and the first upper active region 210 having uniform widths W1 and W2, respectively, along the forward (rightward) direction D1 toward the cell boundary BR, and to form the second lower active region 120 and the second upper active region 220 having uniform widths W3 and W4, respectively, along the backward (leftward) direction D1 toward the boundary BR, as shown in FIG. Figure 1A Alternatively, the width reduction at the cell boundary BR may be as follows: Figure 2 The tapering form shown in .

[0054] Figure 2 A 3D stacked semiconductor device according to one or more embodiments is shown, in which corner rounding is formed in active regions having different widths in a plurality of cells.

[0055] Reference Figure 2 , which is related to Figure 1A Corresponding to the top view, the unit block 20 of the 3D stacked semiconductor device may include Figure 1A Therefore, repeated descriptions thereof may be omitted, and instead, different aspects of the unit block 20 may be described hereinafter using the same reference numerals as needed.

[0056] Unlike in the cell block 10, the respective widths W1 and W2 of the first lower active region 110 and the first upper active region 210 in the first cell C1 of the cell block 20 may not be consistent along the forward (rightward) D1 direction toward the cell boundary BR, and similarly, the respective widths W3 and W4 of the second lower active region 120 and the second upper active region 220 may not be consistent along the backward (leftward) D1 direction toward the cell boundary BR. Alternatively, the respective widths W1 and W2 of the first lower active region 110 and the first upper active region 210 may gradually decrease from a position near the cell boundary BR outside the gate structure 153 in the cell C1 to the cell boundary BR, while the widths W3 and W4 of the second lower active region 120 and the second upper active region 220 may gradually increase from a position near the cell boundary BR outside the gate structure 153 in the cell C2 to the cell boundary BR.

[0057] Therefore, if Figure 2 As shown in , the first lower active region 110 may have an outer fillet around the outer corner edge R11 outside the gate structure 153 (where the width W1 begins to gradually decrease), and the first upper active region 210 may have an outer fillet around the outer corner edge R21 outside the gate structure 153 (where the width W2 begins to gradually decrease). Similarly, the second lower active region 120 may have an inner fillet around the inner corner edge R12 outside the gate structure 153 (where the width W2 begins to gradually increase), and the second upper active region 220 may have an inner fillet around the inner corner edge R22 outside the gate structure 153 (where the width W4 begins to gradually increase). Due to the fillet, each of the corner edges R11, R12, R21 and R22 may have a corresponding curvature. In addition, the channel structures CH13 and CH23 have a width that changes gently along the D1 direction below the gate structure 153 in the D3 direction. In addition, the rounded corners on the outside of the gate structure 153 produce insufficient active areas around the outer corner edges R11 and R21 and excessive active areas around the inner corner edges R12 and R22 .

[0058] The rounded corners and gently varying widths around the corner edges R11, R21, R12, and R22 of the active regions 110, 120, 210, and 220 may be due to process variations and limitations in the photolithography, masking, and etching operations of forming the two lower active regions 110 and 120 from an initial lower active region and the two upper active regions 210 and 220 from an initial upper active region. Such rounded corners may also result in additional process variations in subsequent operations, including forming source / drain regions SD11, SD12, SD21, and SD22 by epitaxially growing channel structures CH13 and CH23 surrounded by dummy gate structures (to be replaced by gate structure 153). For example, after the source / drain regions SD12 and SD11 are grown from the channel structures CH13 and CH23, the dummy gate structure is replaced by the gate structure 153. Due to the excess active area at the inner corner edges R12 and R22, a short circuit or an increase in short circuit may occur between the gate structure 153 and the source / drain regions SD12 and SD22 formed based on the third lower channel CH13 and the third upper channel structure CH23. In addition, insufficient active areas at the outer corner edges R11 and R21 may result in insufficient formation of the source / drain regions SD11 and SD21.

[0059] Provided below are embodiments of a method for removing or reducing a rounded corner region in an active region and a 3D stacked semiconductor device manufactured based on the method.

[0060] FIG. 3A to FIG. 3C A semiconductor device obtained after various steps of manufacturing a 3D stacked semiconductor device according to one or more embodiments is shown, wherein rounded corners are removed or reduced in active regions having different widths in a plurality of cells. Figure 1A and Figure 2 The 3D stacked semiconductor device shown in FIG. 1 is a 3D stacked semiconductor device, so the same reference numerals may be used in the description.

[0061] Reference Figure 3A , the initial lower active region having a width W1 and the initial upper active region having a width W2 formed above the initial lower active region may be patterned so that the initial active region is divided into a first lower active region 110 having a width W1, a first upper active region 210 having a width W2, a second lower active region 120 having a width W3, and a second upper active region 220 having a width W4. The patterning operation in this step may be performed on the initial lower active region and the initial upper active region by, for example, photolithography, masking, and etching. The width W1 is greater than the width W2, and the width W3 is greater than the width W4.

[0062] However, due to patterning variations and limitations, the width W1 of the initial lower active region and the width W2 of the initial upper active region may gradually decrease or taper in the forward direction D1, so that Figure 3A As shown in , the first lower active region 110 and the first upper active region 210 may have outer rounded corners around outer corner edges R11 and R21, respectively, and the second lower active region 120 and the second upper active region 220 may have inner rounded corners around inner corner edges R12 and R22, respectively. The outer corner edges R11 and R21 may be aligned with each other in the D2 direction, and the inner corner edges R12 and R22 may also be aligned with each other in the D2 direction.

[0063] Cutting mask patterning may be performed on the first cutting mask region CT1 and the second cutting mask region CT2 to remove the outer and inner corners. The cutting mask patterning may be performed by forming one or more hard mask patterns at multiple locations on the top surface of each of the initial lower active region and the initial upper active region divided into four active regions 110, 120, 210, and 220, via additional photolithography, masking, and etching operations. The hard mask pattern may expose the cutting mask regions CT1 and CT2, based on which dry etching or wet etching may be performed.

[0064] Meanwhile, an initial lower active region may be formed from substrate 101 with BDI layer 105 therebetween, and an initial upper active region may be formed over the initial lower active region with MDI layer 115 therebetween (see Figure 1B and Figure 1C ). Therefore, the above-mentioned patterning and cutting mask patterning may be performed based on the BDI layer and the MDI layer as an etch stop layer.

[0065] Both the initial lower active region and the initial upper active region may include a plurality of nanosheet semiconductor layers epitaxially grown layer by layer from the substrate 101. The nanosheet semiconductor layers may include sacrificial layers and channel layers alternately stacked on the substrate 101. In subsequent steps, the sacrificial layers may be replaced by a material forming a gate structure, and the channel layers may form a plurality of channel structures.

[0066] Reference Figure 3B Due to the cutting mask patterning in the previous step, the first lower active region 110 and the first upper active region 210 may be formed to have widths W1 and W2 consistent along the D1 direction, and the second lower active region 120 and the second upper active region 220 may be formed to have widths W3 and W4 consistent along the D1 direction.

[0067] However, the cutting mask patterning performed in the previous step can also leave minimal outer and inner fillets around the outer corner edges R11, R21 and the inner corner edges R12, R22. However, due to the cutting mask patterning, this step ( Figure 3B ) may have a greater curvature than that of the outer corner edges R11, R21 and the inner corner edges R12, R22 in the previous step ( Figure 3A) at the outer corner edges R11, R21 and the inner corner edges R12, R22. It should be understood that the higher the curvature of the active area, the sharper the curvature of the active area. Therefore, the width W1 of the initial lower active area and the width W2 of the initial upper active area are in this step ( Figure 3B ) may be larger than in the previous step ( Figure 3A ) changes less smoothly at the corner edges R11, R12, R21 and R22.

[0068] Reference Figure 3C , a first cell C1 and a second cell may be formed, wherein channel structures CH11, CH12, CH13, CH21, CH22, and CH23, source / drain regions SD11, SD12, SD21, and SD22, and gate structures 151-155 are formed based on active regions 110, 120, 210, and 220 having different widths.

[0069] The channel structures CH11, CH12, CH13, CH21, CH22, and CH23 may be formed by first forming a dummy gate structure at the location of the gate structures 151-155 and etching the active regions 110, 120, 210, and 220 at the locations where the source / drain regions SD11, SD12, SD21, and SD22 are to be formed. At this time, a dummy gate structure corresponding to the gate structure 153 may be formed to overlap with a boundary BR between the first lower active region 110 and the second lower active region 120. The boundary BR also separates the first upper active region 210 and the second upper active region 220. Based on the boundary BR, a first cell C1 and a second cell C2 having active regions of different widths are formed.

[0070] Meanwhile, the channel structures CH13 and CH23 may be formed to include corner edges R11 , R12 , R21 , and R22 , and the gate structure 153 replacing the dummy gate structure may overlap the corner edges R11 , R12 , R21 , and R22 in the D3 direction.

[0071] Next, the source / drain regions can be epitaxially grown from the channel structure surrounded by the dummy gate structure, and the dummy gate structure and the sacrificial layers included in the active areas 110, 120, 210 and 220 can be replaced by the gate structures 151-155 to form the corresponding lower transistors LT1-LT3 and upper transistors UT1-UT3 of the 3D stacked semiconductor device 30.

[0072] Hereinafter, another method for removing or reducing a rounded corner region in an active region and a 3D stacked semiconductor device manufactured based on the method are provided.

[0073] FIG. 4A to FIG. 4CA semiconductor device obtained after various steps of manufacturing a 3D stacked semiconductor device according to one or more other embodiments is shown, wherein rounded corners are removed or reduced in active regions having different widths in a plurality of cells. Figure 1A and Figure 2 , so the same reference numerals may be used in the description.

[0074] Reference Figure 4A , the initial lower active region having a width W1 and the initial upper active region having a width W2 formed above the initial lower active region may be patterned, thereby dividing the initial active region into a first lower active region 110 having a width W1, a first upper active region 210 having a width W2, a second lower active region 120 having a width W3, and a second upper active region 220 having a width W4. The patterning operation in this step may be performed on the initial lower active region and the initial upper active region by, for example, photolithography, masking, and etching. The width W1 is greater than the width W2, and the width W3 is greater than the width W4.

[0075] However, due to patterning variations and limitations, the width W1 of the initial lower active region and the width W2 of the initial upper active region may gradually decrease or taper in the forward direction D1, so that Figure 4A As shown in , the first lower active region 110 and the first upper active region 210 may have outer rounded corners around outer corner edges R11 and R21, respectively, and the second lower active region 120 and the second upper active region 220 may have inner rounded corners around inner corner edges R12 and R22, respectively. The outer corner edges R11 and R21 may be aligned with each other in the D2 direction, and the inner corner edges R12 and R22 may also be aligned with each other in the D2 direction.

[0076] Cutting mask patterning may be performed on the first cutting mask region CT1 and the second cutting mask region CT2 to remove the inner rounded corners. The cutting mask patterning may be performed by forming one or more hard mask patterns at multiple locations on the top surface of each of the initial lower active region and the initial upper active region divided into four active regions 110, 120, 210, and 220, through additional photolithography, masking, and etching operations. The hard mask pattern may expose the cutting mask regions CT1 and CT2, based on which dry etching or wet etching may be performed.

[0077] Meanwhile, an initial lower active region may be formed from substrate 101 with BDI layer 105 therebetween, and an initial upper active region may be formed over the initial lower active region with MDI layer 115 therebetween (see Figure 1B and Figure 1C). Therefore, the above-mentioned patterning and cutting mask patterning may be performed based on the BDI layer and the MDI layer as an etch stop layer.

[0078] Both the initial lower active region and the initial upper active region may include a plurality of nanosheet semiconductor layers epitaxially grown layer by layer from the substrate 101. The nanosheet semiconductor layers may include sacrificial layers and channel layers alternately stacked on the substrate 101. In subsequent steps, the sacrificial layers may be replaced by a material forming a gate structure, and the channel layers may form a plurality of channel structures.

[0079] Reference Figure 4B Due to the cutting mask patterning in the previous step, the second lower active region 120 and the second upper active region 210 may be formed to have uniform widths W3 and W4 in the backward D1 direction toward the inner corner edges R12 and R22 .

[0080] However, the outer fillets around the outer corner edges R11 and R21 may still remain on the first lower active region 110 and the first upper active region 210, respectively. In addition, the cut mask patterning performed in the previous step may also leave a minimal inner fillet around the inner corner edges R12 and R22. However, due to the cut mask patterning, in this step ( Figure 4B ) can have a greater curvature than that of the inner corner edges R12 and R22 (where the widths W3 and W4 begin to increase) in the previous step ( Figure 4A ) and the curvatures of the outer corner edges R11 and R21 where the widths W1 and W2 gradually decrease. Therefore, the width W1 of the initial lower active area and the width W2 of the initial upper active area may still change smoothly at the outer corner edges R11 and R21, and be smaller at the inner corner edges R12 and R22 than in this step ( Figure 4B ) at the outer corner edges R11 and R21 and at the previous step ( Figure 4A ) changes less smoothly at the inner corner edges R12 and R22.

[0081] Reference Figure 4C , a first cell C1 and a second cell C2 may be formed, wherein channel structures CH11, CH12, CH13, CH21, CH22, and CH23, source / drain regions SD11, SD12, SD21, and SD22, and gate structures 151-155 are formed based on active regions 110, 120, 210, and 220 having different widths.

[0082] The channel structures CH11, CH12, CH13, CH21, CH22, and CH23 may be formed after first forming a dummy gate structure at the location of the gate structures 151-155 and etching the active regions 110, 120, 210, and 220 at the locations where the source / drain regions SD11, SD12, SD21, and SD22 are to be formed. At this time, a dummy gate structure corresponding to the gate structure 153 may be formed to overlap the outer corner edges R11 and R21 in the D3 direction. Therefore, the boundary BR between the first lower active region 110 and the second lower active region 120 may overlap the outer corner edges R11 and R21 in the D3 direction. The boundary BR also separates the first upper active region 210 and the second upper active region 220. Based on the boundary BR, a first cell C1 and a second cell C2 having active regions of different widths may be formed. However, the dummy gate structure overlapping the outer corner edges R11 and R21 may not overlap the inner corner edges R12 and R22 , or a side surface of the dummy gate structure may overlap the inner corner edges R12 and R22 in the D3 direction.

[0083] Therefore, the channel structures CH13 and CH23 may be formed to include outer corner edges R11 and R21 but not inner corner edges R12 and R22. When the channel structures CH13 and CH23 include outer corner edges R11 and R12, the channel structures CH13 and CH23 may each have a gently varying width under the dummy gate structure.

[0084] Next, source / drain regions can be epitaxially grown from the channel structure surrounded by the dummy gate structure, and the dummy gate structure and the sacrificial layers included in the active areas 110, 120, 210 and 220 can be replaced by gate structures 151-155 to form corresponding lower transistors LT1-LT3 and upper transistors UT1-UT3 of the 3D stacked semiconductor device 40.

[0085] By the above method, the rounded corners at the corner edges can be removed, and therefore, the insufficient active area and the excessive active area can also be removed. Therefore, a 3D stacked semiconductor device in which the active area has different widths on multiple units can be formed without or with reduced risk of short circuit between the gate structure and the source / drain region of the rounded corners, and without or with reduced risk of insufficient source / drain region formation.

[0086] Figure 5 A flow chart for manufacturing a 3D stacked semiconductor device according to one or more other embodiments is shown, wherein rounded corners are removed or reduced in active regions having different widths in multiple cells. The description of the flow chart may be provided using the same reference numerals used to describe the above embodiments.

[0087] In step S10, an initial lower active region having a width W1 and an initial upper active region having a width W2 less than the width W1 may be patterned to form a first lower active region 110 having a width W1, a first upper active region 210 having a width W2, a second lower active region 120 having a width W3, and a second upper active region 220 having a width W4 less than the width W3.

[0088] The patterning operation may be performed by photolithography, masking, and etching the initial active region based on the BDI layer 105 formed between the substrate and the initial lower active region and the MDI layer 115 formed between the initial lower active region and the initial upper active region.

[0089] However, since the patterning operation has process variations and limitations (which prevent the initial active area from being accurately patterned to have uniform widths W1, W2, W3, and W3 along the D1 direction from the boundaries BR of the divided active areas 110, 120, 210, and 220), rounded corners may be formed at the inner corner edges R12 and the outer corner edges R11 between the lower active areas 110 and 120 and at the inner corner edges R22 and the outer corner edges R21 between the upper active areas 210 and 220.

[0090] In step S20 , cut mask patterning may be performed to remove the rounded corners at the inner corner edge R12 between the lower active regions 110 and 120 and the rounded corners at the inner corner edge R22 between the upper active regions 210 and 220 .

[0091] The cutting mask patterning in this step can also be performed by photolithography, masking and etching operations, which still have process variations and limitations. However, due to this cutting mask patterning, the rounded corners can be at least reduced, thereby increasing the curvature of the inner corner edges R12 and R22. However, the rounded corners at the outer corner edges R11 and R21 may still exist.

[0092] In step S30, a dummy gate structure (to be replaced by gate structure 153) may be formed to overlap outer corner edges R11 and R21, and the lower active regions 110, 120 and upper active regions 210 and 220 may be patterned to form a channel structure under the dummy gate structure, and provide space for forming source / drain regions based on the dummy gate structure and the channel structure surrounded by the dummy gate structure.

[0093] When the outer corner edges R11 and R21 overlap with the dummy gate structure, the outer corner edges R11 and R21 can be surrounded by the dummy gate structure to remove the fillets at the outer corner edges R11 and R21, thereby removing or reducing the active area defects outside the dummy gate structure. Therefore, insufficient formation of the source / drain regions SD11 and SD21 in the next step can be avoided. In addition, since the fillets at the inner corner edges R12 and R22 can also be removed or reduced by cutting mask patterning, the source / drain regions SD12 and SD22 can be formed in the next step without or reducing the risk of short circuiting with the gate structure 153 that will replace the dummy gate structure.

[0094] In addition, the first lower active region 110 and the first upper active region 210 on one side of the dummy gate structure and the second lower active region 120 and the second upper active region 220 on the other side of the dummy gate structure may be patterned based on the dummy gate structure to form channel structures CH13 and CH23 below the dummy gate structure and form a space for forming a source / drain region on the side of the dummy gate structure. At this time, the channel structures CH13 and CH23 may include outer corner edges R11 and R21 overlapping the dummy gate structure.

[0095] In step S40 , source / drain regions SD11 , SD12 , SD21 , and SD22 may be formed based on the channel structures CH13 and CH23 , and the dummy gate structure may be replaced by the gate structure 153 .

[0096] As described in the previous steps, source / drain regions SD11, SD12, SD21 and SD22 can be formed based on the channel structures CH13 and CH23 including outer corner edges R11 and R21 overlapping the dummy gate structure, without or reducing the risk of forming insufficient source / drain regions SD11 and SD21 and a short circuit between the gate structure 153 and at least one of the source / drain regions SD12 and SD22.

[0097] In the above embodiments, the corner edge of the width of the active region is indicated to be formed at the channel structure below the gate structure and overlapped with the boundary between two adjacent cells. However, the present disclosure is not limited to this. According to one or more embodiments, the active region can be formed to have a width variation inside the cell of the 3D stacked semiconductor device, but not at the channel structure, not below the gate structure, or not overlapping with the boundary between two adjacent cells.

[0098] In the above embodiments, both the lower active area and the upper active area have a smoothly varying width and a less smoothly varying width. However, the present disclosure is not limited thereto. According to one or more embodiments, only one of the lower active area and the upper active area may have a smoothly varying width and a less smoothly varying width, while the other has a uniform width along the D1 direction.

[0099] In the above embodiments, the lower active region and the upper active region have different widths to facilitate forming a contact structure on the top surface of the source / drain region. However, the present disclosure is not limited thereto, and the embodiments may also be applicable to a 3D stacked semiconductor device in which the lower active region and the upper active region have the same width.

[0100] In the above embodiments, the semiconductor device having active regions with different widths as described above is described as a 3D stacked semiconductor device. However, the present disclosure is not limited thereto, and the embodiments may also be applied to a single stack 3D stacked semiconductor device.

[0101] In the above embodiments, 3D stacked semiconductor devices 10, 20, 30, and 40 are described as being formed by n-type lower nanosheet transistors and p-type upper nanosheet transistors. However, according to one or more embodiments, these 3D stacked semiconductor devices may be formed by transistors of different types and / or different polarities at the lower level and / or upper level.

[0102] Figure 6 is a schematic block diagram showing an electronic device including a semiconductor device according to one or more other embodiments, wherein rounded corners are removed or reduced in active regions having different widths in a plurality of cells. The semiconductor device may be Figure 3C and Figure 4C One of the 3D stacked semiconductor devices 30 and 40 is shown in FIG.

[0103] Reference Figure 6 , the electronic device 1000 may include at least one processor 1100, a communication module 1200, an input / output (I / O) module 1300, a memory 1400, and a buffer random access memory (RAM) module 1500. According to an embodiment, the electronic device 1000 may be a mobile device such as a smartphone or a tablet, but is not limited thereto.

[0104] The processor 1100 may include a central processing unit (CPU), a graphics processing unit (GPU), and / or any other processor that controls the operation of the electronic device 1000. The communication module 1200 may be implemented to communicate wirelessly or wired with an external device. The input / output module 1300 may include at least one of a touch sensor, a touch panel, a keyboard, a mouse, a proximity sensor, a microphone, etc. to receive input, and includes at least one of a display, a speaker, etc. to generate an output signal processed by the processor 1100. The memory 1400 may be implemented to store user data, output signals, etc. input through the input / output module 1300. The memory 1400 may be an embedded multimedia card (eMMC), a solid state drive (SSD), a universal flash memory (UFS) device, etc.

[0105] The buffer RAM module 1500 may temporarily store data for processing operations of the electronic device 1000. For example, the buffer RAM 1500 may include a volatile memory such as a double data rate (DDR) synchronous dynamic random access memory (SDRAM), a low power double data rate (LPDDR) SDRAM, a graphics double data rate (GDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), etc.

[0106] although Figure 6 Although not shown in the figure, the electronic device 1000 may further include at least one sensor, such as an image sensor.

[0107] At least one component in the electronic device 1000 may be formed based on the 3D stacked semiconductor device 30 or 40 in which rounded corners are removed or reduced in active regions having different widths in a plurality of units.

[0108] The foregoing is a description of example embodiments and should not be construed as limiting the present disclosure. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the above embodiments without substantially departing from the present disclosure.

[0109] This application is based on and claims priority to U.S. Provisional Application No. 63 / 548,095 filed in the U.S. Patent and Trademark Office on November 10, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: A first active region extending in a first direction and comprising: a first outer corner edge, at which the width of the first active region in the second direction changes smoothly along the first direction; and a first inner corner edge, the width of the first active region changing less smoothly along the first direction at the first inner corner edge than at the first outer corner edge; and a gate structure extending in the second direction and overlapping the first outer corner edge in a third direction, The first direction intersects the second direction horizontally, and the third direction intersects the first direction and the second direction vertically.

2. The semiconductor device according to claim 1, wherein the first active region comprises: a first source / drain region; a second source / drain region; as well as a first channel structure between the first source / drain region and the second source / drain region and overlapping the gate structure in the third direction, The first outer corner edge overlapping the gate structure in the third direction is included in the first channel structure. 3 . The semiconductor device according to claim 2 , wherein the first source / drain region has a first width in the second direction, and the second source / drain region has a second width in the second direction that is different from the first width.

4. The semiconductor device according to claim 1, further comprising: A second active region extending in the first direction, above the first active region, and comprising: a second outer corner edge, at which the width of the second active region in the second direction changes smoothly along the first direction; and a second inner corner edge, the width of the second active region varies less smoothly along the first direction at the second inner corner edge than at the second outer corner edge, The gate structure overlaps with the second outer corner edge in the third direction. 5 . The semiconductor device according to claim 4 , wherein the width of the first active region is greater than the width of the second active region.

6. The semiconductor device according to claim 4, wherein the first active region comprises: a first source / drain region; a second source / drain region; a first channel structure between the first source / drain region and the second source / drain region and overlapping the gate structure in the third direction; a third source / drain region, above the first source / drain region along the third direction; a fourth source / drain region, above the second source / drain region along the third direction; a second channel structure, between the third source / drain region and the fourth source / drain region, and overlapping the gate structure in the third direction, wherein the first outer corner edge is included in the first channel structure, and The second outer corner edge is included in the second channel structure.

7. The semiconductor device according to claim 6, wherein the first source / drain region has a first width in the second direction, the second source / drain region has a second width in the second direction that is different from the first width, and The third source / drain region has a third width in the second direction, and the fourth source / drain region has a fourth width in the second direction that is different from the third width.

8. The semiconductor device according to claim 1, wherein the first active region comprises: a first region on a first side of the first outer corner edge opposite to the first inner corner edge, the first region having a first width in the second direction; as well as a second region on a second side of the first inner corner edge opposite to the first outer corner edge, the second region having a second width in the second direction, wherein the first width is uniform in the first direction, the second width is uniform in the first direction, and The first width is different from the second width.

9. The semiconductor device according to claim 8, wherein the second active region comprises: a third region on the first side of the second outer corner edge opposite to the second inner corner edge, the third region having a third width in the second direction; as well as a fourth region, on the second side of the second inner corner edge opposite to the second outer corner edge, the fourth region having a fourth width in the second direction, wherein the third width is uniform along the first direction, the fourth width is uniform along the first direction, and The third width is different from the fourth width.

10. A semiconductor device comprising: a first channel structure; a first source / drain region connected to the first channel structure; a second source / drain region connected to the first channel structure; as well as a gate structure configured to control a current flow between the first source / drain region and the second source / drain region through the first channel structure, The width of the first channel structure in the second direction changes smoothly along a first direction intersecting with the second direction. 11 . The semiconductor device according to claim 10 , wherein the gate structure overlaps the first channel structure in a third direction intersecting the first direction and the second direction. 12 . The semiconductor device according to claim 10 , wherein a width of the first source / drain region in the second direction is greater than a width of the second source / drain region in the second direction. 13 . The semiconductor device according to claim 10 , wherein the first source / drain region is included in a first cell of the semiconductor device, and the second source / drain region is included in a second cell of the semiconductor device.

14. The semiconductor device according to claim 10, further comprising: a second channel structure, above the first channel structure in the third direction, a third source / drain region over the first source / drain region in a third direction and connected to the second channel structure; a fourth source / drain region over the second source / drain region in the third direction and connected to the second channel structure; and wherein the gate structure is configured to control current flow between the third source / drain region and the fourth source / drain region through the second channel structure, The width of the second channel structure in the second direction changes smoothly along the first direction. 15 . The semiconductor device according to claim 14 , wherein the gate structure overlaps the second channel structure in the third direction. 16 . The semiconductor device according to claim 14 , wherein a width of the third source / drain region in the second direction is greater than a width of the fourth source / drain region in the second direction.

17. A semiconductor device comprising: a first cell including a first active region; a second cell including a second active region, the second cell being adjacent to the first cell in a first direction, and the second active region being aligned with the first active region in the first direction; as well as a gate structure extending in the second direction across at least one of the first active region and the second active region, The first active region has a first width in the second direction, and the second active region has a second width in the second direction that is smaller than the first width, wherein the first active region includes a first outer corner edge, the first width changes smoothly at the first outer corner edge, and the first outer corner edge overlaps the gate structure in a third direction intersecting the first direction and the second direction, and The second active region includes a first inner corner edge, and the second width changes less smoothly at the first inner corner edge than at the first outer corner edge.

18. The semiconductor device according to claim 17, further comprising a first channel structure connecting the first active region and the second active region, The first channel structure overlaps with the gate structure in the third direction and includes the first outer corner edge.

19. The semiconductor device according to claim 17, wherein the first unit further includes a third active region above the first active region in the third direction, and the second unit further includes a fourth active region above the second active region, wherein the fourth active region is aligned with the third active region in the first direction, wherein the third active region has a third width in the second direction, and the fourth active region has a fourth width in the second direction that is smaller than the third width, wherein the third active region comprises a second outer corner edge, at which the third width changes smoothly, and the third outer corner edge overlaps the gate structure in the third direction, and The fourth active region includes a second inner corner edge, and the fourth width changes less smoothly at the second inner corner edge than at the second outer corner edge.

20. The semiconductor device according to claim 19, further comprising a second channel structure connecting the third active region and the fourth active region, The second channel structure overlaps with the gate structure in the third direction and includes the second outer corner edge.

Images