Pwell doping structure of VSWR (Voltage Standing Wave Ratio) for improving radio frequency power VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) and preparation method thereof

Abstract

The invention discloses a Pwell doping structure for improving the VSWR (Voltage Standing Wave Ratio) of a radio frequency power VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) and a preparation method of the Pwell doping structure, and relates to the field of semiconductor materials, so that the radio frequency power VDMOS has the capability of coping with a high voltage standing wave Ratio, the Pwell doping structure for improving the VSWR of the radio frequency power VDMOS at least comprises a substrate; the donor type drift layer is formed on the substrate; acceptor-type doped regions formed in the first region and the second region of the donor-type drift layer; the P-type heavily doped region and the N-type doped region are formed on the acceptor-type doped region, and the P-type heavily doped region is in contact with the N-type doped region; the source electrode metal layers are formed in the first groove and the second groove of the acceptor type doped region; and the source electrode metal layers are in contact with the P-type heavily doped region and the N-type doped region. According to the structure, the parasitic resistance in the VDMOS is reduced, the conduction effect of a parasitic bipolar transistor (BJT) is inhibited, and the capability of the radio frequency power VDMOS for coping with a high voltage standing wave ratio is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor materials, and in particular to a Pwell doping structure for improving the VSWR of a radio frequency power VDMOS and a preparation method thereof. Background Art

[0002] In a solid-state power amplifier, there is usually a large impedance mismatch between the solid-state power amplifier and the antenna. Therefore, during the operation of the RF power tube, energy will be reflected into the RF power device, causing the current and voltage swings inside the device to increase to varying degrees. After the load emission is superimposed on the original voltage and current signals, a high-voltage and high-current standing wave is formed. Due to the effect of the parasitic circuit inside the device, the temperature rises or the parasitic bipolar junction transistor turns on and burns out.

[0003] To address this technical issue, those skilled in the art typically introduce a stepped doping structure into the acceptor-doped region, with an injection energy 30% lower than that of the main acceptor-doped region. This structure disperses the electric field at the cylindrical junction, improving the device's withstand voltage and reducing the likelihood of the parasitic bipolar junction transistor turning on. However, this approach only improves the device's high-voltage withstand capability to withstand high voltage standing wave ratios (VSWRs), and is unable to cope with the high peak RF currents that occur under partial phase conditions of high VSWRs.

[0004] Therefore, how to enable the RF power VDMOS to have the ability to cope with high voltage standing wave ratio has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the Invention

[0005] In view of the above technical status, the present invention provides a Pwell doping structure for improving the VSWR of a radio frequency power VDMOS and a preparation method thereof.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] A Pwell doping structure for improving the VSWR of a radio frequency power VDMOS, comprising at least:

[0008] substrate;

[0009] a donor-type drift layer formed on the substrate;

[0010] an acceptor-type doped region formed in the first region and the second region of the donor-type drift layer;

[0011] A P-type heavily doped region and an N-type doped region are formed on the acceptor-type doped region, wherein the P-type heavily doped region is in contact with the N-type doped region;

[0012] A source metal layer is formed in the first trench and the second trench of the acceptor-type doping region, and the source metal layer is in contact with the P-type heavily doped region and the N-type doped region.

[0013] In an optional embodiment of the present application, the present invention further includes:

[0014] a first gate oxide layer;

[0015] a polysilicon gate formed on the first gate oxide layer, and a second gate oxide layer formed on the polysilicon gate;

[0016] The first gate oxide layer is in contact with the N-type doping region, the donor-type drift layer and a portion of the acceptor-type doping region respectively.

[0017] In an optional embodiment of the present application, the source metal layer includes: a first source metal layer, a second source metal layer and a third source metal layer;

[0018] The first source metal layer is located in a first trench formed by the acceptor-type doped region, the P-type heavily doped region, the N-type doped region, the first gate oxide layer, and the second gate oxide layer of the first region;

[0019] The second source metal layer is located in a second trench formed by the acceptor-type doped region, the P-type heavily doped region, the N-type doped region, and the first gate oxide layer and the second gate oxide layer of the second region;

[0020] The third source metal layer is connected to the first source metal layer and the second source metal layer, and is in contact with the second gate oxide layer.

[0021] In an optional embodiment of the present application, it further includes: a drain metal layer formed at the bottom of the substrate.

[0022] In an optional embodiment of the present application, the P-type heavily doped region and the N-type doped region are stacked sequentially in a depletion layer widening region of the acceptor-type doped region, and the depletion layer widening region is a side of the acceptor-type doped region close to the donor-type drift layer.

[0023] Compared with the prior art, the Pwell doping structure provided by the present invention improves the VSWR of the RF power VDMOS. By introducing a trench in the acceptor-type doping region and forming a source metal layer in the channel, the semiconductor resistance in the acceptor-type doping region is replaced by the metal resistance of the source metal layer. At the same time, by introducing a P-type heavily doped region in the acceptor-type doping region, the parasitic resistance in the VDMOS is reduced, the conduction of the parasitic bipolar transistor BJT is suppressed, and the ability of the RF power VDMOS to cope with high voltage standing wave ratio is improved.

[0024] The present invention also provides a method for preparing a Pwell doping structure for improving the VSWR of a radio frequency power VDMOS, which at least comprises:

[0025] providing a substrate;

[0026] forming a donor-type drift layer on a substrate;

[0027] forming an acceptor-type doping region in the first region and the second region of the donor-type drift layer;

[0028] forming a P-type heavily doped region and an N-type doped region on the acceptor-type doped region, wherein the P-type heavily doped region is in contact with the N-type doped region;

[0029] A source metal layer is formed in the first trench and the second trench of the acceptor-type doping region, and the source metal layer is in contact with the P-type heavily doped region and the N-type doped region.

[0030] In an optional embodiment of the present application, the present invention further includes:

[0031] forming a first gate oxide layer on the N-type doping region, the donor-type drift layer, and a portion of the acceptor-type doping region;

[0032] forming a polysilicon gate on the first gate oxide layer;

[0033] A second gate oxide layer is formed on the polysilicon gate.

[0034] In an optional embodiment of the present application, the present invention further includes:

[0035] According to the position of the N-type doping region in the acceptor-type doping region, etching the first gate oxide layer, the second gate oxide layer, the N-type doping region and a portion of the acceptor-type doping region to form a first trench and a second trench;

[0036] forming a first source metal layer and a second source metal layer on the first trench and the second trench respectively;

[0037] A third source metal layer is formed on the second oxide layer, wherein the third source metal layer connects the first source metal layer and the second source metal layer.

[0038] In an optional embodiment of the present application, forming a P-type heavily doped region and an N-type doped region on the acceptor-type doped region includes:

[0039] Forming an N-type doping region on the acceptor-type doping region by N ion implantation;

[0040] On a side of the N-type doped region close to the donor-type drift layer, forming a P-type heavily doped region by P ion implantation;

[0041] Part of the acceptor-type doped region between the P-type heavily doped region and the donor-type drift layer serves as a depletion layer widening region.

[0042] In an optional embodiment of the present application, the method further includes: generating a drain metal layer at the bottom of the substrate.

[0043] Compared with the prior art, the beneficial effects of the preparation method of the Pwell doping structure for improving the VSWR of the RF power VDMOS provided by the present invention are the same as the beneficial effects of the Pwell doping structure for improving the VSWR of the RF power VDMOS described in the above technical solution, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0045] Figure 1 The stepped Pwell doping structure in the prior art provided in the embodiment of the present application;

[0046] Figure 2 An equivalent circuit diagram of the first VDMOS structure provided in an embodiment of the present application;

[0047] Figure 3 A schematic diagram of a Pwell doping structure for improving the VSWR of a radio frequency power VDMOS provided in an embodiment of the present application;

[0048] Figure 4 Flowchart of a method for preparing a Pwell doping structure for VSWR of a radio frequency power VDMOS provided in an embodiment of the present application;

[0049] Figure 5 A flow chart for generating an acceptor-type doping region provided in an embodiment of the present application;

[0050] Figure 6 A schematic diagram of channel generation provided in an embodiment of the present application;

[0051] Figure 7 This is an equivalent circuit diagram of the second VDMOS structure provided in an embodiment of the present application.

[0052] Reference numerals:

[0053] 101-drain metal layer, 102-substrate;

[0054] 103 - donor-type drift layer, 104 - acceptor-type doped region;

[0055] 105- stepped doping structure, 106- gate oxide layer;

[0056] 107-polysilicon gate, 108-source metal layer;

[0057] 109-N-type doped region, 301-P-type heavily doped region;

[0058] 302-first gate oxide layer, 303-second gate oxide layer;

[0059] 304 - first source metal layer, 305 - second source metal layer;

[0060] 306 - third source metal layer. DETAILED DESCRIPTION

[0061] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0062] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0063] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0064] In the description of the present invention, it should be understood that the terms "up", "down", "front", "back", "left", "right", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0065] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and may encompass internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0066] In a solid-state power amplifier, there is usually a large impedance mismatch between the solid-state power amplifier and the antenna. Therefore, during the operation of the RF power tube, energy will be reflected into the RF power device, causing the current and voltage swings inside the device to increase to varying degrees. After the load emission is superimposed on the original voltage and current signals, a high-voltage and high-current standing wave is formed. Due to the effect of the parasitic circuit inside the device, the temperature rises or the parasitic bipolar junction transistor turns on and burns out.

[0067] In order to solve this technical problem, those skilled in the art usually introduce a stepped doping structure in the acceptor-doped region with an injection energy 30% lower than that of the main acceptor-doped region. Figure 1 , Figure 1 The embodiment of the present application provides a stepped Pwell doping structure in the prior art.

[0068] like Figure 1 As shown, the stepped Pwell doping structure includes: a drain metal layer 101, a substrate 102, a donor-type drift layer 103, an acceptor-type doping region 104, a stepped doping structure 105, a gate oxide layer 106, a polysilicon gate 107, a source metal layer 108, and an N-type doping region 109.

[0069] The core idea is to increase the device's withstand voltage and reduce the likelihood of parasitic bipolar junction transistors turning on by utilizing the electric field at the cylindrical junction of the stepped doping structure 105. However, this approach only improves the device's withstand voltage to resist high voltage standing wave ratios (VSWRs), and cannot handle the high peak RF currents that occur under partial phase conditions of high VSWRs.

[0070] Therefore, how to enable the RF power VDMOS to have the ability to cope with high voltage standing wave ratio has become a technical problem that needs to be solved urgently by those skilled in the art.

[0071] To solve the above technical problems, the present application provides a Pwell doping structure for improving the VSWR of a radio frequency power VDMOS and a preparation method thereof, which are described in detail one by one in the following embodiments.

[0072] In order to facilitate understanding of the embodiments of the present application, the causes of the above technical problems are first described in detail in conjunction with the equivalent circuit diagram of the traditional VDMOS structure.

[0073] Please refer to Figure 2 , Figure 2 This is an equivalent circuit diagram of the first VDMOS structure provided in an embodiment of the present application.

[0074] like Figure 2 As shown in the figure, the parasitic parameters in the traditional VDMOS structure include parasitic resistances Rb1 and Rb2, parasitic capacitance C CB , parasitic diode PN, parasitic bipolar transistor BJT.

[0075] For this circuit structure, during the high voltage standing wave ratio test, the potential failure mechanisms of the RF power VDMOS include: large peak drain voltage and large peak drain current.

[0076] Under the same standing wave ratio and different phase conditions, the RF peak voltage and RF peak current at the drain terminal (D) of the VDMOS are different. Under low phase conditions, a large RF voltage swing may occur. In this case, the RF peak voltage can reach twice the operating voltage, resulting in a high-peak RF drain voltage fault. Under this fault mechanism, the parasitic diode bears the high reverse peak RF withstand voltage. Because the high voltage swing exceeds the device's drain breakdown voltage, the parasitic diode's PN junction turns on and enters avalanche breakdown. Due to the concentrated electric field at the cylindrical junction, avalanche breakdown occurs first at the cylindrical junction. The holes generated by the avalanche then pass through the parasitic resistance in the acceptor-doped region 104. However, as the temperature rises, carrier scattering intensifies, Rb increases, and the voltage drop Vce across Rb also increases. When the voltage drop across Rb exceeds the built-in potential Vbi of the N+P junction, the parasitic bipolar transistor (BJT) turns on. Once the parasitic bipolar transistor BJT turns on, it forms a local low-impedance path, allowing a large amount of current to flow. At this time, although the voltage is low, the power consumption will increase significantly due to the large current, which will cause the local temperature to rise rapidly, and eventually cause the device to overheat or even be damaged.

[0077] Therefore, reducing the parasitic resistance can effectively suppress the problem of large peak drain voltage caused by high-voltage standing wave ratio and improve the reliability of RF power VDMOS under low phase.

[0078] Furthermore, at higher phases (such as around 40°), a larger current swing will occur, resulting in a large peak drain current problem. Unlike the large peak drain voltage, its failure mechanism is due to the parasitic capacitance C CBDuring the charging process, a large current flows into the acceptor-type doped region 104 and flows through the parasitic resistor Rb2, generating a voltage drop Vbe. At the same time, due to the heat generated by DC power consumption, the structure of the parasitic resistance increases. When Vbe is higher than Vbi, the parasitic bipolar transistor BJT is turned on, and the device enters a low-voltage and high-current state locally, eventually causing overheating or even damage to the device.

[0079] Therefore, reducing the parasitic resistance Rb can also effectively suppress the problem of large peak drain current caused by high voltage standing wave ratio, thereby improving the reliability of RF power VDMOS under high phase.

[0080] In order to address the above problems, an embodiment of the present application first provides a Pwell doping structure for improving the VSWR of a radio frequency power VDMOS.

[0081] Please refer to Figure 3 , Figure 3 Schematic diagram of the Pwell doping structure for improving the VSWR of the RF power VDMOS provided in an embodiment of the present application.

[0082] like Figure 3 As shown, the Pwell doping structure for improving the VSWR of the RF power VDMOS includes:

[0083] substrate 102.

[0084] A donor-type drift layer 103 is formed on the substrate 102 .

[0085] Acceptor-type doping regions 104 are formed in the first region and the second region of the donor-type drift layer 103 .

[0086] A P-type heavily doped region 301 and an N-type doped region 109 are formed on the acceptor-type doped region 104 ; wherein the P-type heavily doped region 301 and the N-type doped region 109 are in contact;

[0087] A source metal layer 108 is formed in the first trench and the second trench of the acceptor-type doping region 104 . The source metal layer 108 is in contact with the P-type heavily doped region 301 and the N-type doping region 109 .

[0088] In the embodiment of the present application, the P-type heavily doped region 301 and the N-type doped region 109 are stacked in sequence in the depletion layer widening region of the acceptor-type doped region 104 , and the depletion layer widening region is the side of the acceptor-type doped region 104 close to the donor-type drift layer 103 .

[0089] Furthermore, the Pwell doping structure for improving the VSWR of the RF power VDMOS further includes:

[0090] A first gate oxide layer 302 ; wherein the first gate oxide layer 302 is in contact with the N-type doping region 109 , the donor-type drift layer 103 and a portion of the acceptor-type doping region 104 .

[0091] A polysilicon gate 107 is formed on the first gate oxide layer 302 , and a second gate oxide layer 303 is formed on the polysilicon gate 107 .

[0092] Furthermore, the Pwell doping structure for improving the VSWR of the radio frequency power VDMOS further includes: a drain metal layer 101 .

[0093] The drain metal layer 101 is formed at the bottom of the substrate 102 .

[0094] The source metal layer 108 includes a first source metal layer 304 , a second source metal layer 305 and a third source metal layer 306 .

[0095] The first source metal layer 304 is located in a first trench formed by the acceptor-type doped region 104 , the P-type heavily doped region 301 , the N-type doped region 109 , the first gate oxide layer 302 , and the second gate oxide layer 303 in the first region.

[0096] The second source metal layer 305 is located in a second trench formed by the acceptor-type doped region 104 , the P-type heavily doped region 301 , the N-type doped region 109 , the first gate oxide layer 302 , and the second gate oxide layer 303 in the second region.

[0097] The third source metal layer 306 connects the first source metal layer 304 and the second source metal layer 305 , and contacts the second gate oxide layer.

[0098] In order to facilitate understanding of the Pwell doping structure for improving the VSWR of the RF power VDMOS, the Pwell doping structure for improving the VSWR of the RF power VDMOS is described in detail below in conjunction with a preparation method thereof.

[0099] Please refer to Figure 4 , Figure 4 Flowchart of a method for preparing a Pwell doping structure for VSWR of a radio frequency power VDMOS provided in an embodiment of the present application.

[0100] S401, providing a substrate.

[0101] A substrate refers to a material used as a base support during the manufacturing process of a semiconductor device or integrated circuit. In the embodiments of the present application, the substrate may be a silicon substrate, a silicon carbide substrate, etc., and the present application does not impose any restrictions on this.

[0102] S402 , forming a donor-type drift layer on the substrate.

[0103] The donor drift layer is mainly used to withstand the blocking voltage of the device. When the VDMOS is in the off state, the high voltage between the drain and the source is mainly borne by the donor drift layer.

[0104] In the embodiment of the present application, the donor-type drift layer can be generated on the substrate by chemical vapor deposition (CVD) or low pressure chemical vapor deposition (LPCVD), and the present application does not impose any limitation on this.

[0105] S403 , forming acceptor-type doping regions in the first region and the second region of the donor-type drift layer.

[0106] The acceptor-doped region is primarily used to isolate different active regions and prevent lateral current flow in the substrate. It provides an independent operating area for the source and gate, avoiding the influence of parasitic elements. It also forms a PN junction with the donor-doped drift layer. This PN junction blocks current when the device is turned off and is part of the parasitic bipolar junction transistor (BJT).

[0107] For further information, please refer to Figure 5 , Figure 5 A flow chart for generating an acceptor-type doping region provided in an embodiment of the present application.

[0108] like Figure 5 As shown, Figure 5 The device includes a substrate 102 and a donor-type drift layer 103 formed on the substrate 102 .

[0109] In order to form the acceptor-doped region 104 on the donor-type drift layer 103 and thereby isolate different active regions, the donor-type drift layer 103 is first etched to generate a first region and a second region symmetrical with respect to the central axis of the donor-type drift layer 103. Subsequently, the acceptor-doped region 104 is generated in the first region and the second region by chemical vapor deposition. Alternatively, the donor-type drift layer 103 can be generated by ion implantation in regions symmetrical with respect to the central axis of the donor-type drift layer 103.

[0110] S404 , forming a P-type heavily doped region and an N-type doped region on the acceptor-type doped region, wherein the P-type heavily doped region is in contact with the N-type doped region.

[0111] In an embodiment of the present application, the N-type doped region can be realized by N-type ion beam implantation on the acceptor-type doped region. It should be noted that when performing N-type ion beam implantation, the implantation position of the N-type ion beam needs to ensure that the finally generated N-type doped region does not contact the donor-type drift layer 103.

[0112] Furthermore, the P-type heavily doped region is formed on a side of the N-type doped region close to the substrate 102 by performing P-type ion beam implantation at a large tilt angle.

[0113] At the same time, in order to prevent the high drain voltage caused by the high voltage standing wave ratio from widening the depletion layer to the P-type heavily doped region, sufficient acceptor-type doped region should be reserved between the side of the P-type heavily doped region away from the N-type doped region and the donor-type drift layer 103 to serve as the depletion layer widening area.

[0114] S405 , forming a source metal layer in the first trench and the second trench of the acceptor-type doping region, wherein the source metal layer is in contact with the P-type heavily doped region and the N-type doped region.

[0115] Specifically, the above S405 includes:

[0116] According to the position of the N-type doping region in the acceptor-type doping region, etching the first gate oxide layer, the second gate oxide layer, the N-type doping region and a portion of the acceptor-type doping region to form a first trench and a second trench;

[0117] forming a first source metal layer and a second source metal layer on the first trench and the second trench respectively;

[0118] A third source metal layer is formed on the second oxide layer, wherein the third source metal layer connects the first source metal layer and the second source metal layer.

[0119] For further information, please refer to Figure 6 , Figure 6 A schematic diagram of channel generation provided in an embodiment of the present application.

[0120] like Figure 6 As shown, Figure 6 The structure includes: a substrate 102 , a donor-type drift layer 103 , an acceptor-type doping region 104 , an N-type doping region 109 , a gate oxide layer 106 , and a polysilicon gate 107 .

[0121] In another optional embodiment of the present application, the gate oxide layer 106 , the N-type doping region 109 and part of the acceptor-type doping region 104 may be etched according to the position of the N-doping region to obtain the first trench and the second trench.

[0122] In another optional embodiment of the present application, the N-type doping region 109 and part of the acceptor-type doping region may be etched to obtain the first channel and the second channel according to the position of the N-doping region without forming a gate oxide layer.

[0123] In particular, for the P-type heavily doped region, the P-type heavily doped region can be obtained by performing P-type ion implantation in combination with the position of the N-type doped region 109 after the first channel and the second channel are formed, or by performing P-type ion implantation in combination with the position of the N-type doped region 109 before the first channel and the second channel are formed. This application does not impose any restrictions on this.

[0124] Furthermore, for the gate of the VDMOS: the method also includes: forming a first gate oxide layer on the N-type doped region, the donor-type drift layer and part of the acceptor-type doped region; forming a polysilicon gate on the first gate oxide layer; and forming a second gate oxide layer on the polysilicon gate 107.

[0125] Furthermore, for the drain of the VDMOS, the method further includes: generating a drain metal layer at the bottom of the substrate 102 .

[0126] For further information, please refer to Figure 7 , Figure 7 This is an equivalent circuit diagram of the second VDMOS structure provided in an embodiment of the present application.

[0127] like Figure 7 As shown, Figure 7 The equivalent circuit diagram shown is specifically an equivalent circuit diagram of the Pwell doping structure for improving the VSWR of the radio frequency power VDMOS obtained by the above preparation method.

[0128] Figure 7 Including: parasitic resistance Rb1, parasitic capacitance C CB , parasitic diode PN, parasitic bipolar transistor BJT.

[0129] Compared with the traditional VDMOS circuit, the Pwell doping structure for improving the VSWR of the RF power VDMOS obtained by the preparation method provided in the present application forms a groove in the acceptor-type doping region while introducing an N-type doping region in the acceptor-type doping region, and then forms a source metal layer in the groove, thereby shortening the conduction path of the hole current in the acceptor-type doping region caused by the voltage standing wave ratio. The metal resistance of the source metal layer replaces the semiconductor resistance in the acceptor-type doping region, reducing the Rb2 part in the equivalent circuit diagram, thereby reducing the parasitic resistance in the acceptor-type doping region. Under the same circuit conditions, it can effectively reduce the voltage drop Vbe generated by the parasitic resistance Rb2, and suppress the conduction of the parasitic bipolar transistor BJT. At the same time, by introducing a P-type heavily doped region in the acceptor-type doping region, it is beneficial to reduce the parasitic resistance Rb1 of the VDMOS, and under the same current conditions, it can play a role in suppressing the conduction of the parasitic bipolar transistor BJT.

[0130] To sum up, the Pwell doping structure and preparation method for improving the VSWR of the RF power VDMOS provided in the embodiments of the present application introduce trenches in the acceptor-type doping region and form a source metal layer in the channel, thereby replacing the semiconductor resistance in the acceptor-type doping region with the metal resistance of the source metal layer. At the same time, by introducing a P-type heavily doped region in the acceptor-type doping region, it is beneficial to reduce the parasitic resistance in the VDMOS, inhibit the conduction of the parasitic bipolar transistor BJT, and improve the ability of the RF power VDMOS to cope with high voltage standing wave ratio.

[0131] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0132] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which are intended to fall within the scope of the present disclosure.

Claims

1. A Pwell doping structure for improving the VSWR of a radio frequency power VDMOS, characterized in that: At least: substrate; a donor-type drift layer formed on the substrate; An acceptor-type doped region formed in a first region and a second region of the donor-type drift layer; A P-type heavily doped region and an N-type doped region formed on the acceptor-type doped region, wherein the P-type heavily doped region is in contact with the N-type doped region; A source metal layer is formed in the first trench and the second trench of the acceptor-type doping region, and the source metal layer is in contact with the P-type heavily doped region and the N-type doped region.

2. The Pwell doping structure for improving the VSWR of the RF power VDMOS according to claim 1, characterized in that: Also includes: a first gate oxide layer; a polysilicon gate formed on the first gate oxide layer, and a second gate oxide layer formed on the polysilicon gate; The first gate oxide layer is in contact with the N-type doping region, the donor-type drift layer and a portion of the acceptor-type doping region respectively.

3. The Pwell doping structure for improving the VSWR of the RF power VDMOS according to claim 2, characterized in that: The source metal layer comprises: a first source metal layer, a second source metal layer and a third source metal layer; The first source metal layer is located in a first trench formed by the acceptor-type doped region, the P-type heavily doped region, the N-type doped region, the first gate oxide layer and the second gate oxide layer of the first region; The second source metal layer is located in a second trench formed by the acceptor-type doped region, the P-type heavily doped region, the N-type doped region, the first gate oxide layer and the second gate oxide layer of the second region; The third source metal layer connects the first source metal layer and the second source metal layer and contacts the second gate oxide layer.

4. The Pwell doping structure for improving the VSWR of the RF power VDMOS according to claim 1, characterized in that: Also includes: A drain metal layer is formed at the bottom of the substrate.

5. The Pwell doping structure for improving the VSWR of the RF power VDMOS according to claim 1, characterized in that: The P-type heavily doped region and the N-type doped region are sequentially stacked in a depletion layer widening region of the acceptor-type doped region, and the depletion layer widening region is a side of the acceptor-type doped region close to the donor-type drift layer.

6. A method for preparing a Pwell doping structure for improving the VSWR of a radio frequency power VDMOS, characterized in that: At least: providing a substrate; forming a donor-type drift layer on a substrate; forming an acceptor-type doping region in a first region and a second region of the donor-type drift layer; forming a P-type heavily doped region and an N-type doped region on the acceptor-type doped region, wherein the P-type heavily doped region is in contact with the N-type doped region; A source metal layer is formed in the first trench and the second trench of the acceptor-type doping region, and the source metal layer is in contact with the P-type heavily doped region and the N-type doped region.

7. The method according to claim 6, characterized in that Also includes: forming a first gate oxide layer on the N-type doping region, the donor-type drift layer and a portion of the acceptor-type doping region; forming a polysilicon gate on the first gate oxide layer; A second gate oxide layer is formed on the polysilicon gate.

8. The method according to claim 7, characterized in that: Also includes: According to the position of the N-type doping region in the acceptor-type doping region, etching the first gate oxide layer, the second gate oxide layer, the N-type doping region and a portion of the acceptor-type doping region to form a first trench and a second trench; forming a first source metal layer and a second source metal layer on the first trench and the second trench respectively; A third source metal layer is formed on the second oxide layer, wherein the third source metal layer connects the first source metal layer and the second source metal layer.

9. The method according to claim 6, characterized in that The forming of a P-type heavily doped region and an N-type doped region on the acceptor-type doped region comprises: On the acceptor-type doped region, an N-type doped region is formed by N ion implantation; On a side of the N-type doped region close to the donor-type drift layer, forming a P-type heavily doped region by P ion implantation; Wherein, a part of the acceptor-type doped region exists between the P-type heavily doped region and the donor-type drift layer as a depletion layer widening region.

10. The method according to claim 6, characterized in that Also includes: A drain metal layer is grown at the bottom of the substrate.

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