Terminal structure of groove type silicon carbide power device and preparation method

Abstract

The invention discloses a terminal structure of a groove-type silicon carbide power device and a preparation method, and relates to the technical field of semiconductors, the terminal structure comprises an N-type substrate, the N-type substrate is provided with an N-Drift region and an N-CSL layer, the N-CSL layer is provided with a P + transition region and a plurality of P + field limiting rings, the P + transition region and the P + field limiting rings are sequentially arranged from inside to outside, and the N-Drift region and the N-CSL layer are sequentially arranged from inside to outside. Annular grooves are formed between the P + transition region and the P + field limiting rings and between the P + field limiting rings, and the annular grooves are completely filled with silicon dioxide. According to the invention, the influence of positively charged N ions on the terminal structure can be reduced through the grooves, and the filled silicon dioxide can reduce the electric field at the P + field limiting ring on the premise of reducing the cost, thereby effectively improving the voltage resistance of the terminal structure. Compared with the prior art, the technical problems that an existing terminal is low in voltage resistance, poor in stability, complex in preparation process and high in cost are solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a terminal structure and a preparation method of a trench-type silicon carbide power device. Background Art

[0002] Semiconductor power devices are the core of efficient conversion, control and regulation of electric energy. In recent years, silicon carbide power devices, with their excellent high-voltage resistance, high-temperature resistance, low-loss performance, can effectively meet the high-efficiency, small and lightweight requirements of electronic power systems, and have obvious advantages in the fields of new energy vehicles, photovoltaic power generation, rail transportation, smart grids, etc. Therefore, the research and application of silicon carbide power devices has become one of the frontiers and hot spots of semiconductor power device research.

[0003] In the process of silicon carbide semiconductor power devices, terminal technology usually refers to the technology used to control and improve the electric field distribution at the edge of semiconductor devices. In silicon carbide trench gate metal oxide semiconductor field effect transistors, the application of terminal technology is particularly critical. A good terminal structure design can effectively improve device performance, ensure stable operation of the device, and improve manufacturing yield. The introduction of terminal technology has the following advantages: First, the electric field distribution at the edge of the device can be controlled, and the electric field strength at the edge can be reduced, thereby increasing the overall breakdown voltage of the device, reducing the loss of the device during the switching process, and improving the overall efficiency.

[0004] Second, it can disperse the electric field at the edge to avoid early breakdown caused by excessive local electric field. In addition, controlling the edge electric field helps reduce defects caused by edge effects and improve the reliability and stability of the device.

[0005] Third, edge parasitic capacitance and parasitic resistance can be reduced, thereby improving the overall performance of the device.

[0006] Fourth, it can make the edges smoother, facilitate packaging, and reduce stress damage that may occur during the packaging process.

[0007] Fifth, edge defects can be reduced, thereby improving the manufacturing yield of semiconductor devices.

[0008] From the above content, it can be seen that terminal technology plays a vital role in the design of power semiconductor devices, especially for wide bandgap materials such as silicon carbide. Reasonable terminal design is of great significance to improving the performance and reliability of the device.

[0009] At present, silicon carbide semiconductor power devices usually have a planar junction terminal structure and a trench terminal structure, such as the planar junction terminal structure disclosed in the patent document with publication number CN118198106A and the trench terminal structure disclosed in the patent document with publication number CN212625588U. Compared with the planar junction terminal structure, the trench terminal structure has the advantages of increased breakdown voltage, uniform surface electric field, etc. and is being used more and more widely.

[0010] In addition, the trench junction terminal structure disclosed in the above patent document includes a silicon carbide substrate with a first conductivity type, a silicon carbide epitaxial layer grown on the silicon carbide substrate, a plurality of trenches etched on the silicon carbide epitaxial layer, and a second conductivity type injection region injected into the trench. The terminal has the advantage of better dispersing the electric field through the trench structure combined with the passivation layer filling, but after careful analysis, it is found that the terminal still has the following technical problems: 1. Although the terminal has the function of dispersing the electric field through the groove structure combined with the passivation layer filling, it does not provide specific experimental data, resulting in the unknown function of dispersing the electric field. After careful analysis by the inventors, it is found that its voltage resistance is still low.

[0011] 2. The terminal uses BPSG (boron phosphorus silicon glass) / Si3N4 (silicon nitride) as the passivation layer. However, the preparation of BPSG requires strict control of process parameters and raw material purity. The production process is relatively complicated and difficult to produce. In addition, BPSG easily reacts with water vapor in the air to generate boric acid and phosphoric acid, resulting in poor stability and reduced pressure resistance. Si3N4 has extremely high hardness and needs to be produced under high temperature and high pressure conditions. Its production process is also relatively complicated, and the raw materials are expensive, and the requirements for processing technology and equipment are also very high. Moreover, when subjected to impact or large stress, it is easy to crack or even break. Correspondingly, the terminal has high cost, poor stability and low pressure resistance.

[0012] 3. In order to reduce the cell size and enhance the current capacity of the channel, the current mainstream silicon carbide devices will use secondary epitaxy or high-energy ion injection to form a current extension layer (CSL). However, this terminal only has a lightly doped drift region, and there is no secondary epitaxy or high-energy ion injection to form a current extension layer with a higher doping concentration, which makes it unsuitable for the current mainstream trench silicon carbide devices.

[0013] To this end, it is necessary to provide a new technology that is suitable for the current mainstream trench silicon carbide devices and can improve the breakdown voltage, simplify the process and reduce the cost to solve the above technical problems. Summary of the invention

[0014] In order to overcome the above-mentioned technical problems existing in the prior art, the present invention further provides a terminal structure and a preparation method of a trench-type silicon carbide power device. The present invention adopts a structure in which a P+ transition region and a P+ field limiting ring are arranged on the N-CSL layer, and a groove is formed between the P+ transition region and the P+ field limiting ring and between each P+ field limiting ring, and silicon dioxide is filled in the groove. In actual use, the N-CSL layer will ionize a large number of positively charged N ions when withstand voltage, and the present invention can reduce the influence of positively charged N ions on the terminal structure when withstand voltage through the groove, and by filling silicon dioxide in the groove, the electric field at the P+ field limiting ring can be reduced while reducing costs, thereby effectively improving the voltage resistance of the terminal structure. In addition, the preparation process of the present invention is relatively simple. Compared with the prior art, it not only solves the technical problems of low voltage resistance, poor stability, complex preparation process and high cost of the existing terminal, but is also particularly suitable for the current mainstream trench-type silicon carbide devices.

[0015] To achieve the above purpose, the technical solution adopted by the present invention is as follows: In a first aspect, the present invention provides a terminal structure of a trench-type silicon carbide power device, comprising an N-type substrate, on which an N-Drift region and an N-CSL layer are sequentially arranged, on which an annular P+ transition region and a plurality of P+ field limiting rings are respectively arranged by high-energy ion implantation, the P+ transition region and the P+ field limiting rings both penetrate the N-CSL layer and contact the N-Drift region, the P+ transition region and the plurality of P+ field limiting rings are sequentially arranged from the inside to the outside, annular grooves are arranged between the P+ transition region and the innermost P+ field limiting ring and between each P+ field limiting ring, the annular grooves are respectively formed by completely etching the N-CSL layer between the P+ transition region and the P+ field limiting ring and completely etching the N-CSL layer between each P+ field limiting ring, and the annular grooves are completely filled with silicon dioxide.

[0016] The P+ field limiting rings are evenly arranged on the N-CSL layer, the number of the P+ field limiting rings is 20-22, and the width of all the annular grooves is 1.5-2.5 μm.

[0017] The doping concentration of the P+ transition region and the P+ field limiting ring is 10 19 -10 20 cm -3 Magnitude.

[0018] The upper surface of the P+ transition region and the upper surface of the P+ field limiting ring are both at the same level as the upper surface of the N-CSL layer, the upper surface of the silicon dioxide is at the same level as the upper surface of the N-CSL layer, or the upper surface of the silicon dioxide is higher than the upper surface of the N-CSL layer.

[0019] The thickness of the N-CSL layer is 1.5-2.2 μm, the width of the P+ transition region is 40-200 μm, and the width of the P+ field limiting ring is 1-3 μm.

[0020] The N-Drift region is formed by epitaxial doping, the N-CSL layer is formed by epitaxial doping or high-energy ion implantation, and the doping concentration of the N-CSL layer is higher than the doping concentration of the N-Drift region.

[0021] The doping concentration of the N-type substrate is 10 19 -10 20 cm -3 The doping concentration of N-Drift region is 10 14 -10 16 cm -3 The doping concentration of N-CSL layer is 10 15 -10 17 cm -3 Magnitude.

[0022] An N+ cut-off ring is formed around the upper surface of the N-CSL layer by ion implantation, and the P+ transition region and the P+ field limiting ring are both located inside the N+ cut-off ring.

[0023] In a second aspect, the present invention provides a method for preparing a terminal structure of a trench silicon carbide power device, comprising the following steps: Step 1: sequentially arrange an N-Drift region and an N-CSL layer on the upper surface of a heavily doped N-type substrate; Step 2: Set a P+ transition region and several P+ field limiting rings on the N-CSL layer by high-energy ion implantation. The doping concentrations of the P+ transition region and the P+ field limiting rings are the same. The P+ transition region and the P+ field limiting rings penetrate the N-CSL layer and contact the N-Drift region. The P+ transition region and the several P+ field limiting rings are sequentially set from the inside to the outside. Step 3: Completely etch the N-CSL layer between the P+ transition region and the P+ field limiting ring and completely etch the N-CSL layer between each P+ field limiting ring, form annular grooves between the P+ transition region and the P+ field limiting ring and between each P+ field limiting ring, and fill all the annular grooves with silicon dioxide; Step 4: Add an N+ cutoff ring to the P+ field limiting ring termination area through ion implantation, and then anneal at high temperature to activate the ions to complete the preparation.

[0024] In a third aspect, the present invention provides a method for preparing a terminal structure of a trench silicon carbide power device, comprising the following steps: Step 1: sequentially arrange an N-Drift region and an N-CSL layer on the upper surface of a heavily doped N-type substrate; Step 2: Aluminum ions are implanted into the N-CSL layer to form a P+ ring that penetrates the N-CSL layer and contacts the N-Drift region; Step 3: Etch part of the P+ ring until the N-Drift area is exposed, and form a number of annular grooves on the P+ ring. All the annular grooves are evenly distributed, and all the annular grooves are filled with silicon dioxide. The P+ ring is separated into a P+ transition area and a number of P+ field limiting rings by silicon dioxide. Step 4: Add an N+ cutoff ring to the P+ field limiting ring termination area through ion implantation, and then activate the ions by high temperature annealing to complete the preparation.

[0025] By adopting the above technical solution, the beneficial technical effects of the present invention are: 1. Currently, in mainstream trench MOSFETs, it is usually necessary to introduce an N-CSL layer (current spreading layer) with a high N ion concentration to improve the electrical performance and reliability of power devices. However, in the terminal structure, the N-CSL layer with a high N ion concentration will ionize a large number of positively charged N ions when withstand voltage, and the positively charged N ions will emit electric lines that terminate at the P+ field limiting ring, resulting in an increase in the electric field at the P+ field limiting ring and an increased risk of breakdown.

[0026] To this end, the present invention is designed to set the P+ transition zone and several P+ field limiting rings on the N-CSL layer, and form an annular groove by completely etching the N-CSL layer between the P+ transition zone and the P+ field limiting ring and between each P+ field limiting ring, and fill the annular groove with silicon dioxide. When the terminal of this specific structure is in use, the annular groove has the effect of reducing the influence of positively charged N ions on the terminal structure during voltage resistance, and the silicon dioxide filled in the annular groove has the effect of optimizing the surface electric field distribution and increasing the breakdown voltage. The combination of the two can reduce the electric field at the P+ field limiting ring under the premise of reducing costs, thereby improving the voltage resistance of the terminal structure. In addition, the preparation process of the present invention is relatively simple. Compared with the prior art, the present invention not only effectively improves the voltage resistance and stability of the terminal, but also simplifies the preparation process and reduces the cost, and is particularly suitable for the current mainstream trench silicon carbide devices.

[0027] It should also be noted that the present invention specifically limits the filling of silicon dioxide in the annular groove, which has the effect of achieving the highest voltage resistance under the premise of ensuring low cost. If other materials are used instead of silicon dioxide, it will lead to increased costs and / or affect the voltage resistance effect. In addition, if silicon dioxide does not fill the annular groove, it will lead to uneven electric field distribution, thereby affecting the voltage resistance effect of the terminal.

[0028] In detail, the advantages of the preparation method of the present invention are substantially the same as those of the terminal structure and will not be described in detail.

[0029] 2. The present invention sets the P+ field limiting rings uniformly, which is conducive to making the electric field distribution on the terminal surface more uniform. In addition, the present invention sets the number of P+ field limiting rings to 20-22, sets the width of all annular grooves to 1.5-2.5 μm, and sets the doping concentration of the P+ transition region and the P+ field limiting ring to 10 19 -10 20 cm -3 By combining the specific width of the annular groove, the specific number of P+ field limiting rings and the specific doping concentration, the device can achieve a withstand voltage of about 1.9kV while keeping the device area small. It should be noted that if the width of the annular groove is less than 1.5μm, the number of P+ field limiting rings is less than 20, and the doping concentration is less than 10 19 cm -3 On the contrary, although the voltage resistance can be further improved, the improvement in voltage resistance is small and the device area and cost will be increased.

[0030] 3. The present invention sets the upper surface of the P+ transition zone and the upper surface of the P+ field limiting ring to be at the same horizontal plane as the upper surface of the N-CSL layer, and makes the upper surface of the silicon dioxide and the upper surface of the N-CSL layer at the same horizontal plane, or the upper surface of the silicon dioxide is higher than the upper surface of the N-CSL layer, which has the advantages of simple process and reduced cost, and can ensure uniform electric field distribution.

[0031] 4. The present invention sets the thickness of the N-CSL layer to 1.5-2.2 μm, the width of the P+ transition region to 40-200 μm, and the width of the P+ field limiting ring to 1-3 μm. The use of these specific parameters is conducive to improving the pressure resistance while reducing the cell area.

[0032] 5. The present invention adopts a low-doping concentration N-Drift region to have the effect of carrying a higher forward withstand voltage; the high-doping concentration N-CSL layer has the ability to increase the current capacity of the cell region, while also reducing leakage current and reducing specific on-resistance.

[0033] 6. The present invention sets the doping concentration of the N-type substrate to 10 19 -10 20 cm -3 The doping concentration of N-Drift region is set to 10 14 -10 16 cm -3 The doping concentration of the N-CSL layer is set to 10 15 -10 17 cm -3 The order of magnitude can maintain a low production cost while achieving the above-mentioned ideal voltage resistance level.

[0034] 7. The present invention is advantageous in limiting the magnitude of the breakdown current during reverse breakdown through the N+ cut-off ring, thereby protecting the normal operation of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a three-dimensional schematic diagram of the 1 / 4 terminal structure of the present invention; Figure 2 It is a plan view of the 1 / 4 terminal structure in step 1; Figure 3 It is a plan view of the 1 / 4 terminal structure in step 2; Figure 4 It is a plan view of the 1 / 4 terminal structure in step 3; Figure 5 It is a plan view of the 1 / 4 terminal structure in step 4; Figure 6 It is a schematic diagram of a 1 / 4 cross section from the N+ cutoff ring region to the P+ transition region; Figure 7 This is a simulation experiment diagram of Example 1; Figure 8 It is a simulation experiment diagram of Example 2; Fig. 9 This is a simulation experiment diagram of Example 3; Fig.10 This is a simulation experiment diagram of Example 4.

[0036] The markings in the figure are: 1.1, N-type substrate, 1.2, N-Drift region, 1.3, N-CSL layer, 1.4, P+ transition region, 1.5, P+ field limiting ring, 1.6, silicon dioxide, 1.7, N+ cut-off ring. DETAILED DESCRIPTION

[0037] Example 1 like Figure 1 As shown, this embodiment provides a terminal structure of a trench-type silicon carbide power device, including an N-type substrate 1.1, on which an N-Drift region 1.2 and an N-CSL layer 1.3 are sequentially arranged, the N-Drift region 1.2 is formed by epitaxial doping, the N-CSL layer 1.3 can be formed by secondary epitaxial doping or high-energy ion implantation, and the doping concentration of the N-CSL layer 1.3 is higher than the doping concentration of the N-Drift region 1.2. Then, a P+ transition region 1.4 and a plurality of P+ field limiting rings 1.5 are respectively arranged on the N-CSL layer 1.3 by high-energy ion implantation, the upper surface of the P+ transition region 1.4 and the upper surface of the P+ field limiting ring 1.5 are both at the same level as the upper surface of the N-CSL layer 1.3, the P+ field limiting ring 1.5 is uniformly arranged on the N-CSL layer 1.3, and the doping concentrations of the P+ transition region 1.4 and the P+ field limiting ring 1.5 are both 10 19 cm-3 The number of P+ transition regions 1.4 is 1, and the number of P+ field limiting rings 1.5 is 20. Both the P+ transition region 1.4 and the P+ field limiting ring 1.5 penetrate the N-CSL layer 1.3 and contact the N-Drift region 1.2. The P+ transition region 1.4 and the P+ field limiting ring 1.5 are both annular, and the P+ transition region 1.4 and several P+ field limiting rings 1.5 are arranged in sequence from the inside to the outside. Annular grooves are arranged between the P+ transition region 1.4 and the innermost P+ field limiting ring 1.5 and between each P+ field limiting ring 1.5. These annular grooves are formed by completely etching the N-CSL layer 1.3 between the P+ transition region 1.4 and the P+ field limiting ring 1.5 and completely etching the N-CSL layer 1.3 between each P+ field limiting ring 1.5, and the width of all the annular grooves is 1.5μm. Finally, all the annular grooves are completely filled with silicon dioxide 1.6. After all the annular grooves are filled with silicon dioxide 1.6, the upper surface of silicon dioxide 1.6 is at the same level as the upper surface of the N-CSL layer 1.3, or the upper surface of silicon dioxide 1.6 is higher than the upper surface of the N-CSL layer 1.3, so as to ensure uniform electric field distribution.

[0038] According to a preferred implementation of this embodiment, the thickness of the N-CSL layer 1.3 is 1.5 μm, the width of the P+ transition region 1.4 is 40 μm, and the width of the P+ field limiting ring 1.5 is 1 μm, which is beneficial to improving the voltage resistance level while reducing the cell area.

[0039] According to another preferred implementation of this embodiment, the doping concentration of the N-type substrate 1.1 is 10 19 cm -3 The doping concentration of N-Drift region 1.2 is 10 14 cm -3 The doping concentration of N-CSL layer 1.3 is 10 15 cm -3 The magnitude is conducive to maintaining a low production cost while achieving the above-mentioned ideal voltage resistance level.

[0040] According to another preferred implementation of this embodiment, Figure 1 As shown, an N+ cut-off ring 1.7 is formed around the upper surface of the N-CSL layer 1.3 by ion implantation, and the P+ transition region 1.4 and the P+ field limiting ring 1.5 are both located inside the N+ cut-off ring 1.7. The spacing between the N+ cut-off ring 1.7 and the outermost P+ field limiting ring 1.5 needs to ensure the minimum width of limiting the terminal PN junction diffusion, which needs to be determined according to actual conditions. The N+ cut-off ring 1.7 can limit the magnitude of the breakdown current during reverse breakdown, thereby protecting the normal operation of the chip.

[0041] The terminal structure of this embodiment is a kind of trench junction terminal of silicon carbide power device. The N-CSL current expansion layer is formed by secondary epitaxy or high-energy ion implantation to meet the current design requirements of silicon carbide power devices. When designing the terminal, in order to eliminate the high concentration of positively charged N ions in the N-CSL layer 1.3, the N-CSL layer 1.3 between the P+ transition region 1.4 and the P+ field limiting ring 1.5 and between each P+ field limiting ring 1.5 is completely etched, and the insulating dielectric silicon dioxide 1.6 is filled until the trench is filled. At the same time, the uniformly arranged P+ field limiting ring 1.5 makes the electric field distribution on the terminal surface more uniform, and finally achieves the purpose of increasing the terminal breakdown voltage. In addition, the manufacturing process of this embodiment is relatively simple, and because of the use of specific parameters, it also has the advantages of reducing the cell area, reducing costs and improving the withstand voltage level.

[0042] Example 2 like Figure 1 As shown, this embodiment provides a terminal structure of a trench-type silicon carbide power device, including an N-type substrate 1.1, on which an N-Drift region 1.2 and an N-CSL layer 1.3 are sequentially arranged, the N-Drift region 1.2 is formed by epitaxial doping, the N-CSL layer 1.3 can be formed by secondary epitaxial doping or high-energy ion implantation, and the doping concentration of the N-CSL layer 1.3 is higher than the doping concentration of the N-Drift region 1.2. Then, a P+ transition region 1.4 and a plurality of P+ field limiting rings 1.5 are respectively arranged on the N-CSL layer 1.3 by high-energy ion implantation, the upper surface of the P+ transition region 1.4 and the upper surface of the P+ field limiting ring 1.5 are both at the same level as the upper surface of the N-CSL layer 1.3, the P+ field limiting ring 1.5 is uniformly arranged on the N-CSL layer 1.3, and the doping concentrations of the P+ transition region 1.4 and the P+ field limiting ring 1.5 are both 5*10 19 cm -3The number of P+ transition regions 1.4 is 1, and the number of P+ field limiting rings 1.5 is 21. Both the P+ transition region 1.4 and the P+ field limiting ring 1.5 penetrate the N-CSL layer 1.3 and contact the N-Drift region 1.2. The P+ transition region 1.4 and the P+ field limiting ring 1.5 are both annular, and the P+ transition region 1.4 and several P+ field limiting rings 1.5 are arranged in sequence from the inside to the outside. Annular grooves are arranged between the P+ transition region 1.4 and the innermost P+ field limiting ring 1.5 and between each P+ field limiting ring 1.5. These annular grooves are formed by completely etching the N-CSL layer 1.3 between the P+ transition region 1.4 and the P+ field limiting ring 1.5 and completely etching the N-CSL layer 1.3 between each P+ field limiting ring 1.5, and the width of all annular grooves is 2μm. Finally, all the annular grooves are completely filled with silicon dioxide 1.6. After the annular grooves are filled with silicon dioxide 1.6, the upper surface of silicon dioxide 1.6 is at the same level as the upper surface of the N-CSL layer 1.3, or the upper surface of silicon dioxide 1.6 is higher than the upper surface of the N-CSL layer 1.3, so as to ensure uniform electric field distribution.

[0043] According to a preferred implementation of this embodiment, the thickness of the N-CSL layer 1.3 is 1.8 μm, the width of the P+ transition region 1.4 is 120 μm, and the width of the P+ field limiting ring 1.5 is 2 μm, which is beneficial to improving the voltage resistance level while reducing the cell area.

[0044] According to another preferred implementation of this embodiment, the doping concentration of the N-type substrate 1.1 is 5*10 19 cm -3 The doping concentration of N-Drift region 1.2 is 10 15 cm -3 The doping concentration of N-CSL layer 1.3 is 10 16 cm -3 The magnitude is conducive to maintaining a low production cost while achieving the above-mentioned ideal voltage resistance level.

[0045] According to another preferred implementation of this embodiment, Figure 1 As shown, an N+ cut-off ring 1.7 is formed around the upper surface of the N-CSL layer 1.3 by ion implantation, and the P+ transition region 1.4 and the P+ field limiting ring 1.5 are both located inside the N+ cut-off ring 1.7. The spacing between the N+ cut-off ring 1.7 and the outermost P+ field limiting ring 1.5 needs to ensure the minimum width of limiting the terminal PN junction diffusion, which needs to be determined according to actual conditions. The N+ cut-off ring 1.7 can limit the magnitude of the breakdown current during reverse breakdown, thereby protecting the normal operation of the chip.

[0046] The manufacturing process of this embodiment is relatively simple, and can also achieve the purpose of increasing the terminal breakdown voltage, and also has the advantages of reducing the cell area, reducing the cost and improving the withstand voltage level.

[0047] Example 3 like Figure 1 As shown, this embodiment provides a terminal structure of a trench-type silicon carbide power device, including an N-type substrate 1.1, on which an N-Drift region 1.2 and an N-CSL layer 1.3 are sequentially arranged, the N-Drift region 1.2 is formed by epitaxial doping, the N-CSL layer 1.3 can be formed by secondary epitaxial doping or high-energy ion implantation, and the doping concentration of the N-CSL layer 1.3 is higher than the doping concentration of the N-Drift region 1.2. Then, a P+ transition region 1.4 and a plurality of P+ field limiting rings 1.5 are respectively arranged on the N-CSL layer 1.3 by high-energy ion implantation, the upper surface of the P+ transition region 1.4 and the upper surface of the P+ field limiting ring 1.5 are both at the same level as the upper surface of the N-CSL layer 1.3, the P+ field limiting ring 1.5 is uniformly arranged on the N-CSL layer 1.3, and the doping concentrations of the P+ transition region 1.4 and the P+ field limiting ring 1.5 are both 10 20 cm -3 The number of P+ transition regions 1.4 is 1, and the number of P+ field limiting rings 1.5 is 22. Both the P+ transition region 1.4 and the P+ field limiting ring 1.5 penetrate the N-CSL layer 1.3 and contact the N-Drift region 1.2. The P+ transition region 1.4 and the P+ field limiting ring 1.5 are both annular, and the P+ transition region 1.4 and several P+ field limiting rings 1.5 are arranged in sequence from the inside to the outside. Annular grooves are arranged between the P+ transition region 1.4 and the innermost P+ field limiting ring 1.5 and between each P+ field limiting ring 1.5. These annular grooves are formed by completely etching the N-CSL layer 1.3 between the P+ transition region 1.4 and the P+ field limiting ring 1.5 and completely etching the N-CSL layer 1.3 between each P+ field limiting ring 1.5, and the width of all annular grooves is 2.5μm. Finally, all the annular grooves are completely filled with silicon dioxide 1.6. After the annular grooves are filled with silicon dioxide 1.6, the upper surface of silicon dioxide 1.6 is at the same level as the upper surface of the N-CSL layer 1.3, or the upper surface of silicon dioxide 1.6 is higher than the upper surface of the N-CSL layer 1.3, so as to ensure uniform electric field distribution.

[0048] According to a preferred implementation of this embodiment, the thickness of the N-CSL layer 1.3 is 2.2 μm, the width of the P+ transition region 1.4 is 200 μm, and the width of the P+ field limiting ring 1.5 is 3 μm, which is beneficial to improving the voltage resistance level while reducing the cell area.

[0049] According to another preferred implementation of this embodiment, the doping concentration of the N-type substrate 1.1 is 1020 cm -3 The doping concentration of N-Drift region 1.2 is 10 16 cm -3 The doping concentration of N-CSL layer 1.3 is 10 17 cm -3 The magnitude is conducive to maintaining a low production cost while achieving the above-mentioned ideal voltage resistance level.

[0050] According to another preferred implementation of this embodiment, Figure 1 As shown, an N+ cut-off ring 1.7 is formed around the upper surface of the N-CSL layer 1.3 by ion implantation, and the P+ transition region 1.4 and the P+ field limiting ring 1.5 are both located inside the N+ cut-off ring 1.7. The spacing between the N+ cut-off ring 1.7 and the outermost P+ field limiting ring 1.5 needs to ensure the minimum width of limiting the terminal PN junction diffusion, which needs to be determined according to actual conditions. The N+ cut-off ring 1.7 can limit the magnitude of the breakdown current during reverse breakdown, thereby protecting the normal operation of the chip.

[0051] The manufacturing process of this embodiment is relatively simple, and can also achieve the purpose of increasing the terminal breakdown voltage, and also has the advantages of reducing the cell area, reducing the cost and improving the withstand voltage level.

[0052] Example 4 This embodiment is basically the same as the embodiment 3, the main difference is that the width of all the annular grooves in this embodiment is 1.5 μm, the number of the P+ field limiting rings 1.5 is 21, and the doping concentration of the P+ transition region 1.4 and the P+ field limiting ring 1.5 is 10 20 cm -3 That is, in this embodiment, a P+ transition region 1.4 and a P+ field limiting ring 1.5 with a higher doping concentration are used under the premise of using a smaller number of P+ field limiting rings 1.5.

[0053] Example 5 This embodiment provides a method for preparing a terminal structure of a trench silicon carbide power device, comprising the following steps: Step 1: If Figure 2 As shown, an N-Drift region 1.2 and an N-CSL layer 1.3 are sequentially arranged on the upper surface of a heavily doped N-type substrate 1.1.

[0054] Step 2: If Figure 3As shown, a P+ transition region 1.4 and a plurality of P+ field limiting rings 1.5 are respectively arranged on the N-CSL layer 1.3 by high-energy ion implantation, the doping concentrations of the P+ transition region 1.4 and the P+ field limiting rings 1.5 are the same, the P+ transition region 1.4 and the P+ field limiting rings 1.5 both penetrate the N-CSL layer 1.3 and contact the N-Drift region 1.2, and the P+ transition region 1.4 and the plurality of P+ field limiting rings 1.5 are arranged sequentially from the inside to the outside.

[0055] Step 3: If Figure 4 As shown, the N-CSL layer 1.3 between the P+ transition region 1.4 and the P+ field limiting ring 1.5 is completely etched, and the N-CSL layer 1.3 between each P+ field limiting ring 1.5 is completely etched, and annular grooves are formed between the P+ transition region 1.4 and the P+ field limiting ring 1.5 and between each P+ field limiting ring 1.5, and the annular grooves are filled with silicon dioxide 1.6.

[0056] Step 4: If Figure 5 As shown, an N+ cutoff ring 1.7 is added to the termination region of the P+ field limiting ring 1.5 by ion implantation, and then the ions are activated by annealing at a high temperature to complete the preparation and obtain the following Figure 6 The schematic diagram of the 1 / 4 cross section from the N+ cutoff ring 1.7 region to the P+ transition region 1.4 is shown.

[0057] In detail, the specific implementation of the preparation method described in this embodiment can refer to the implementation of the aforementioned terminal structure, and the repeated parts will not be repeated.

[0058] Example 6 This embodiment provides a method for preparing a terminal structure of a trench silicon carbide power device, comprising the following steps: Step 1: If Figure 2 As shown, an N-Drift region 1.2 and an N-CSL layer 1.3 are sequentially arranged on the upper surface of a heavily doped N-type substrate 1.1.

[0059] Step 2: A P+ ring is implanted on the N-CSL layer 1.3 through high energy ion implantation to penetrate the N-CSL layer 1.3 and contact the N-Drift region 1.2.

[0060] Step 3: If Figure 4 As shown, part of the P+ ring is etched to expose the N-Drift area 1.2, and a number of annular grooves are formed on the P+ ring. All the annular grooves are evenly distributed, and all the annular grooves are filled with silicon dioxide 1.6. The silicon dioxide 1.6 is used to separate the P+ ring into a P+ transition area 1.4 and a number of P+ field limiting rings 1.5.

[0061] Step 4: If Figure 5As shown, an N+ cutoff ring 1.7 is added to the termination region of the P+ field limiting ring 1.5 by ion implantation, and then the ions are activated by annealing at a high temperature to complete the preparation.

[0062] In detail, the specific implementation of the preparation method described in this embodiment can refer to the implementation of the aforementioned terminal structure, and the repeated parts will not be repeated, and the following is obtained: Figure 6 The schematic diagram of the 1 / 4 cross section from the N+ cutoff ring 1.7 region to the P+ transition region 1.4 is shown.

[0063] Experimental example This experimental example simulates the terminal structures of Examples 1-4, and the obtained simulation diagrams are as follows: Figure 7-10 As shown, Depend on Figure 7 It can be seen that the terminal structure of Example 1 can achieve a breakdown voltage of 1775V.

[0064] Depend on Figure 8 It can be seen that the terminal structure of Example 2 can achieve a breakdown voltage of 1896V.

[0065] Depend on Fig. 9 It can be seen that the terminal structure of Example 3 can achieve a breakdown voltage of 1943V.

[0066] Depend on Fig.10 It can be seen that the terminal structure of Example 4 can achieve a breakdown voltage of 1824V.

[0067] In summary, the present invention can effectively reduce the impact of positively charged N ions on the terminal structure through annular grooves of specific width and filled with silicon dioxide 1.6, and effectively optimize the surface electric field distribution, thereby improving the breakdown voltage as a whole. And from the above experimental results, it can be seen that when the present invention adopts the smallest annular groove width, the least number of P+ field limiting rings 1.5 and the lowest doping concentration, the breakdown voltage of the terminal structure is the lowest, and when the annular groove width is the largest, the number of P+ field limiting rings 1.5 and the highest doping concentration are adopted, the breakdown voltage of the terminal structure is the highest, and under the premise that any parameter remains unchanged, increasing other parameters can correspondingly increase the breakdown voltage.

[0068] The above description is only a specific implementation mode of the present invention. Any feature disclosed in this specification, unless otherwise stated, can be replaced by other alternative features that are equivalent or have similar purposes; all the disclosed features, or all the steps in the methods or processes, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. A terminal structure of a trench-type silicon carbide power device, comprising an N-type substrate (1.1), characterized in that: An N-Drift region (1.2) and an N-CSL layer (1.3) are sequentially arranged on the N-type substrate (1.1); a P+ transition region (1.4) and a plurality of P+ field limiting rings (1.5) are respectively arranged on the N-CSL layer (1.3) by high-energy ion implantation; the P+ transition region (1.4) and the P+ field limiting rings (1.5) both penetrate the N-CSL layer (1.3) and contact the N-Drift region (1.2); The field limiting rings (1.5) are arranged in sequence from the inside to the outside, and an annular groove is arranged between the P+ transition region (1.4) and the innermost P+ field limiting ring (1.5) and between each P+ field limiting ring (1.5), and the annular groove is formed by completely etching the N-CSL layer (1.3) between the P+ transition region (1.4) and the P+ field limiting ring (1.5) and completely etching the N-CSL layer (1.3) between each P+ field limiting ring (1.5), and the annular groove is completely filled with silicon dioxide (1.6).

2. The terminal structure of a trench silicon carbide power device according to claim 1, characterized in that: The P+ field limiting rings (1.5) are evenly arranged on the N-CSL layer (1.3), the number of the P+ field limiting rings (1.5) is 20-22, and the width of all the annular grooves is 1.5-2.5 μm.

3. A terminal structure of a trench silicon carbide power device according to claim 1 or 2, characterized in that: The doping concentrations of the P+ transition region (1.4) and the P+ field limiting ring (1.5) are both 10 19 -10 20 cm -3 Magnitude.

4. The terminal structure of a trench silicon carbide power device according to claim 1, characterized in that: The upper surface of the P+ transition region (1.4) and the upper surface of the P+ field limiting ring (1.5) are both on the same horizontal plane as the upper surface of the N-CSL layer (1.3), and the upper surface of the silicon dioxide (1.6) is on the same horizontal plane as the upper surface of the N-CSL layer (1.3), or the upper surface of the silicon dioxide (1.6) is higher than the upper surface of the N-CSL layer (1.3).

5. The terminal structure of a trench silicon carbide power device according to claim 1, characterized in that: The thickness of the N-CSL layer (1.3) is 1.5-2.2 μm, the width of the P+ transition region (1.4) is 40-200 μm, and the width of the P+ field limiting ring (1.5) is 1-3 μm.

6. The terminal structure of a trench silicon carbide power device according to claim 7, characterized in that: The N-Drift region (1.2) is formed by epitaxial doping, the N-CSL layer (1.3) is formed by secondary epitaxial doping or high-energy ion implantation, and the doping concentration of the N-CSL layer (1.3) is higher than the doping concentration of the N-Drift region (1.2).

7. The terminal structure of a trench silicon carbide power device according to claim 1, characterized in that: The doping concentration of the N-type substrate (1.1) is 10 19 -10 20 cm -3 The doping concentration of N-Drift region (1.2) is 10 14 -10 16 cm -3 The doping concentration of the N-CSL layer (1.3) is 10 15 -10 17 cm -3 Magnitude.

8. The terminal structure of a trench silicon carbide power device according to claim 1, characterized in that: An N+ cut-off ring (1.7) is formed around the upper surface of the N-CSL layer (1.3) by ion implantation, and the P+ transition region (1.4) and the P+ field limiting ring (1.5) are both located inside the N+ cut-off ring (1.7).

9. A method for preparing a terminal structure of a trench-type silicon carbide power device, characterized in that The following steps are involved: Step 1: sequentially disposing an N-Drift region (1.2) and an N-CSL layer (1.3) on the upper surface of a heavily doped N-type substrate (1.1); Step 2: a P+ transition region (1.4) and a plurality of P+ field limiting rings (1.5) are respectively arranged on the N-CSL layer (1.3) by high-energy ion implantation. The doping concentrations of the P+ transition region (1.4) and the P+ field limiting rings (1.5) are the same. The P+ transition region (1.4) and the P+ field limiting rings (1.5) both penetrate the N-CSL layer (1.3) and contact the N-Drift region (1.2). The P+ transition region (1.4) and the plurality of P+ field limiting rings (1.5) are arranged in sequence from the inside to the outside. Step 3: completely etching the N-CSL layer (1.3) between the P+ transition region (1.4) and the P+ field limiting ring (1.5) and completely etching the N-CSL layer (1.3) between each P+ field limiting ring (1.5), forming annular grooves between the P+ transition region (1.4) and the P+ field limiting ring (1.5) and between each P+ field limiting ring (1.5), and filling all the annular grooves with silicon dioxide (1.6); Step 4: Add an N+ cutoff ring (1.7) to the termination area of ​​the P+ field limiting ring (1.5) through ion implantation, and then anneal at high temperature to activate the ions to complete the preparation.

10. A method for preparing a terminal structure of a trench-type silicon carbide power device, characterized in that The following steps are involved: Step 1: sequentially disposing an N-Drift region (1.2) and an N-CSL layer (1.3) on the upper surface of a heavily doped N-type substrate (1.1); Step 2: Aluminum ions are implanted on the N-CSL layer (1.3) to form a P+ ring that penetrates the N-CSL layer (1.3) and contacts the N-Drift region (1.2); Step 3: Etch part of the P+ ring until the N-Drift area (1.2) is exposed, and form a number of annular grooves on the P+ ring. All the annular grooves are evenly distributed, and all the annular grooves are filled with silicon dioxide (1.6). The P+ ring is separated into a P+ transition area (1.4) and a number of P+ field limiting rings (1.5) by using silicon dioxide (1.6); Step 4: Add an N+ cutoff ring (1.7) to the termination area of ​​the P+ field limiting ring (1.5) through ion implantation, and then activate the ions by high-temperature annealing to complete the preparation.

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