Semiconductor structure and semiconductor device

Abstract

The invention provides a semiconductor structure and a semiconductor device. The semiconductor structure comprises a substrate; the epitaxial layer is located on the surface of the substrate; the first doped region is located in the epitaxial layer, the surface, away from the substrate, of the first doped region is the partial surface, away from the substrate, of the epitaxial layer, and the doping type of the first doped region is different from that of the epitaxial layer; the at least two second doped regions are located in the epitaxial layer and located on the two sides of the first doped region in the preset direction respectively, the surfaces, away from the substrate, of the two second doped regions are part of the surface, away from the substrate, of the epitaxial layer, and the doping type of the second doped regions is different from that of the first doped region; and the at least one channel region is located in the epitaxial layer and at least located on the surfaces, close to the substrate, of the two second doped regions, and the doping type of the channel region is the same as that of the first doped region. The problem that in the prior art, due to the fact that the transverse size of a silicon carbide MOSFET device cell is large, the size of a chip is large is solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a semiconductor device. Background Art

[0002] Traditional planar SiC MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices have lateral channels and relatively large lateral dimensions of the cells. Recessed-gate SiC MOSFETs have vertically designed channels, which saves lateral channel dimensions and is currently the main technical route for increasing channel density.

[0003] Limited by the characteristic size and overlay accuracy of semiconductor process equipment, the existing planar gate SiC MOSFET and recessed gate SiC MOSFET have limited effects on reducing the lateral size of cells. Summary of the invention

[0004] The main purpose of the present application is to provide a semiconductor structure and a semiconductor device to solve the problem in the prior art that the lateral size of the silicon carbide MOSFET device cell is large, resulting in a large chip size.

[0005] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a semiconductor structure is provided, including: a substrate; an epitaxial layer, located on the surface of the substrate; a first doped region, located in the epitaxial layer, the surface of the first doped region away from the substrate is the partial surface of the epitaxial layer away from the substrate, and the doping type of the first doped region is different from the doping type of the epitaxial layer; at least two second doped regions, located in the epitaxial layer, and respectively located on both sides of the first doped region in a predetermined direction, the surfaces of the two second doped regions away from the substrate are the partial surface of the epitaxial layer away from the substrate, the doping type of the second doped region is different from the doping type of the first doped region, and the predetermined direction is perpendicular to the thickness direction of the substrate; at least one channel region, located in the epitaxial layer, and at least located on the surfaces of the two second doped regions close to the substrate, and the doping type of the channel region is the same as the doping type of the first doped region.

[0006] Optionally, there are two channel regions, the two channel regions are respectively located at two sides of the first doping region in the predetermined direction, and the channel regions are located one-to-one on the surface of the second doping region close to the substrate.

[0007] Optionally, there is one channel region, and the channel region is located on surfaces of the two second doping regions close to the substrate and on a surface of the first doping region close to the substrate.

[0008] Optionally, the semiconductor structure also includes: at least two gate structures, which are respectively located on both sides of the first doped region in the predetermined direction, and are located on a portion of the surface of the second doped region away from the substrate, on the sidewall of the second doped region, on the sidewall of the channel region, on a portion of the surface of the epitaxial layer away from the substrate, and on a portion of the sidewall of the epitaxial layer.

[0009] Optionally, the epitaxial layer includes: a first sub-epitaxial layer, located on the surface of the substrate; a second sub-epitaxial layer, located on a partial surface of the first sub-epitaxial layer away from the substrate, in the predetermined direction, the length of the first sub-epitaxial layer is greater than the length of the second sub-epitaxial layer, the first doping region, the second doping region and the channel region are all located in the second sub-epitaxial layer, the sidewall of the second doping region is a partial sidewall of the second sub-epitaxial layer, the sidewall of the channel region is a partial sidewall of the second sub-epitaxial layer, the surface of the first doping region away from the substrate is the partial surface of the second sub-epitaxial layer away from the substrate, the surface of the second doping region away from the substrate is the partial surface of the second sub-epitaxial layer away from the substrate, and the two gate structures are located on the partial surface of the second doping region away from the substrate, on the sidewall of the second sub-epitaxial layer and on the partial surface of the first sub-epitaxial layer away from the substrate.

[0010] Optionally, the semiconductor structure also includes: at least one third doping region, located in the epitaxial layer and at least located on the side of the channel region close to the substrate, the doping type of the third doping region is the same as the doping type of the first doping region, the doping concentration of the third doping region is less than the doping concentration of the first doping region, and the doping concentration of the third doping region is greater than the doping concentration of the channel region.

[0011] Optionally, there is one third doping region. When there are two channel regions, the third doping region is located on the surface of the first doping region close to the substrate. When there is only one channel region, the third doping region is located on a partial surface of the channel region close to the substrate.

[0012] Optionally, there are two third doping regions, and they are located at least on a portion of the surface of the gate structure close to the substrate.

[0013] Optionally, the gate structure includes: a gate oxide layer, located on a portion of the surface of the second doped region away from the substrate, on the side walls of the second doped region, on the side walls of the channel region, on a portion of the surface of the epitaxial layer away from the substrate, and on a portion of the side walls of the epitaxial layer; a gate, located on a surface of the gate oxide layer away from the substrate and on the side walls of the gate oxide layer.

[0014] Optionally, the semiconductor structure further includes: a first metal layer located on a surface of the first doped region away from the substrate and on a partial surface of the second doped region away from the substrate; and a second metal layer located on a surface of the substrate away from the epitaxial layer.

[0015] According to another aspect of the present application, a semiconductor device is provided, comprising any one of the semiconductor structures described above.

[0016] According to the technical solution of the present application, the semiconductor structure includes a substrate, an epitaxial layer located on the surface of the substrate, a first doped region located in the epitaxial layer, at least two second doped regions and at least one first channel region, wherein the first doped region has a different doping type from the epitaxial layer, the two second doped regions are respectively located on both sides of the first doped region in a predetermined direction, the doping type of the second doped region is different from the doping type of the first doped region, the channel region is at least located on the surface of the two second doped regions close to the substrate, and the doping type of the channel region is the same as the doping type of the first doped region. Compared with the problem of large chip size caused by large lateral size of silicon carbide MOSFET device cell in the prior art, the first doped region of the present application is located between the two second doped regions, and the channel region is at least located on the surface of the two second doped regions close to the substrate, that is, not only the channel region is vertically arranged, but also the other lateral structures of the cell (second doped region, first doped region, JFET region) are also designed as vertical structures, realizing the superposition of multiple regions in the vertical direction, ensuring that the lateral size of the cell is small, thereby ensuring the small size of the chip, ensuring high chip area utilization efficiency, and thus ensuring high power density of silicon carbide devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings constituting part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0018] Figure 1 A schematic cross-sectional structure diagram of a semiconductor structure provided according to an embodiment of the present application is shown;

[0019] Figure 2 A schematic cross-sectional structure diagram of another semiconductor structure provided according to an embodiment of the present application is shown;

[0020] Figure 3 A schematic cross-sectional structure diagram of another semiconductor structure provided according to an embodiment of the present application is shown;

[0021] Figure 4 A schematic cross-sectional structure diagram of yet another semiconductor structure provided according to an embodiment of the present application is shown.

[0022] The above drawings include the following reference numerals:

[0023] 10. Substrate; 11. Epitaxial layer; 12. First doped region; 13. Second doped region; 14. Channel region; 15. Gate structure; 111. First sub-epitaxial layer; 112. Second sub-epitaxial layer; 16. Third doped region; 151. Gate oxide layer; 152. Gate; 17. First metal layer; 18. Second metal layer. DETAILED DESCRIPTION

[0024] It should be noted that the following detailed descriptions are illustrative and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present application belongs.

[0025] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0026] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be intermediate elements. Moreover, in the specification and claims, when it is described that an element is "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element through a third element.

[0027] As introduced in the background technology, in the prior art, the lateral dimensions of the silicon carbide MOSFET device cell are relatively large, resulting in a relatively large chip size. To solve the above problem, an embodiment of the present application provides a semiconductor structure and a semiconductor device.

[0028] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0029] In this embodiment, a semiconductor structure is provided, such as Figures 1 to 4 As shown, including:

[0030] Substrate 10;

[0031] An epitaxial layer 11 is located on the surface of the substrate 10;

[0032] a first doping region 12 located in the epitaxial layer 11, wherein a surface of the first doping region 12 away from the substrate 10 is a surface of the epitaxial layer 11 away from the substrate 10, and a doping type of the first doping region 12 is different from a doping type of the epitaxial layer 11;

[0033] at least two second doping regions 13, located in the epitaxial layer 11, and respectively located on both sides of the first doping region 12 in a predetermined direction, the surfaces of the two second doping regions 13 away from the substrate 10 are partial surfaces of the epitaxial layer 11 away from the substrate 10, the doping type of the second doping regions 13 is different from the doping type of the first doping regions 12, and the predetermined direction is perpendicular to the thickness direction of the substrate 10;

[0034] At least one channel region 14 is located in the epitaxial layer 11 and at least located on the surface of the two second doping regions 13 close to the substrate 10 . The doping type of the channel region 14 is the same as the doping type of the first doping region 12 .

[0035] Through the above embodiments, the semiconductor structure includes a substrate, an epitaxial layer located on the surface of the substrate, a first doped region located in the epitaxial layer, at least two second doped regions and at least one first channel region, wherein the first doped region has a different doping type from the epitaxial layer, the two second doped regions are respectively located on both sides of the first doped region in a predetermined direction, the doping type of the second doped region is different from the doping type of the first doped region, the channel region is at least located on the surface of the two second doped regions close to the substrate, and the doping type of the channel region is the same as the doping type of the first doped region. Compared with the problem of large chip size caused by large lateral size of silicon carbide MOSFET device cells in the prior art, the first doped region of the present application is located between the two second doped regions, and the channel region is at least located on the surface of the two second doped regions close to the substrate, that is, not only the channel region is vertically arranged, but also other lateral structures of the cell (second doped region, first doped region, JFET region) are also designed as vertical structures, realizing the superposition of multiple regions in the vertical direction, ensuring that the lateral size of the cell is small, thereby ensuring the small size of the chip, ensuring high chip area utilization efficiency, and thus ensuring high power density of silicon carbide devices.

[0036] Specifically, the second doping region is located in the epitaxial layer and surrounds the first doping region in a predetermined direction.

[0037] Specifically, the doping concentration of the above-mentioned substrate is generally heavily doped, the doping type of the above-mentioned substrate is the same as the doping type of the above-mentioned epitaxial layer, and the doping concentration of the above-mentioned substrate is greater than the doping concentration of the above-mentioned epitaxial layer. In the embodiment of the present application, the doping type of the above-mentioned substrate is N-type, and the doping type of the above-mentioned epitaxial layer is N-type. The material of the above-mentioned substrate includes but is not limited to silicon carbide and diamond. The above-mentioned substrate has a supporting function and has the characteristics of low on-resistance and low contact resistance. The doping concentration of the above-mentioned substrate is 1E19cm -3 -1E20cm -3 The doping concentration of the above epitaxial layer is 1E15cm -3 -1E16cm -3 .

[0038] Specifically, the first doping region may be formed by ion implantation technology. The doping concentration of the first doping region is 1E18 cm -3 -1E21cm -3 In the embodiment of the present application, the doping type of the first doping region is P type, and the doping particles of the first doping region include but are not limited to Al and B.

[0039] Specifically, the second doping region may be formed by ion implantation technology. The doping concentration of the second doping region is 1E18 cm -3 -1E21cm -3 The doping concentration of the second doping region is greater than the doping concentration of the epitaxial layer. In the embodiment of the present application, the doping type of the second doping region is N type, and the doping particles of the second doping region include but are not limited to N and P.

[0040] Specifically, the channel region may be formed by ion implantation technology. The doping concentration of the channel region is 1E17 cm -3 -1E21cm -3 The doping concentration of the channel region is less than the doping concentration of the first doping region. In the embodiment of the present application, the doping type of the channel region is P type, and the doping particles of the channel region include but are not limited to Al and B.

[0041] In an exemplary embodiment, Figure 1 and Figure 2As shown, there are two channel regions 14, and the two channel regions 14 are respectively located on both sides of the first doping region 12 in the predetermined direction, and the channel regions 14 are correspondingly located on the surface of the second doping region 13 close to the substrate 10. In this embodiment, there are two channel regions, and they are respectively located on both sides of the first doping region in the predetermined direction. The corresponding layout of the channel region and the second doping region helps to form a more uniform electric field distribution, and enables the channel region and the second doping region to be superimposed in the vertical direction, thereby further reducing the lateral size of the cell while maintaining the device performance, and further ensuring a high degree of integration of the device.

[0042] In other embodiments, Figure 3 and Figure 4 As shown, there is one channel region 14, which is located on the surfaces of the two second doping regions 13 close to the substrate 10 and on the surface of the first doping region 12 close to the substrate 10. In this embodiment, there is one channel region, which is located on the surfaces of the two second doping regions close to the substrate and on the surface of the first doping region close to the substrate. The first doping region, the second doping region and the channel region are designed as a superimposed structure, and multiple regions can be further superimposed in the vertical direction to further reduce the cell size.

[0043] In some other exemplary embodiments, Figures 1 to 4 As shown, the semiconductor structure further includes: at least two gate structures 15, which are respectively located on both sides of the first doping region 12 in the predetermined direction, and are located on the partial surface of the second doping region 13 away from the substrate 10, on the sidewall of the second doping region 13, on the sidewall of the channel region 14, on the partial surface of the epitaxial layer away from the substrate, and on the partial sidewall of the epitaxial layer. In this embodiment, the gate structure is located on the sidewall of the second doping region and the partial surface away from the substrate, as well as the corresponding positions of the channel region and the epitaxial layer. Such a layout can enhance the control capability of the channel current and improve the switching speed and efficiency of the device. In addition, the gate structure is respectively located on both sides of the first doping region in the predetermined direction. Such a design can make the layout of the device more compact and further improve the integration of the device.

[0044] Some options include Figures 1 to 4As shown, the epitaxial layer 11 includes: a first sub-epitaxial layer 111, which is located on the surface of the substrate 10; a second sub-epitaxial layer 112, which is located on a portion of the surface of the first sub-epitaxial layer 111 away from the substrate 10. In the predetermined direction, the length of the first sub-epitaxial layer 111 is greater than the length of the second sub-epitaxial layer 112. The first doped region 12, the second doped region 13 and the channel region 14 are all located in the second sub-epitaxial layer 112. The sidewall of the second doped region 13 is a portion of the sidewall of the second sub-epitaxial layer 112. The sidewall of the channel region 14 is The sidewall is a partial sidewall of the second sub-epitaxial layer 112, the surface of the first doping region 12 away from the substrate 10 is a partial surface of the second sub-epitaxial layer 112 away from the substrate 10, the surface of the second doping region 13 away from the substrate 10 is a partial surface of the second sub-epitaxial layer 112 away from the substrate 10, and the two gate structures 15 are located on the partial surface of the second doping region 13 away from the substrate 10, on the sidewall of the second sub-epitaxial layer 112, and on the partial surface of the first sub-epitaxial layer 111 away from the substrate 10. In this embodiment, by designing the first doping region, the second doping region and the channel region in the second sub-epitaxial layer, a more compact device structure can be achieved, thereby further improving the integration of the device.

[0045] In other embodiments, Figures 1 to 4 As shown, the thickness of the first sub-epitaxial layer 111 is greater than the thickness of the second sub-epitaxial layer 112. In this embodiment, the greater thickness of the first sub-epitaxial layer helps to disperse heat and reduce heat accumulation of the device during high-power operation, thereby further improving the thermal stability of the device.

[0046] Some other options, such as Figures 1 to 4 As shown, the semiconductor structure further includes: at least one third doping region 16, which is located in the epitaxial layer 11 and at least located on the side of the channel region 14 close to the substrate 10. The doping type of the third doping region 16 is the same as the doping type of the first doping region 12. The doping concentration of the third doping region 16 is less than the doping concentration of the first doping region 12. The doping concentration of the third doping region 16 is greater than the doping concentration of the channel region 14. In this embodiment, the third doping region is used to form a JFET structure. The JFET can adjust the electric field inside the device, control the current, and help to improve the switching speed of the device and adjust the on-resistance. In addition, the doping concentration gradient design of the third doping region helps to improve the electrical characteristics of the device.

[0047] Specifically, the third doping region may be formed by ion implantation technology. The doping concentration of the third doping region is 1E18 cm -3 -1E21cm -3In the embodiment of the present application, the doping type of the third doping region is P type, and the doping particles of the channel region include but are not limited to Al and B.

[0048] In some other options, such as Figure 1 and Figure 4 As shown, the third doping region 16 has a Figure 1 As shown, in the case where there are two channel regions 14, the third doping region 16 is located on the surface of the first doping region 12 close to the substrate 10, as shown in FIG. Figure 4 As shown, in the case where there is only one channel region 14, the third doping region 16 is located on a surface of the channel region 14 close to the substrate 10. In this embodiment, by arranging the third doping region on the surface of the first doping region or the channel region close to the substrate, the electrical characteristics of the doping region can be more effectively controlled, thereby further optimizing the performance of the device.

[0049] In the above embodiment, the third doped region is located in the first sub-epitaxial layer and the second sub-epitaxial layer.

[0050] In other embodiments, Figure 2 and Figure 3 As shown, there are two third doped regions 16, and they are at least located on a portion of the surface of the gate structure 15 close to the substrate 10. In this embodiment, by providing the third doped region on a portion of the surface of the gate structure close to the substrate, the functional area of ​​the device can be further increased without increasing the lateral size of the device, which further helps to improve the integration of the semiconductor device.

[0051] In the above embodiment, the two third doping regions are located in the first sub-epitaxial layer.

[0052] In an exemplary embodiment, Figures 1 to 4 As shown, the gate structure 15 includes: a gate oxide layer 151, which is located on the surface of the second doping region 13 away from the substrate 10, on the sidewall of the second doping region 13, on the sidewall of the channel region 14, on the surface of the epitaxial layer 11 away from the substrate 10, and on part of the sidewall of the epitaxial layer 11; a gate 152, which is located on the surface of the gate oxide layer 151 away from the substrate 10 and on the sidewall of the gate oxide layer 151. In this embodiment, the gate oxide layer serves as an insulating layer between the gate and the semiconductor, which can effectively isolate the gate and the semiconductor, prevent current leakage, and further improve the stability and reliability of the device; the gate can control the conductivity of the channel region, and the change of the gate voltage can cause the change of the number of carriers (electrons or holes) in the channel region, thereby controlling the switching state of the device.

[0053] Specifically, the gate oxide layer may be formed by thermal oxidation, PECVD (Plasma Enhanced Chemical Vapor Deposition), ALD (Atomic Layer Deposition), etc. The material of the gate oxide layer includes but is not limited to silicon oxide (SiO2), hafnium oxide (HfO2), aluminum oxide (Al2O3) and aluminum nitride (AlN). The thickness of the gate oxide layer is 10nm-1000nm.

[0054] Specifically, the material of the gate includes but is not limited to polysilicon and silicon carbide, the dopant of the gate includes but is not limited to P, N and B, and the doping concentration of the gate is 1E18cm -3 -1E20cm -3 The above-mentioned gate has the characteristics of high temperature resistance and low resistance.

[0055] In an exemplary embodiment, Figures 1 to 4 As shown, the semiconductor structure further includes: a first metal layer 17, located on the surface of the first doping region 12 away from the substrate 10 and on a portion of the surface of the second doping region 13 away from the substrate 10; and a second metal layer 18, located on the surface of the substrate 10 away from the epitaxial layer 11. In this embodiment, the first metal layer is used as a source electrode and the second metal layer is used as a drain electrode, which can provide good electrical conductivity, facilitate the transmission and collection of current, and improve the conductive performance of the device.

[0056] Specifically, the first metal layer is deposited on the front side of the device, and can be deposited by evaporation, sputtering, etc. The material of the first metal layer includes but is not limited to Ti, Al, Ni and Au. The first metal layer can short-circuit the first doped region and the second doped region.

[0057] Specifically, the second metal layer is deposited on the back of the device, and can be deposited by evaporation, sputtering, etc. The material of the second metal layer includes but is not limited to Ti, Al, Ni and Au.

[0058] Specifically, in the semiconductor structure provided by the embodiment of the present application, since the second doping region, the channel region, the JFET region, etc. are the same injection window, the number of related photomasks can be effectively saved, and the doping of the specified area can be achieved by modifying the injection conditions and annealing conditions. The semiconductor structure provided by the embodiment of the present application can save chip area and improve channel density: the semiconductor structure not only changes the traditional lateral dimensions (including the N+ region (i.e., the second doping region), the channel region, and the JFET region) to vertical superposition, shortening the lateral dimensions, but also the remaining lateral dimensions including P+ (i.e., the first doping region), gate oxide (gate oxide layer), polysilicon (gate), etc. can also be reduced based on the minimum process capability.

[0059] The present application also provides a method for preparing a semiconductor structure, comprising the following steps:

[0060] Step S101: providing a substrate;

[0061] Step S102: forming an epitaxial layer on the surface of the substrate;

[0062] Step S103: forming a first doped region in the epitaxial layer, wherein a surface of the first doped region away from the substrate is a surface of the epitaxial layer away from the substrate, and a doping type of the first doped region is different from a doping type of the epitaxial layer;

[0063] Step S104: forming at least two second doping regions in the epitaxial layer, the two second doping regions being respectively located on both sides of the first doping region in a predetermined direction, the surfaces of the two second doping regions away from the substrate being the partial surfaces of the epitaxial layer away from the substrate, the doping type of the second doping regions being different from the doping type of the first doping regions, and the predetermined direction being perpendicular to the thickness direction of the substrate;

[0064] Step S105: forming at least one channel region in the epitaxial layer, wherein the channel region is at least located on the surface of the two second doping regions close to the substrate, and the doping type of the channel region is the same as the doping type of the first doping region.

[0065] In other embodiments, at least one channel region is formed in the epitaxial layer, including: forming two channel regions in the epitaxial layer, the two channel regions are respectively located on both sides of the first doping region in the predetermined direction, and the channel regions are located one by one on the surface of the second doping region close to the substrate.

[0066] Specifically, a substrate is first provided; then an epitaxial layer is formed on the surface of the substrate; then a first doping region is obtained by opening a hole through a first mask and ion implantation is performed; then two channel regions are obtained by opening a hole through a second mask and ion implantation is performed, and the two channel regions are respectively located on both sides of the first doping region in a predetermined direction; then the second mask is reused and ion implantation is performed to obtain two second doping regions, and the second doping regions are located one by one on the surface of the channel region away from the substrate. Among them, the channel region and the second doping region reuse the same mask (i.e., the same implantation window), which can effectively save the number of related photomasks, and the doping of the designated area can be achieved by modifying the implantation conditions and annealing conditions.

[0067] An embodiment of the present application also provides a semiconductor device, comprising: any one of the above-mentioned semiconductor structures.

[0068] In the above embodiment, the semiconductor device includes a semiconductor structure, wherein the semiconductor structure includes a substrate, an epitaxial layer located on the surface of the substrate, a first doped region located in the epitaxial layer, at least two second doped regions, and at least one first channel region, wherein the first doped region has a different doping type from the epitaxial layer, the two second doped regions are respectively located on both sides of the first doped region in a predetermined direction, the doping type of the second doped region is different from the doping type of the first doped region, the channel region is at least located on the surface of the two second doped regions close to the substrate, and the doping type of the channel region is the same as the doping type of the first doped region. Compared with the problem of large chip size caused by large lateral size of the silicon carbide MOSFET device cell in the prior art, the first doped region of the present application is located between the two second doped regions, and the channel region is at least located on the surface of the two second doped regions close to the substrate, that is, not only the channel region is vertically arranged, but also other lateral structures of the cell (second doped region, first doped region, JFET region) are also designed as vertical structures, realizing the superposition of multiple regions in the vertical direction, ensuring that the lateral size of the cell is small, thereby ensuring the small size of the chip, ensuring high chip area utilization efficiency, and thus ensuring high power density of silicon carbide devices.

[0069] Specifically, in an embodiment of the present application, the above-mentioned semiconductor device is a silicon carbide MOSFET device.

[0070] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0071] 1) In the semiconductor structure of the present application, the semiconductor structure includes a substrate, an epitaxial layer located on the surface of the substrate, a first doped region located in the epitaxial layer, at least two second doped regions and at least one first channel region, wherein the first doped region has a different doping type from the epitaxial layer, the two second doped regions are located on both sides of the first doped region in a predetermined direction, the doping type of the second doped region is different from the doping type of the first doped region, the channel region is at least located on the surface of the two second doped regions close to the substrate, and the doping type of the channel region is the same as the doping type of the first doped region. Compared with the problem of large chip size caused by large lateral size of silicon carbide MOSFET device cells in the prior art, the first doped region of the present application is located between the two second doped regions, and the channel region is at least located on the surface of the two second doped regions close to the substrate, that is, not only the channel region is vertically arranged, but also the other lateral structures of the cell (second doped region, first doped region, JFET region) are also designed as vertical structures, realizing the superposition of multiple regions in the vertical direction, ensuring that the lateral size of the cell is small, thereby ensuring the small size of the chip, ensuring high chip area utilization efficiency, and thus ensuring high power density of silicon carbide devices.

[0072] 2) In the semiconductor device of the present application, the semiconductor device includes a semiconductor structure, wherein the semiconductor structure includes a substrate, an epitaxial layer located on the surface of the substrate, a first doped region located in the epitaxial layer, at least two second doped regions and at least one first channel region, wherein the first doped region has a different doping type from the epitaxial layer, the two second doped regions are located on both sides of the first doped region in a predetermined direction, the doping type of the second doped region is different from the doping type of the first doped region, the channel region is at least located on the surface of the two second doped regions close to the substrate, and the doping type of the channel region is the same as the doping type of the first doped region. Compared with the problem of large chip size caused by large lateral dimensions of the silicon carbide MOSFET device cell in the prior art, the first doped region of the present application is located between the two second doped regions, and the channel region is at least located on the surface of the two second doped regions close to the substrate, that is, not only the channel region is vertically arranged, but also the other lateral structures of the cell (second doped region, first doped region, JFET region) are also designed as vertical structures, realizing the superposition of multiple regions in the vertical direction, ensuring that the lateral dimensions of the cell are small, thereby ensuring the small size of the chip, ensuring high chip area utilization efficiency, and thus ensuring high power density of silicon carbide devices.

[0073] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor structure, characterized in that: include: substrate; an epitaxial layer located on the surface of the substrate; A first doping region is located in the epitaxial layer, a surface of the first doping region away from the substrate is a portion of the surface of the epitaxial layer away from the substrate, and a doping type of the first doping region is different from a doping type of the epitaxial layer; at least two second doping regions, located in the epitaxial layer and respectively located on both sides of the first doping region in a predetermined direction, surfaces of the two second doping regions away from the substrate are partial surfaces of the epitaxial layer away from the substrate, the doping type of the second doping regions is different from the doping type of the first doping regions, and the predetermined direction is perpendicular to the thickness direction of the substrate; At least one channel region is located in the epitaxial layer and is located on the surface of at least two of the second doping regions close to the substrate, and the doping type of the channel region is the same as the doping type of the first doping region.

2. The semiconductor structure according to claim 1, characterized in that: There are two channel regions, which are respectively located at two sides of the first doping region in the predetermined direction, and the channel regions are located one-to-one on the surface of the second doping region close to the substrate.

3. The semiconductor structure according to claim 1, characterized in that: There is one channel region, which is located on surfaces of the two second doping regions close to the substrate and on a surface of the first doping region close to the substrate.

4. The semiconductor structure according to claim 2 or 3, characterized in that: The semiconductor structure further comprises: At least two gate structures are respectively located on both sides of the first doped region in the predetermined direction, and are located on a portion of the surface of the second doped region away from the substrate, on the sidewall of the second doped region, on the sidewall of the channel region, on a portion of the surface of the epitaxial layer away from the substrate, and on a portion of the sidewall of the epitaxial layer.

5. The semiconductor structure according to claim 4, characterized in that: The epitaxial layer comprises: A first sub-epitaxial layer, located on the surface of the substrate; The second sub-epitaxial layer is located on a partial surface of the first sub-epitaxial layer away from the substrate. In the predetermined direction, the length of the first sub-epitaxial layer is greater than the length of the second sub-epitaxial layer. The first doped region, the second doped region and the channel region are all located in the second sub-epitaxial layer. The sidewall of the second doped region is a partial sidewall of the second sub-epitaxial layer, and the sidewall of the channel region is a partial sidewall of the second sub-epitaxial layer. The surface of the first doped region away from the substrate is the partial surface of the second sub-epitaxial layer away from the substrate, and the surface of the second doped region away from the substrate is the partial surface of the second sub-epitaxial layer away from the substrate. The two gate structures are located on the partial surface of the second doped region away from the substrate, on the sidewall of the second sub-epitaxial layer, and on the partial surface of the first sub-epitaxial layer away from the substrate.

6. The semiconductor structure according to claim 4, characterized in that: The semiconductor structure further comprises: At least one third doping region is located in the epitaxial layer and at least on a side of the channel region close to the substrate, the doping type of the third doping region is the same as the doping type of the first doping region, the doping concentration of the third doping region is less than the doping concentration of the first doping region, and the doping concentration of the third doping region is greater than the doping concentration of the channel region.

7. The semiconductor structure according to claim 6, characterized in that: There is one third doping region. When there are two channel regions, the third doping region is located on the surface of the first doping region close to the substrate. When there is only one channel region, the third doping region is located on the partial surface of the channel region close to the substrate.

8. The semiconductor structure according to claim 6, characterized in that: There are two third doping regions, and the third doping regions are at least located on a portion of the surface of the gate structure close to the substrate.

9. The semiconductor structure according to claim 4, characterized in that: The gate structure comprises: a gate oxide layer, located on a portion of the surface of the second doped region away from the substrate, on a sidewall of the second doped region, on a sidewall of the channel region, on a portion of the surface of the epitaxial layer away from the substrate, and on a portion of the sidewall of the epitaxial layer; The gate is located on a surface of the gate oxide layer away from the substrate and on a side wall of the gate oxide layer.

10. The semiconductor structure according to claim 1, characterized in that The semiconductor structure further comprises: A first metal layer is located on a surface of the first doping region away from the substrate and a portion of a surface of the second doping region away from the substrate; The second metal layer is located on a surface of the substrate away from the epitaxial layer.

11. A semiconductor device, characterized in that: A semiconductor structure comprising any one of claims 1 to 10.

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