A 3C-SiC composite epitaxial structure and device structure based on 4H-SiC

Abstract

The present invention provides a 3C-SiC composite epitaxial structure and a device structure based on 4H-SiC. The composite epitaxial structure includes: a 4H-SiC substrate, an N-type doped epitaxial layer, a P-type doped buried layer, a carrier tunneling region, and a 3C-SiC epitaxial layer. The N-type doped epitaxial layer is disposed on the 4H-SiC substrate. The 3C-SiC epitaxial layer is epitaxially grown secondarily or bonded to the surface of the N-type doped epitaxial layer. A carrier tunneling region is formed at the contact interface layer between the 3C-SiC epitaxial layer and the N-type doped epitaxial layer. The P-type doped buried layer is ion-implanted into the upper region of the N-type doped epitaxial layer. This structure can effectively solve the problems in the prior art that when using 4H-SiC as a substrate to prepare SiC-MOS devices, the improvement of the interface state density and the channel electron mobility is limited, the on-state ability of the device is poor, and the electrical performance and long-term reliability are not good, and provides a composite epitaxial structure and a device structure with strong on-state ability, good electrical performance and long-term reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly to a 3C-SiC composite epitaxial structure and a device structure based on 4H-SiC. Background Art

[0002] In the actual design, fabrication, and application of power devices, wide-bandgap semiconductor materials such as GaN, SiC, and Ga2O3 can provide much higher breakdown voltage per unit thickness than silicon. However, there are various problems in the basic structure and fabrication process of power devices, and many special or high-temperature process equipment is also required.

[0003] For example, SiC MOSFET devices have always had problems related to gate oxide interface states and various reliability issues. SiC materials have many crystal forms, such as 3C-SiC, 4H-SiC, and 6H-SiC. Among them, 4H-SiC is the main SiC crystal form used in the preparation of SiC devices due to its wide bandgap width and high critical breakdown field strength. However, there are some problems that need to be solved urgently in SiC-MOS devices prepared with 4H-SiC:

[0004] 1. The existing techniques for optimizing the interface quality of gate oxides in 4H-SiC MOSFETs are still limited in improving the interface state density and channel electron mobility.

[0005] 2. After 3C-SiC and 4H-SiC are heteroepitaxially grown or bonded together, electron potential wells and barriers will be formed at the interface, resulting in difficulty for electrons to flow between 3C-SiC and 4H-SiC, and the conduction ability of the device is very poor.

[0006] 3. The existing technical solutions have limited protection effects on the gate trench bottom and corner oxides. Especially under extreme electrical stress conditions such as avalanche breakdown or short circuit, the gate dielectric layer is extremely prone to damage.

[0007] 4. Due to the extremely low diffusion coefficient of impurity elements in SiC materials, doping of SiC materials can only form PN shallow junctions through high-temperature ion implantation, and it is difficult to achieve deep junction implantation and high-temperature push junction of P-type doping like Si. Moreover, increasing the ion implantation energy blindly will damage the lattice structure of SiC, affecting the electrical performance and long-term reliability of the device.

[0008] 5. The heteroepitaxial and bonding technologies of 3C-SiC and 4H-SiC; the heteroepitaxial technologies of Ga2O3 and 3C-SiC and Ga2O3 and 4H-SiC are not yet mature, and there are a large number of lattice defects at the heteroepitaxial / bonding interface. When the device is in the blocking state, these interface layer defects generate electron-hole pairs under the action of a strong electric field, resulting in an increase in the leakage current of the device.

[0009] Based on this, the present invention provides a new 3C-SiC composite epitaxial structure and device structure based on 4H-SiC. Summary of the Invention

[0010] Based on the above description, the present invention provides a 3C-SiC composite epitaxial structure and device structure based on 4H-SiC to solve the problems in the prior art that when using 4H-SiC as a substrate to prepare SiC-MOS devices, the improvement of the interface state density and the channel electron mobility is limited, the on-state ability of the device is poor, and the electrical performance and long-term reliability are not good.

[0011] The technical solution of the present invention to solve the above technical problems is as follows:

[0012] In a first aspect, the present invention provides a 3C-SiC composite epitaxial structure based on 4H-SiC, including: a 4H-SiC substrate, an N-type doped epitaxial layer, a P-type doped buried layer, a carrier tunneling region, and a 3C-SiC epitaxial layer;

[0013] The N-type doped epitaxial layer is disposed on the 4H-SiC substrate;

[0014] The 3C-SiC epitaxial layer is epitaxially grown or bonded for the second time on the surface of the N-type doped epitaxial layer;

[0015] The carrier tunneling region is formed at the contact interface layer between the 3C-SiC epitaxial layer and the N-type doped epitaxial layer;

[0016] The P-type doped buried layer is ion-implanted into the upper region of the N-type doped epitaxial layer.

[0017] On the basis of the above technical solution, the present invention can also be improved as follows.

[0018] Further, the 4H-SiC substrate is an N-type doped 4H-SiC layer; the 3C-SiC epitaxial layer is an N-type doped 3C-SiC layer.

[0019] Further, the N-type doped epitaxial layer is an N-type doped 4H-SiC layer or an N-type doped Ga2O3 layer.

[0020] Further, the carrier tunneling region is an N-type doped carrier tunneling region.

[0021] Further, the 3C-SiC composite epitaxial structure based on 4H-SiC further includes a P epitaxial buried layer;

[0022] The P epitaxial buried layer is disposed on the surface of the N-type doped epitaxial layer and is located between the N-type doped epitaxial layer and the 3C-SiC epitaxial layer.

[0023] Furthermore, a plurality of P-type doped buried layers are provided; the plurality of P-type doped buried layers are spaced apart and distributed in the N-type doped epitaxial layer.

[0024] In a second aspect, the present invention further provides a device structure, characterized in that the device structure includes: a 3C-SiC composite epitaxial structure based on 4H-SiC as described in the first aspect, a P-type doped connection region, a P+ region, an N+ region, a P-well region, a gate, a source electrode, and a drain electrode;

[0025] The P-type doped connection region is connected to the P-type doped buried layer in the 3C-SiC composite epitaxial structure based on 4H-SiC;

[0026] The P+ region is disposed on the 3C-SiC composite epitaxial structure based on 4H-SiC, and the P+ region is in contact connection with the P-type doped connection region at least in one cross section;

[0027] The gate is disposed on the upper part of the 3C-SiC epitaxial layer in the 3C-SiC composite epitaxial structure based on 4H-SiC;

[0028] The P-well region and the N+ region are superposed and disposed on both sides of the gate; the P-well region is located in the upper surface region of the 3C-SiC epitaxial layer, and the N+ region is located on the side of the P-well region away from the substrate of the 3C-SiC composite epitaxial structure based on 4H-SiC;

[0029] The gate is disposed at the middle position between the P-well region and the N+ region;

[0030] The source electrode is disposed on the tops of the N+ region and the P+ region;

[0031] The drain electrode is disposed at the bottom of the 3C-SiC composite epitaxial structure based on 4H-SiC.

[0032] Based on the above technical solutions, the present invention can be further improved as follows.

[0033] Furthermore, the P+ region is in contact connection with the P epitaxial buried layer of the 3C-SiC composite epitaxial structure based on 4H-SiC;

[0034] Alternatively, the device structure further includes a P-type doped grounding region, and the P-type doped grounding region is disposed around and at the bottom of the gate and is in contact connection with the P-type doped buried layer.

[0035] Furthermore, the gate is a trench gate, and the trench gate is disposed through the middle position between the N+ region and the P-well region and penetrates through the 3C-SiC epitaxial layer of the 3C-SiC composite epitaxial structure based on 4H-SiC;

[0036] Alternatively, the gate is a planar gate, and the bottom of the planar gate is connected to both the P-well region and the N+ region.

[0037] Furthermore, the device structure further includes a semi-packaged P-type connection layer;

[0038] The semi-packaged P-type connection layer vertically penetrates through the N+ region, P-well region, 3C-SiC epitaxial layer, and carrier tunneling region of the 4H-SiC-based 3C-SiC composite epitaxial structure and reaches the P epitaxial buried layer.

[0039] Compared with the prior art, the technical solution of the present application has the following beneficial technical effects:

[0040] The 4H-SiC-based 3C-SiC composite epitaxial structure and device structure provided by the present invention have the following beneficial effects compared with the prior art:

[0041] The 4H-SiC-based 3C-SiC composite epitaxial structure includes an N-type doped 4H-SiC substrate, an N-type doped epitaxial layer above the 4H-SiC substrate, an N-type doped 3C-SiC epitaxial layer above the N-type epitaxial layer, an epitaxial interface layer naturally formed between the N-type doped epitaxial layer and the 3C-SiC, an N-type doped carrier tunneling region penetrating through part of the epitaxial interface layer, and a P-type doped buried layer below the N-type doped carrier tunneling region.

[0042] (1) The composite epitaxial structure composed of 3C-SiC and 4H-SiC has a relatively narrow bandgap at the top. This means that the channel electron mobility of the power device prepared based on 3C-SiC is higher, the threshold stability of the device is higher, and the device can achieve a lower on-resistance and a higher switching frequency. It alleviates the problem that the existing 4H-SiC MOSFET gate oxide interface quality optimization technology is still limited in improving the interface state density and channel electron mobility.

[0043] (2) A highly doped N-type region is selectively implanted in the epitaxial interface layer formed between 3C-SiC and the N-type doped epitaxial layer to form a carrier tunneling region. By means of high-concentration doping, the widths of the electron potential barrier and electron potential well near the epitaxial interface become thinner, and electrons can pass through the original potential barrier and potential well by tunneling, enhancing the electron tunneling effect and reducing the on-resistance of the device. It solves the problem that after 3C-SiC and 4H-SiC are heteroepitaxially grown or bonded together, an electron potential well and potential barrier will be formed at the interface, resulting in difficult electron flow between 3C-SiC and 4H-SiC and poor on-capability of the device.

[0044] (3) A P-type doped buried layer is disposed below the carrier tunneling region. The P-type doped buried layer can shield excessive drain potential from passing through the carrier tunneling layer, reducing the electric field strength of the gate oxide in the 3C-SiC epitaxial layer and achieving the effect of protecting the gate oxide of the power device. This solves the problem that the existing technical solutions have limited protection effect on the gate trench bottom and corner oxides, especially the gate dielectric layer is extremely vulnerable to damage under extreme electrical stress conditions such as avalanche breakdown or short circuit.

[0045] (4) The P-type doped buried layer is formed during the epitaxial process, avoiding high-energy implantation after the epitaxy is completely formed and reducing the damage to the epitaxial layer lattice. This solves the problem that due to the extremely low diffusion coefficient of impurity elements in the SiC material, doping of the SiC material can often only form a PN shallow junction through high-temperature ion implantation, making it difficult to achieve deep junction implantation and high-temperature push junction of P-type doping like Si. Moreover, blindly increasing the energy of ion implantation will damage the lattice structure of SiC, affecting the electrical performance and long-term reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 It is a schematic structural diagram of a 3C-SiC composite epitaxial structure based on 4H-SiC provided in Embodiment 1 of the present invention;

[0047] Figure 2 It is a schematic structural diagram of a device structure provided in Embodiment 2 of the present invention;

[0048] Figure 3 and Figure 4 It is a schematic diagram of the grounding method and structure of two P-type doped buried layers provided in Embodiment 2 of the present invention;

[0049] Figure 5 and Figure 6 It is a schematic diagram of the distribution of multiple P-type doped buried layers in the composite epitaxial structure provided in Embodiment 3 of the present invention;

[0050] Figure 7 It is a schematic structural diagram of a 3C-SiC composite epitaxial structure based on 4H-SiC provided in Embodiment 4 of the present invention;

[0051] Figure 8 It is a schematic structural diagram of the corresponding device structure provided in Embodiment 4 of the present invention;

[0052] Figure 9 It is a schematic structural diagram of a 3C-SiC composite epitaxial structure based on 4H-SiC provided in Embodiment 5 of the present invention;

[0053] Figure 10 It is a schematic structural diagram of a device structure provided in Embodiment 6 of the present invention;

[0054] Figure 11Schematic diagram of the device structure provided in Embodiment 7 of the present invention;

[0055] Figure 12 Schematic diagram of the device structure provided in Embodiment 8 of the present invention;

[0056] Figure 13 Schematic diagram of the device structure provided in Embodiment 9 of the present invention;

[0057] Figure 14 and Figure 15 Schematic diagram of the device structure provided in Embodiment 10 of the present invention;

[0058] Figure 16 Schematic diagram of the device structure provided in Embodiment 11 of the present invention;

[0059] Figure 17 Schematic diagram of the device structure provided in Embodiment 12 of the present invention;

[0060] Figures 18 to 26 Layout diagram of the cell provided in Embodiment 13 of the present invention;

[0061] Figure 27 and 28 Cross-sectional view of the cell layout provided in Embodiment 13 of the present invention;

[0062] Figure 29 Schematic diagram of the device structure provided in Embodiment 14 of the present invention;

[0063] Figure 30 Schematic diagram of the preparation process of the 3C-SiC composite epitaxial structure based on 4H-SiC provided in Embodiment 15 of the present invention;

[0064] In the drawings, the list of components represented by each reference numeral is as follows:

[0065] 1. 4H-SiC substrate; 2. N-type doped epitaxial layer; 3. P-type doped buried layer; 4. Carrier tunneling region; 5. 3C-SiC epitaxial layer; 6. P-type doped connection region; 7. P-type doped grounding region; 8. P+ region; 9. N+ region; 10. P-well region; 11. P epitaxial buried layer; 12. Deep P+ source; 13. Semi-packaged P-type connection layer; 14. Gate; 15. Source; 16. Drain. Detailed implementation manners

[0066] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0067] The embodiments of the present invention will be further described in detail below in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but cannot be used to limit the scope of the present invention.

[0068] Example 1

[0069] As Figure 1 shown, this example provides an integrated structure based on a multi-material composite substrate structure. As Figure 1 shown, it includes: a 4H-SiC substrate 1, an N-type doped epitaxial layer 2, a P-type doped buried layer 3, a carrier tunneling region 4, and a 3C-SiC epitaxial layer 5.

[0070] The N-type doped epitaxial layer 2 is disposed on the 4H-SiC substrate 1.

[0071] Among them, the 4H-SiC substrate 1 is an N-type doped 4H-SiC layer; the N-type doped epitaxial layer 2 is an N-type doped 4H-SiC layer or an N-type doped Ga2O3 layer. In this example, the 4H-SiC layer is used as the N-type doped epitaxial layer 2 as a specific example for introduction.

[0072] The 3C-SiC epitaxial layer 5 is secondarily epitaxially grown or bonded to the surface of the N-type doped 4H-SiC epitaxial layer.

[0073] Among them, the 3C-SiC epitaxial layer 5 is an N-type doped 3C-SiC layer.

[0074] That is, the 3C-SiC epitaxial layer 5 is located at the top of the structure, and the effect it brings is that the 3C-SiC at the top has a relatively narrow bandgap width, which means that the channel electron mobility of the power device prepared based on 3C-SiC is higher, the threshold stability of the device is higher, and the device can achieve a lower on-resistance and a higher switching frequency.

[0075] A carrier tunneling region 4 is formed at the contact interface layer between the 3C-SiC epitaxial layer 5 and the N-type doped epitaxial layer 2; the P-type doped buried layer 3 is ion-implanted into the upper region of the N-type doped epitaxial layer 2.

[0076] Among them, the carrier tunneling region 4 is an N-type doped carrier tunneling region.

[0077] It should be noted that: the contact interface layer is naturally formed between two epitaxial materials, rather than deliberately set. As Figure 1 shown, the N-type doped carrier tunneling region 4 penetrates through a part of the epitaxial interface layer.

[0078] Specifically, a highly doped N-type region (carrier tunneling region 4) is selectively implanted in the 3C-SiC and 4H-SiC epitaxial interface layer. By means of high-concentration doping, the widths of the electron barrier and electron potential well near the epitaxial interface become thinner, and electrons can pass through the original barrier and potential well by tunneling, enhancing the electron tunneling effect and reducing the on-resistance of the device.

[0079] Specifically, a P-type doped buried layer 3 is disposed below the carrier tunneling region 4. The P-type doped buried layer 3 can shield the excessive drain 16 potential from passing through the carrier tunneling layer, reducing the electric field strength of the gate 14 oxide in the 3C-SiC epitaxial layer 5, and achieving the effect of protecting the gate 14 oxide of the power device.

[0080] Moreover, this embodiment provides two grounding methods and structural schematic diagrams of the P-type doped buried layer 3, which can adopt Figure 3 and Figure 4 shown in the two device interfaces, and are applied to the device structure interface in Figure 2 to achieve the grounding of the P+ doped buried layer.

[0081] The P-type buried layer is formed during the epitaxial process, avoiding high-energy implantation after the epitaxy is completely formed, and reducing the damage to the epitaxial layer lattice.

[0082] Embodiment 2

[0083] As Figure 2 shown, this embodiment provides a device structure, including: a 3C-SiC composite epitaxial structure based on 4H-SiC as in Embodiment 1, a P-type doped connection region 6, a P+ region 8, an N+ region 9, a P-well region 10, a gate 14, a source 15, and a drain 16.

[0084] The P-type doped connection region 6 is disposed in the P-type doped buried layer 3 in the 3C-SiC composite epitaxial structure based on 4H-SiC.

[0085] The P+ region 8 is disposed on the 3C-SiC composite epitaxial structure based on 4H-SiC, and the P+ region 8 is in contact connection with the P-type doped connection region 6 at least in one cross section.

[0086] In this embodiment, the gate 14 is a trench gate, and the gate 14 is disposed on the upper part of the 3C-SiC epitaxial layer 5 in the 3C-SiC composite epitaxial structure based on 4H-SiC.

[0087] On both sides of the gate 14, a superimposed P-well region 10 and an N+ region 9 are provided; the P-well region 10 is located in the upper surface region of the 3C-SiC epitaxial layer 5, and the N+ region 9 is located on the side of the P-well region 10 away from the substrate in the 3C-SiC composite epitaxial structure based on 4H-SiC.

[0088] It further includes a P-type doped grounding region 7, and the P-type doped grounding region 7 is disposed around and at the bottom of the gate 14 and is in contact connection with the P-type doped buried layer 3.

[0089] It should be noted that: in actual operation, the structural interface that can conduct current ( Figure 2 the device cross-section in Figure 3 ) and the device interface that cannot conduct current (

[0090] The source electrode 15 is disposed on the tops of the N+ region 9 and the P+ region 8.

[0091] The drain electrode 16 is disposed at the bottom of the 3C-SiC composite epitaxial structure based on 4H-SiC.

[0092] Embodiment 3

[0093] Based on Embodiment 1, the difference from Embodiment 1 is that:

[0094] In this embodiment, the P-type doped buried layer is set to be multiple; multiple P-type doped buried layers are distributed at intervals in the N-type doped epitaxial layer. Here, "multiple" means 2 or more.

[0095] Specifically, as Figure 5 shown, there are 2 P-type doped buried layers 3 in 4H-SiC, one on the top and one on the bottom; as Figure 6 shown, there are 3 P-type doped buried layers 3 in 4H-SiC, one on the top and two on the bottom, the one on the upper side is located in the middle region, and the two on the lower side are respectively located on both sides; the P-type doped buried layer in 4H-SiC can be set to more than one layer, and the advantage of doing so is that a better electric field shielding effect can be achieved; and the P-type doped buried layers between different layers can be distributed in a staggered manner or completely different distributions.

[0096] For the remaining same structures, refer to the introduction in Embodiment 1, and details are not described herein again.

[0097] Embodiment 4

[0098] Based on Embodiment 1, the difference from Embodiment 1 is that:

[0099] In this embodiment, as Figure 7 shown, the 3C-SiC composite epitaxial structure based on 4H-SiC further includes a P epitaxial buried layer 11; the P epitaxial buried layer 11 is disposed on the surface of the N-type doped epitaxial layer and is located between the N-type doped epitaxial layer and the 3C-SiC epitaxial layer.

[0100] Specifically, as Figure 7As shown, an N-type 4H-SiC - P-type 4H-SiC - N-type 3C-SiC sandwich epitaxy can be formed on the surface of 4H-SiC by means of epitaxy / implantation. The P-epitaxial buried layer can not only play the same role as the P-type doped buried layer in shielding the drain potential and enhancing the reliability of the gate oxide, but also shield the leakage current caused by defects in the interface layer between 3C-SiC and 4H-SiC under the blocking state, reducing the power consumption of the device under blocking conditions.

[0101] In addition, the P-epitaxial buried layer 11 can also act as the P-type doped connection region in Embodiment 2, as Figure 8 shown.

[0102] For the rest of the same structure, refer to the description of Embodiment 1, which will not be elaborated here.

[0103] Embodiment 5

[0104] Based on Embodiment 1, the difference from Embodiment 1 is that:

[0105] The 3C-SiC and 4H-SiC in the epitaxial material can be replaced with other semiconductor materials, as Figure 9 shown. For example, 4H-SiC can be replaced with Ga2O3 material with stronger breakdown voltage capability.

[0106] For the rest of the same structure, refer to the description of Embodiment 1, which will not be elaborated here.

[0107] Embodiment 6

[0108] Based on Embodiment 2, the difference from Embodiment 2 is that:

[0109] In this embodiment, the gate 14 is a planar gate, as Figure 10 shown, and the bottom of the planar gate is connected to both the P-well region and the N+ region.

[0110] The power device based on the composite epitaxial wafer can be other device structures such as planar gate type MOSFET, IGBT, etc. That is, a composite epitaxial structure proposed in this patent can be used to fabricate various existing semiconductor device structures.

[0111] For the rest of the same structure, refer to the description of Embodiment 2, which will not be elaborated here.

[0112] Embodiment 7

[0113] Based on Embodiment 2, the difference from Embodiment 2 is that:

[0114] In this embodiment, as Figure 11As shown, in the device structure, a deep P+ source 12 is constructed above the P+ region. The deep P+ source 12 can be formed through a source auxiliary trench. The advantage of this is to increase the source contact area and reduce the on-resistance of the device.

[0115] For the remaining same structures, refer to the description of Embodiment 2 and details will not be repeated here.

[0116] Embodiment 8

[0117] Based on Embodiments 2 and 7, the difference from Embodiment 7 is as follows:

[0118] In this embodiment, as Figure 12 shown, the material filled in the source auxiliary trench can be replaced by source metal. The advantage of this is that it can reduce the energy of P+ source ion implantation and reduce the damage to the lattice.

[0119] For the remaining same structures, refer to the description of Embodiment 2 and details will not be repeated here.

[0120] Embodiment 9

[0121] Based on Embodiments 2 and 8, the difference from Embodiment 8 is as follows:

[0122] In this embodiment, as Figure 13 shown, the source metal in the auxiliary trench can contact with the N-type doped 3C-SiC to form a Schottky diode, improving the freewheeling characteristics in the third quadrant of the device.

[0123] For the remaining same structures, refer to the description of Embodiment 2 and details will not be repeated here.

[0124] Embodiment 10

[0125] Based on Embodiment 2, the difference from Embodiment 2 is as follows:

[0126] In this embodiment, as Figure 14 shown, a semi-packaged P-type connection layer 13 can be introduced at one of the corners of the trench. The semi-packaged P-type buried layer 13 needs to wrap one side of the trench gate; the semi-packaged P-type connection layer 13 shorts the P-type doped buried layer to the source to achieve grounding. The semi-packaged P-type connection layer 13 can not only provide better protection for the trench gate oxide layer, but also reduce the cell size of the device.

[0127] The semi-packaged P-type connection layer 13 is not completely continuous but is periodically distributed. The top view is as Figure 15 shown.

[0128] For the remaining same structures, refer to the description of Embodiment 2 and details will not be repeated here.

[0129] Embodiment 11

[0130] On the basis of Embodiment 2, the difference from Embodiment 2 lies in that:

[0131] In this embodiment, as Figure 16 shown, the carrier tunneling region 4 and the trench of the device do not need to appear correspondingly in the vertical direction, which means that the requirements for the device manufacturing process by the epitaxial structure of this patent are lower and the design margin is larger.

[0132] For the remaining same structures, refer to the introduction of Embodiment 2 and will not be elaborated here.

[0133] Embodiment 12

[0134] On the basis of Embodiment 1, the difference from Embodiment 1 lies in that:

[0135] In this embodiment, as Figure 17 shown, the carrier tunneling region 4 can be non - continuous but periodically discontinuous distributed. The advantage of doing this is that the current distribution can be dispersed, and the top view is as Figure 17 shown.

[0136] It should be noted that: the carrier tunneling region, the P - type doped buried layer, and the P - type doped connection region can all be discontinuously distributed in space.

[0137] For the remaining same structures, refer to the introduction of Embodiment 1 and will not be elaborated here.

[0138] Embodiment 13

[0139] On the basis of Embodiment 2, the difference from Embodiment 2 lies in that:

[0140] In this embodiment, the layout of the cell can be a square cell, a strip cell, and a hexagonal cell, and the corresponding examples are as Figures 18 to 26 shown, where the screenshot of side A is as Figure 27 shown, and the screenshot of side B is as Figure 28 shown.

[0141] Embodiment 14

[0142] On the basis of Embodiment 2 and Embodiment 7, the difference from Embodiment 2 lies in that:

[0143] In this embodiment, as Figure 29 shown, the area of the P - type doped connection region can be adjusted, as long as it is ensured that any P - type doped buried layer is in contact with at least one P - type doped connection region, and the P - type doped connection region is in contact with at least one deep P + source electrode.

[0144] Embodiment 15

[0145] To facilitate the understanding of the 3C - SiC composite epitaxial structure based on 4H - SiC provided in Embodiment 1, asFigure 30 As shown in the figure, this embodiment correspondingly provides its preparation method:

[0146] Step S1: Prepare a 4H-SiC substrate;

[0147] Step S2: Grow a 4H-SiC epitaxial layer on the 4H-SiC substrate;

[0148] Step S3: Ion implant to form a P-type doped buried layer in the 4H-SiC epitaxial layer;

[0149] Step S4: Form an N-type doped 3C-SiC epitaxial layer on the surface of the 4H-SiC epitaxial layer by means of secondary epitaxy / bonding;

[0150] Step S5: Selectively implant a highly doped N-type region in the 3C-SiC and 4H-SiC epitaxial interface layer to form a carrier tunneling region.

[0151] That is, the 3C-SiC composite epitaxial structure based on 4H-SiC provided in Embodiment 1 is obtained.

[0152] In summary, the composite epitaxial structures provided in the above Embodiments 1 to 15, the corresponding manufacturing methods, and the corresponding device structures all have the following technical effects:

[0153] (1) The composite epitaxial structure composed of 3C-SiC and 4H-SiC has a relatively narrow bandgap at the top. This means that the channel electron mobility of the power device prepared based on 3C-SiC is higher, the threshold stability of the device is higher, and the device can achieve a lower on-resistance and a higher switching frequency. It alleviates the problem that the existing 4H-SiC MOSFET gate oxide interface quality optimization technology is still limited in improving the interface state density and channel electron mobility.

[0154] (2) A carrier tunneling region is formed by selectively implanting a highly doped N-type region in the epitaxial interface layer formed by 3C-SiC and the N-type doped epitaxial layer. By high-concentration doping, the widths of the electron barrier and electron potential well near the epitaxial interface become thinner, and electrons can pass through the barrier and potential well that could not be passed through originally by tunneling, enhancing the electron tunneling effect and reducing the on-resistance of the device. It solves the problem that after 3C-SiC and 4H-SiC are heteroepitaxially grown or bonded together, an electron potential well and a barrier are formed at the interface, resulting in difficult electron flow between 3C-SiC and 4H-SiC and poor on-capability of the device.

[0155] (3)A P-type doped buried layer is disposed below the carrier tunneling region. This P-type doped buried layer can shield excessive drain potential from passing through the carrier tunneling layer, reducing the electric field strength of the gate oxide in the 3C-SiC epitaxial layer, thereby achieving the effect of protecting the gate oxide of the power device. This solves the problem that the existing technical solutions have limited protection effects on the gate trench bottom and corner oxides, especially the gate dielectric layer is extremely prone to damage under extreme electrical stress conditions such as avalanche breakdown or short circuit.

[0156] (4)The P-type doped buried layer is formed during the epitaxial process, avoiding the need for high-energy implantation after the epitaxy is completely formed, and reducing the damage to the epitaxial layer lattice. This solves the problem that due to the extremely low diffusion coefficient of impurity elements in the SiC material, doping of the SiC material can often only form a PN shallow junction through high-temperature ion implantation, making it difficult to achieve deep junction implantation and high-temperature push junction of P-type doping like Si. Blindly increasing the energy of ion implantation will damage the lattice structure of SiC, affecting the electrical performance and long-term reliability of the device.

[0157] In the description of this specification, the description with reference to terms such as "specific examples" or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present invention. In this specification, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0158] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A 3C-SiC composite epitaxial structure based on 4H-SiC, characterized in that Including: 4H-SiC substrate, N-type doped epitaxial layer, P-type doped buried layer, carrier tunneling region and 3C-SiC epitaxial layer; The N-type doped epitaxial layer is disposed on the 4H-SiC substrate; The 3C-SiC epitaxial layer is secondarily epitaxially grown or bonded to the surface of the N-type doped epitaxial layer; A carrier tunneling region is formed at the contact interface layer between the 3C-SiC epitaxial layer and the N-type doped epitaxial layer; The P-type doped buried layer is ion-implanted into the upper region of the N-type doped epitaxial layer; The 4H-SiC substrate is an N-type doped 4H-SiC layer; the 3C-SiC epitaxial layer is an N-type doped 3C-SiC layer; The N-type doped epitaxial layer is an N-type doped 4H-SiC layer or an N-type doped Ga2O3 layer.

2. The 3C-SiC composite epitaxial structure based on 4H-SiC according to claim 1, characterized in that, The carrier tunneling region is an N-type doped carrier tunneling region.

3. The 3C-SiC composite epitaxial structure based on 4H-SiC according to claim 2, wherein The 4H-SiC-based 3C-SiC composite epitaxial structure further includes a P epitaxial buried layer; The P epitaxial buried layer is disposed on the surface of the N-type doped epitaxial layer, between the N-type doped epitaxial layer and the 3C-SiC epitaxial layer.

4. The 3C-SiC composite epitaxial structure based on 4H-SiC according to claim 1, characterized in that, The P-type doped buried layer is provided in multiple; the multiple P-type doped buried layers are spaced apart and distributed in the N-type doped epitaxial layer.

5. A device structure, characterized in that, The device structure includes: the 4H-SiC-based 3C-SiC composite epitaxial structure according to any one of claims 1 to 4, a P-type doped connection region, a P+ region, an N+ region, a P-well region, a gate, a source electrode and a drain electrode; The P-type doped connection region is disposed in the P-type doped buried layer in the 4H-SiC-based 3C-SiC composite epitaxial structure; The P+ region is disposed on the 4H-SiC-based 3C-SiC composite epitaxial structure, and the P+ region is in contact connection with the P-type doped connection region at least in one cross section; The gate is disposed on the upper part of the 3C-SiC epitaxial layer in the 4H-SiC-based 3C-SiC composite epitaxial structure; The P-well region and the N+ region are superposed and disposed on both sides of the gate; the P-well region is located in the upper surface region of the 3C-SiC epitaxial layer, and the N+ region is located on the side of the P-well region away from the substrate of the 4H-SiC-based 3C-SiC composite epitaxial structure; The source electrode is disposed on the tops of the N+ region and the P+ region; The drain electrode is disposed at the bottom of the 4H-SiC-based 3C-SiC composite epitaxial structure.

6. The device structure according to claim 5, characterized in that The P+ region is in contact connection with the P epitaxial buried layer of the 4H-SiC-based 3C-SiC composite epitaxial structure; Or, the device structure further includes a P-type doped grounding region, and the P-type doped grounding region is disposed around and at the bottom of the gate and is in contact connection with the P-type doped buried layer.

7. The device structure according to claim 6, characterized in that, The gate is a trench gate, and the trench gate is disposed through the middle position between the N+ region and the P-well region and penetrates through the 3C-SiC epitaxial layer of the 4H-SiC-based 3C-SiC composite epitaxial structure; Or, the gate is a planar gate, and the bottom of the planar gate is connected to both the P-well region and the N+ region.

8. The device structure according to claim 5, characterized in that, The device structure further includes a semi-packaged P-type connection layer; The semi-packaged P-type connection layer vertically penetrates through the N+ region, P-well region, 3C-SiC epitaxial layer, and carrier tunneling region of the 4H-SiC-based 3C-SiC composite epitaxial structure and reaches the P-epitaxial buried layer.

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