An integrated structure based on a multi-material composite substrate structure and a manufacturing method thereof

Abstract

The present invention provides an integrated structure based on a multi-material composite substrate structure and a manufacturing method thereof. In the above device, a multi-layer structure is epitaxially disposed on the multi-material composite substrate; the multi-layer structure includes a buffer layer, a high-resistance layer, and a channel layer arranged in an overlapping manner; a plurality of p-type regions are spaced in the region of the channel layer; a barrier layer is epitaxially disposed on the channel layer, and a two-dimensional electron gas is formed at the interface; a trench isolation region penetrates from the top of the barrier layer downward to the multi-material composite substrate; a first channel penetrates from the top of the barrier layer downward to the buffer layer; a second channel penetrates from the top of the barrier layer downward to the channel layer and contacts the p-type region; a passivation dielectric layer is deposited on the surface of the barrier layer, filled in the trench isolation region, and covers the inner wall sides of the first channel and the second channel. This integrated structure can effectively solve a series of problems existing in the prior art, such as the floating body effect, self-heating effect, hot carrier effect, short channel effect, latch-up effect of bulk silicon devices, power consumption, and the increase of parasitic resistance and capacitance.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly to an integrated structure based on a multi-material composite substrate structure and a manufacturing method thereof. Background Art

[0002] The semiconductor integrated circuit industry has entered the nano (nm) era. As the feature size of integrated circuits is gradually reduced to the sub-nano (100 nm) range, a series of new problems have emerged in terms of materials, device structures, processes, and reliability of bulk silicon integrated circuits. These problems mainly include:

[0003] (1) The parasitic thyristor latch-up effect of bulk silicon CMOS circuits and the soft failure effect of bulk silicon devices in a cosmic ray irradiation environment reduce the reliability of the circuit;

[0004] (2) With the reduction of device size, various multi-dimensional and non-linear effects of bulk silicon CMOS devices, such as surface energy level quantization effect, tunneling effect, short channel effect, narrow channel effect, drain-induced barrier lowering effect, hot carrier effect, sub-threshold conductance effect, velocity saturation effect, velocity overshoot effect, etc., become very significant, affecting the further improvement of device performance;

[0005] (3) The chip area occupied by the isolation region between devices relatively increases with the reduction of device size, resulting in an increase in parasitic capacitance and an extension of interconnections, affecting the improvement of integration and speed.

[0006] Meanwhile, under the development trend of increasing chip integration and miniaturization, the functions and performance of chips have been further upgraded and enhanced, but the power consumption and heat generation of chips have also increased accordingly, bringing increasingly serious power consumption and heat dissipation problems.

[0007] The adverse effects brought by excessive heat include: performance degradation, reduced reliability, safety hazards, energy waste, etc. Therefore, with the increase in chip integration, the heat dissipation problem is particularly important.

[0008] In addition, due to the limitations of its own material properties, Si materials are not suitable for use in high-frequency and high-power fields. However, the future development of integrated circuits towards high voltage, high frequency, high temperature, and high power density is an inevitable trend. Based on this, the present invention provides a new integrated structure based on a multi-material composite substrate structure and a manufacturing method thereof. Summary of the Invention

[0009] Based on the above description, the present invention provides an integrated structure based on a multi-material composite substrate structure and a manufacturing method thereof to solve a series of problems existing in integrated circuits in the prior art, such as floating body effect, self-heating effect, hot carrier effect, short channel effect, latch-up effect of bulk silicon devices, power consumption, and increase in parasitic resistance and capacitance.

[0010] The technical solution of the present invention to solve the above technical problems is as follows:

[0011] In a first aspect, the present invention provides an integrated structure based on a multi-material composite substrate structure, including: a multi-material composite substrate, a multi-layer structure, a barrier layer, a trench isolation region, a first channel, a second channel, a passivation dielectric layer, a source electrode, a drain electrode, and a gate electrode;

[0012] The multi-layer structure is epitaxially disposed on the multi-material composite substrate;

[0013] The multi-layer structure includes a buffer layer, a high-resistance layer, and a channel layer stacked in sequence from bottom to top; a plurality of p-type regions are spaced in the region of the channel layer;

[0014] The barrier layer is epitaxially disposed on the channel layer, and a two-dimensional electron gas is formed at the interface; the trench isolation region penetrates downward from the top of the barrier layer to the middle region of the multi-material composite substrate for isolating different devices; the first channel penetrates downward from the top of the barrier layer to the buffer layer for grounding the electrode; the second channel penetrates downward from the top of the barrier layer to the channel layer and contacts the p-type region for leading out the electrode of the body PN diode;

[0015] The passivation dielectric layer is deposited on the surface of the barrier layer, filled in the trench isolation region, and covers the inner wall sides of the first channel and the second channel;

[0016] The source electrode, the drain electrode, and the gate electrode are respectively disposed in the passivation dielectric layer, wherein the drain electrode is located at the top of the second channel and contacts the electrode of the body PN diode.

[0017] Based on the above technical solution, the present invention can also be improved as follows.

[0018] Further, the multi-material composite substrate includes a Si substrate, a 3C-SiC epitaxial layer, and a SiC isolation layer;

[0019] The 3C-SiC epitaxial layer is epitaxially disposed on the Si substrate;

[0020] The SiC isolation layer is bonded to the 3C-SiC epitaxial layer, and a bonding interface layer is formed between the SiC isolation layer and the 3C-SiC epitaxial layer.

[0021] Further, the SiC isolation layer is a high-purity semi-insulating SiC thin film, or a stacked combination layer of a p-type SiC layer and a high-purity semi-insulating SiC thin film.

[0022] Further, in the multi-layer structure, the buffer layer, the high-resistance layer, and the channel layer are all III-V compound semiconductor materials.

[0023] Further, the III-V compound semiconductor material is a heterojunction composed of one or at least two of GaN, GaAs, InP, Ga2O3, and AlGaN.

[0024] Further, a nucleation layer is provided at the bottom of the buffer layer.

[0025] Further, the buffer layer is a Ga2O3 buffer layer; the high-resistance layer is a high-resistance Ga2O3 layer; the channel layer is an unintentionally doped Ga2O3 channel layer; the barrier layer is an (Al x Ga 1-x )2O3 barrier layer, where 0 < x < 1, and the p-type region is a high-resistance quasi-p-Ga2O3 region;

[0026] Or, the nucleation layer is an AlN nucleation layer; the buffer layer is a GaN buffer layer; the high-resistance layer is a high-resistance GaN layer; the channel layer is a GaN channel layer; the barrier layer is an AlGaN barrier layer, and the p-type region is a p-GaN region.

[0027] Further, the integrated structure further includes a p-type layer;

[0028] The p-type layer is provided at the bottom of the gate and is located in the passivation dielectric layer.

[0029] Further, the integrated structure further includes a metal connection layer;

[0030] A plurality of the metal connection layers are respectively and spacedly provided on the top of the passivation dielectric layer and are respectively used for external connection to form a chip interconnection structure.

[0031] In a second aspect, the present invention further provides a manufacturing method for manufacturing the integrated structure based on the multi-material composite substrate structure as described in the first aspect, including:

[0032] Growing and depositing a layer of 3C-SiC epitaxial layer on a Si substrate to obtain a 3C-SiC / Si substrate;

[0033] Bonding an SiC thin film to the 3C-SiC / Si substrate to obtain an SiC / 3C-SiC / Si substrate;

[0034] Growing a multi-layer structure on the SiC / 3C-SiC / Si substrate by metalorganic chemical vapor deposition or hydride vapor epitaxy; the multi-layer structure includes a buffer layer, a high-resistance layer, and a channel layer that are sequentially stacked from bottom to top;

[0035] An epitaxial barrier layer is grown on the channel layer;

[0036] The substrate is etched locally to different depths to form vias with different depths; the channels etched into the 3C-SiC epitaxial layer are used as trench isolation regions between devices; the channels etched into the buffer layer are used for electrode grounding leads; the channels etched into the high-resistance layer are used for electrode leads of the body PN diode;

[0037] A p-type doped III-V material layer is deposited on the surface, or an undoped III-V material layer is deposited and then p-type ion implantation and annealing activation are performed to form a p-type material, and the p-type material is etched selectively to form p-type layers distributed at intervals;

[0038] A passivation dielectric layer is deposited, etched locally and filled locally. A passivation dielectric layer is covered inside the channels for grounding, and the dielectric layer at the bottom of the grounding channels is etched open to expose the buffer layer; a dielectric layer is covered on the surface of the barrier layer, and dielectric openings are made for the electrode channels; the channels of the trench isolation regions are filled with dielectric materials;

[0039] Metal is deposited and patterned, and an ohmic annealing process is carried out to form source electrodes, drain electrodes, electrode leads of the body PN diode and electrode preparation at the formed dielectric openings, and a gate electrode is formed at the p-type layer;

[0040] A passivation dielectric layer is deposited again, etched locally and planarized, and PAD electrode openings and grounding channel openings are completed;

[0041] PAD metal is deposited and patterned, and the metal for filling the grounding vias is filled to complete the multi-layer metal layer interconnection of the chip.

[0042] Compared with the prior art, the technical solution of the present application has the following beneficial technical effects:

[0043] The integrated structure based on the multi-material composite substrate structure and its manufacturing method provided by the present invention have the following beneficial effects compared with the prior art:

[0044] When the substrate in the prior art is Si, the integrated structure can effectively solve a series of problems such as hot carrier effect, short channel effect, latching effect of bulk silicon devices, power consumption, increase of parasitic resistance and capacitance; when the substrate in the prior art is SOI, a series of problems such as floating body effect, self-heating effect, increase of parasitic resistance and capacitance in the prior art are effectively solved; hetero-integration with compound semiconductors is realized, and then a high-performance and high-integration high-frequency high-voltage integrated chip is realized. Specifically:

[0045] (1) The multi-material composite substrate contains high-thermal-conductivity 3C-SiC, which can be used as a high-heat-dissipation layer for integrated circuits; the 3C-SiC layer is epitaxially grown on a Si substrate and belongs to the cubic crystal system with Si, and the process is feasible, integrating the advantages of large-size and low-cost of Si and the advantages of wide-bandgap semiconductor 3C-SiC.

[0046] (2) Bond a semi-insulating SiC thin film - SiC isolation layer to the multi-material composite substrate, which can effectively isolate the high-frequency and high-voltage chip structures; semi-insulating SiC and 3C-SiC belong to the silicon carbide system, and homogeneous bonding is more likely to achieve a high-quality bonding interface without affecting the performance of the bonding materials.

[0047] (3) Heterogeneously bond or heteroepitaxially grow III-V compound semiconductor materials on the semi-insulating SiC thin film. Compared with directly bonding or epitaxially growing III-V materials on Si, it is easier to obtain III-V semiconductor epitaxial layers with good crystal quality, which is beneficial to the preparation of high-performance materials.

[0048] (4) Using a III-V material buffer layer with general crystal quality as the ground potential layer can improve the floating body phenomenon of integrated circuits. Description of the Drawings

[0049] Figure 1 Schematic diagram of the integrated structure based on the multi-material composite substrate provided in Embodiment 1 of the present invention;

[0050] Figure 2 Schematic diagram of the multi-material composite substrate in the integrated structure based on the multi-material composite substrate provided in Embodiment 1 of the present invention;

[0051] Figure 3 Schematic diagram of the integrated structure based on the multi-material composite substrate provided in Embodiment 2 of the present invention;

[0052] Figure 4 Schematic diagram of the integrated structure based on the multi-material composite substrate provided in Embodiment 3 of the present invention;

[0053] Figure 5 Schematic diagram of the integrated structure based on the multi-material composite substrate provided in Embodiment 4 of the present invention;

[0054] Figures 6 to 13 Schematic diagrams of each step of the manufacturing process of the integrated structure based on the multi-material composite substrate provided in Embodiment 5 of the present invention;

[0055] Figure 14 Specific method diagram of step S2 in the manufacturing process of the integrated structure based on the multi-material composite substrate provided in Embodiment 5 of the present invention, which bonds the SiC thin film to the 3C-SiC / Si substrate;

[0056] In the accompanying drawings, the components represented by the reference numerals are listed as follows:

[0057] 1. Multi-material composite substrate; 101. Si substrate; 102. 3C-SiC epitaxial layer; 103. SiC isolation layer;

[0058] 2. Multilayer structure; 201. Buffer layer; 202. High resistance layer; 203. Channel layer; 204. Nucleation layer;

[0059] 3. Barrier layer;

[0060] 4. Trench isolation area;

[0061] 5. p-type region;

[0062] 6. Passivation dielectric layer;

[0063] 7. p-type layer;

[0064] 8. Source;

[0065] 9. Drain;

[0066] 10. Gate. DETAILED DESCRIPTION

[0067] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0068] Regarding a series of problems in bulk silicon integrated circuits, such as hot carrier effect, short channel effect, latch-up effect of bulk silicon devices, power consumption, parasitic resistance, increased capacitance, etc., although process technologies such as deep trench isolation, electron beam etching, silicide, and intermediate bandgap gate electrode can reduce such effects, as long as the PN junction exists, there will be a depletion region, and as long as there is a Well, there will be substrate leakage, so it cannot be solved at all.

[0069] However, the Silicon on Insulator (SOI) technology effectively overcomes the deficiencies of bulk silicon materials with its unique material structure. By forming a semiconductor thin film on an insulator, dielectric isolation of components in integrated circuits can be achieved, giving full play to the advantages of bulk silicon integrated circuit technology, especially in terms of improving switching speed and reducing parasitic effects. The earliest predecessor of SOI should be SOS (Silicon on Sapphire), which was gradually replaced by SOI. SOI technology is gradually becoming the mainstream technology for manufacturing ultra-large-scale integrated circuits with high integration, high speed, low power consumption, and high reliability.

[0070] However, SOI also has its inherent parasitic characteristics. The most typical one is the kink-effect, also known as the floating-body effect. Since the wells in SOI are all floating in the substrate, the wells are not connected to voltage. When the reverse-biased pn junction of the drain conducts current, it will increase the potential of the silicon epitaxial layer, thereby increasing the channel conductance. Therefore, as the drain voltage increases, the drain current also increases, forming a non-saturation characteristic, which reduces the drain breakdown voltage performance. Moreover, the floating-body effect will cause a series of problems such as threshold voltage fluctuation, memory effect, and hysteresis effect. Of course, connecting the substrate out can solve this problem, but it will increase the area and increase the bulk resistance.

[0071] Secondly, there is the self-heating effect. Since the bottom and the periphery are isolated by oxide, and the thermal conductivity of oxide is not good, the heat generated by carrier collisions is accumulated in the well, which will reduce the carrier lifetime.

[0072] In addition, since the top of SOI is silicon material, when it is necessary to integrate some third- and fourth-generation compound semiconductor materials to improve chip performance, reliability, and / or reduce the circuit size, other problems are often introduced due to the large mismatch between Si and other materials, limiting the further development of integrated circuits.

[0073] In summary, in the existing technology, there are various problems. First, to achieve device isolation on integrated circuits and solve a series of problems such as the hot carrier effect, short channel effect, latch-up effect of bulk silicon devices, power consumption, parasitic resistance, and capacitance increase in bulk silicon integrated circuits, it is best to use a substrate containing an insulating layer, which is conducive to implementing various isolation schemes. At the same time, the substrate has the advantages of low resistance and low cost. The current mainstream technology, the SOI substrate, is constructed in this way, but SOI technology still has some deficiencies.

[0074] Second: Using a substrate with an insulating layer as an integrated substrate, which is isolated on the periphery, resulting in the floating body effect. It is necessary to set the substrate to be grounded, but this will sacrifice area.

[0075] Third: Currently, integrated circuits are developing towards high voltage, high temperature, and high power density directions, and the chip integration density is increasing. It is necessary to improve its heat dissipation performance. The dielectric isolation layer of SOI is silicon dioxide (SiO2), which has poor thermal conductivity and has a self-heating effect.

[0076] Fourth: The lattice mismatch and thermal mismatch between Si and most compound semiconductors are relatively large. When integrated circuits need to integrate compound semiconductor devices such as InP-based devices, SiC electronic devices, and GaN-based devices, there is still no optimal solution at present. Whether using heteroepitaxy or bonding to hetero-integrate compound semiconductor materials on Si, there are some problems.

[0077] Based on this, the present invention provides a new integrated structure based on a multi-material composite substrate structure.

[0078] The following further describes the implementation manners of the present invention in detail with reference to the drawings and embodiments. The following embodiments are used to illustrate the present invention, but cannot be used to limit the scope of the present invention.

[0079] It should be noted that: The terms "first" and "second" etc. in the specification, claims, and drawings of this application are used to distinguish different objects, rather than to limit a specific order.

[0080] Embodiment 1

[0081] As Figure 1 shown, this embodiment provides an integrated structure based on a multi-material composite substrate 1. As Figure 1 shown, it includes: a multi-material composite substrate 1, a multi-layer structure 2, a barrier layer 3, a trench isolation region 4, a first channel, a second channel, a passivation dielectric layer 6, a source electrode 8, a drain electrode 9, and a gate electrode 10.

[0082] The multi-layer structure 2 is epitaxially disposed on the multi-material composite substrate 1.

[0083] The multi-layer structure 2 includes a buffer layer 201, a high-resistance layer 202, and a channel layer 203 that are sequentially stacked from bottom to top; a plurality of p-type regions 5 are spaced in the region of the channel layer 203.

[0084] The barrier layer 3 is epitaxially disposed on the channel layer 203, and a two-dimensional electron gas is formed at the interface; the trench isolation region 4 penetrates downward from the top of the barrier layer 3 to the middle region of the multi-material composite substrate 1 at most, for isolating different devices; the first channel penetrates downward from the top of the barrier layer 3 to the buffer layer 201, for grounding the electrode; the second channel penetrates downward from the top of the barrier layer 3 to the channel layer 203 and contacts the p-type region 5, for leading out the electrode of the donor PN diode.

[0085] The passivation dielectric layer 6 is deposited on the surface of the barrier layer 3, filled in the trench isolation region 4, and covers the inner wall sides of the first channel and the second channel.

[0086] The source electrode 8, the drain electrode 9, and the gate electrode 10 are respectively disposed in the passivation dielectric layer 6, wherein the drain electrode 9 is located at the top of the second channel and contacts the electrode of the bulk PN diode.

[0087] Among them, as Figure 2 shown, the multi-material composite substrate 1 includes a Si substrate 101, a 3C-SiC epitaxial layer 102, and a SiC isolation layer 103.

[0088] The 3C-SiC epitaxial layer 102 is epitaxially disposed on the Si substrate 101.

[0089] 3C-SiC has high thermal conductivity and serves as a high heat dissipation layer for the integrated circuit; 3C-SiC can be grown at a temperature lower than 1300 °C and belongs to the cubic crystal system like Si. Therefore, the 3C-SiC epitaxial layer 102 can be grown on Si while ensuring good crystal quality.

[0090] The SiC isolation layer 103 is bonded on the 3C-SiC epitaxial layer 102, and a bonding interface layer is formed between the SiC isolation layer 103 and the 3C-SiC epitaxial layer 102.

[0091] The SiC isolation layer 103 is a high-purity (HPSI, High-purity semi-insulating) semi-insulating SiC thin film. As an isolation layer, it can achieve isolation between high-frequency and high-voltage chip structures; HPSI-SiC usually uses 4H-SiC, which belongs to the same silicon carbide material as the lower layer 3C-SiC, has a small mismatch, and homogeneous bonding can simplify the bonding difficulty and improve the bonding strength.

[0092] In the multi-layer structure 2, the buffer layer 201, the high-resistance layer 202, and the channel layer 203 are all III-V compound semiconductor materials.

[0093] Preferably, the III-V compound semiconductor material is a heterojunction composed of one or at least two of GaN, GaAs, InP, Ga2O3, and AlGaN. As a device region, high-frequency, high-voltage, optoelectronic and other devices can be fabricated.

[0094] In this specific example, as Figure 1 shown, the buffer layer 201 is a Ga2O3 buffer layer 201; the high-resistance layer 202 is a high-resistance Ga2O3 layer; the channel layer 203 is an unintentionally doped Ga2O3 channel layer 203; the barrier layer 3 is an (Al x Ga 1-x )2O3 barrier layer 3, where 0 < x < 1; the p-type region 5 is a high-resistance quasi-p-Ga2O3 region.

[0095] Specifically, SiC has good compatibility with III-V materials. Whether it is epitaxy or bonding, better-quality materials can be obtained; the buffer layer 201 at the bottom of the III-V material can be connected to a potential and used as the device ground layer.

[0096] As Figure 1 shown, the integrated structure further includes a p-type layer 7; the p-type layer 7 is disposed at the bottom of the gate 10 and is located in the passivation dielectric layer 6.

[0097] Furthermore, the integrated structure further includes metal connection layers; multiple metal connection layers are respectively and spacedly disposed on the top of the passivation dielectric layer 6 and are respectively used for external connection to form a chip interconnection structure.

[0098] Specifically, as Figure 1 shown, based on the multi-material composite substrate 1, a high-performance integrated circuit with good heat dissipation performance, an effective isolation solution, improved floating body effect, and hetero-integrated compound semiconductor materials can be constructed.

[0099] In this example, the III-V material is gallium oxide Ga2O3 and an (Al x Ga 1-x )2O3 / Ga2O3 heterojunction. The buffer layer 201 can be intentionally or unintentionally doped to make it have a certain electrical property. The buffer layer 201 is grounded, and the device can be connected to the buffer layer 201 to avoid device floating. HPSI-SiC also belongs to compound semiconductors. Whether it is epitaxy or bonding, the III-V materials on it can ensure good crystal quality.

[0100] Example 2

[0101] Based on Example 1, the difference from Example 1 is that:

[0102] In this embodiment, as Figure 3 shown, in the integrated structure constructed based on the multi-material composite substrate, a nucleation layer 204 is provided at the bottom of the buffer layer 201.

[0103] Among them, the nucleation layer 204 is an AlN nucleation layer; the buffer layer 201 is a GaN buffer layer; the high-resistance layer 202 is a high-resistance GaN layer; the channel layer 203 is a GaN channel layer; the barrier layer 3 is an AlGaN barrier layer; the p-type region 5 is a p-GaN region.

[0104] Specifically, the integrated structure can be fabricated based on GaN materials. The multi-layer structure of III-V materials includes an AlN nucleation layer, which is beneficial for the nucleation and growth of GaN during subsequent heteroepitaxial growth of GaN; an unintentionally doped GaN buffer layer, and unintentionally doped GaN is usually n-type and serves as a ground potential layer; a high-resistance GaN layer that restricts the flow of carriers within the channel layer and improves the gate control ability of the device; an n-type doped GaN channel layer that provides a channel for carrier transport; and an AlGaN barrier layer that can form a polarization effect with GaN to generate a two-dimensional electron gas (2DEG).

[0105] For the remaining identical structures, refer to the description in Embodiment 1 and will not be elaborated here.

[0106] Embodiment 3

[0107] Based on Embodiment 1, the difference from Embodiment 1 is as follows:

[0108] In this embodiment, as Figure 4 shown, the bottom layer of the multi-material composite substrate can be a polycrystalline 3C-SiC substrate, that is, the polycrystalline 3C-SiC substrate replaces the above-mentioned 3C-SiC / Si substrate to form a multi-material composite substrate. The polycrystalline 3C-SiC substrate is inexpensive and has high mechanical strength.

[0109] For the remaining identical structures, refer to the description in Embodiment 1 and will not be elaborated here.

[0110] Embodiment 4

[0111] Based on Embodiment 1, the difference from Embodiment 1 is as follows:

[0112] As Figure 5 shown, the HPSI-type high-purity semi-insulating SiC thin film in the SiC isolation layer of the multi-material composite substrate can include a p-type SiC layer, that is, a stacked combination layer of a p-type SiC layer and a high-purity semi-insulating SiC thin film.

[0113] For the remaining identical structures, refer to the description in Embodiment 1 and will not be elaborated here.

[0114] Embodiment 5

[0115] This embodiment provides a manufacturing method for the integrated structure constructed based on the multi-material composite substrate provided in Embodiment 1. As Figures 6 to 13 shown, the operations are as follows:

[0116] Step S1 ( Figure 6): Deposit a layer of 3C-SiC epitaxial layer on the Si substrate to obtain a 3C-SiC / Si substrate.

[0117] Specifically, deposit a layer of 3C-SiC on the Si substrate by chemical or physical growth methods as a high heat dissipation layer.

[0118] 3C-SiC can be grown at a temperature below 1300 °C and belongs to the same cubic crystal system as Si. The 3C-SiC-on-Si substrate can have the advantages of large size and low cost, while ensuring good crystal quality.

[0119] Step S2 ( Figure 7 ): Bond the SiC thin film to the 3C-SiC / Si substrate to obtain a SiC / 3C-SiC / Si substrate.

[0120] Specifically, bond the HPSI type high-purity semi-insulating SiC thin film to the 3C-SiC / Si substrate by the Smart-cut process. The HPSI-SiC thin film serves as an isolation layer between high-frequency and high-voltage chip structures.

[0121] The specific manufacturing method is as Figure 14 shown. First, implant hydrogen ions into the HPSI type SiC wafer, then bond the SiC wafer to the 3C-SiC / Si, and through appropriate annealing treatment or the condensation method, the hydrogen-implanted wafer is completely cracked, and the semi-insulating SiC thin film is peeled off to form an HPSI-SiC / 3C-SiC / Si substrate. Chemically mechanically polish (CMP) the surface to remove residual damage and form a smooth surface.

[0122] Step S3 ( Figure 8 ): Grow a multi-layer structure on the SiC / 3C-SiC / Si substrate by metalorganic chemical vapor deposition or hydride vapor epitaxy; the multi-layer structure includes a buffer layer, a high-resistance layer, and a channel layer arranged in sequence from bottom to top.

[0123] Specifically, grow a Ga2O3 multi-layer structure on the HPSI-SiC / 3C-SiC / Si substrate by metalorganic chemical vapor deposition (MOCVD) or hydride vapor epitaxy (HVPE), including an unintentionally-doped (UID) Ga2O3 buffer layer at the bottom, a high-resistance Ga2O3 layer formed by doping regulation, and an unintentionally-doped UID-Ga2O3 channel layer at the top.

[0124] The Ga2O3 buffer layer is formed at the initial stage of epitaxy. Usually, its crystal quality is not good and it is not used for device fabrication, but it can provide a ground potential for the subsequent devices. The high-resistance Ga2O3 layer restricts the flow of carriers in the channel layer and can improve the gate control ability of the device. The UID-Ga2O3 buffer layer is formed at the later stage of epitaxy with better crystal quality and serves as the channel layer to form the device functional area.

[0125] Perform local N ion implantation and annealing on the UID-Ga2O3 buffer layer to form a high-resistance quasi-p-Ga2O3 region in some areas inside the UID-Ga2O3 buffer layer. The UID-Ga2O3 is of n-type and forms a bulk PN diode with the high-resistance quasi-p-Ga2O3 region.

[0126] As a fourth-generation ultra-wide bandgap semiconductor material, the devices fabricated with Ga2O3 have advantages such as good breakdown voltage and radiation resistance. Epitaxially growing Ga2O3 on SiC, although still a heteroepitaxy, the crystal quality of the epitaxial layer has been improved to some extent due to the smaller mismatch between them compared to the mismatch between Si and Ga2O3.

[0127] Step S4 ( Figure 9 ) : Epitaxially grow a barrier layer on the channel layer.

[0128] Specifically, epitaxially grow an (Al x Ga 1-x )2O3 barrier layer on the UID-Ga2O3. The Ga2O3 / (Al x Ga 1-x )2O3 heterojunction forms a two-dimensional electron gas (2DEG) at the interface due to the polarization effect and can be used for fabricating high-frequency devices.

[0129] Step S5 ( Figure 9 ) : Locally etch the substrate to different depths to form vias with different depths; the via etched into the 3C-SiC epitaxial layer is used as the trench isolation area between devices; the via etched into the buffer layer is used for electrode grounding; the via etched into the high-resistance layer is used for electrode extraction of the bulk PN diode.

[0130] Specifically, as Figure 9 shown, locally etch the substrate to form vias with different depths. The via etched into the 3C-SiC epitaxial layer is used as the trench isolation (Trench Isolation) area between devices in the future; the via etched into the Ga2O3 buffer layer is used for electrode grounding (GND Via) in the future; the via etched into the high-resistance quasi-p-Ga2O3 region is used for electrode extraction (Diode Via) of the bulk PN diode, so that the bulk diode is connected to the subsequent fabricated high-frequency high-voltage devices as an avalanche diode to improve the avalanche ability of the high-frequency high-voltage devices.

[0131] Step S6 (Figure 10 ): Deposit a p-type doped III-V material on the surface, or deposit an undoped III-V material and then perform p-type ion implantation and annealing activation on it to form a p-type material. Selectively etch the p-type material to form p-type layers distributed at intervals.

[0132] Specifically, in this embodiment, deposit a layer of Ga2O3 on the surface and perform N ion implantation, annealing activation, and selective etching processes to form a p-Ga2O3 layer.

[0133] Step S7 ( Figure 10 ): Deposit, locally etch, and locally fill a passivation dielectric layer. A passivation dielectric layer is covered inside the channels for grounding, and the bottom dielectric layer of the grounding channels is etched open to expose the buffer layer; a dielectric layer is covered on the surface of the barrier layer, and dielectric openings are made in the electrode channels; the channels in the trench isolation (Trench Isolation) area are filled with a dielectric material.

[0134] Step S8 ( Figure 11 ): Deposit metal and pattern it, and perform an ohmic annealing process to form source electrodes, drain electrodes, electrode leads for the body PN diode, and electrode preparation at the formed dielectric openings, and form a gate at the p-Ga2O3 layer.

[0135] Step S9 ( Figure 12 ): Deposit a passivation dielectric layer again, locally etch it, and planarize it to complete the opening of the PAD electrodes and the openings of the grounding channels.

[0136] Step S10 ( Figure 13 ): Deposit PAD metal and pattern it, fill the metal in the grounding vias, and complete the multi-layer metal layer interconnection of the chip.

[0137] Specifically, deposit PAD metal and pattern it, complete the metal filling of the grounding vias, and complete the multi-layer metal layer interconnection of the chip. This integrated structure achieves high heat dissipation performance through high-thermal-conductivity 3C-SiC; realizes the isolation between devices and chips through HPSI semi-insulating SiC and trench isolation; grounds the potential through the Ga2O3 buffer layer, and the device is electrically connected to the buffer layer to avoid the floating of the device source electrode; uses the epitaxial Ga2O3 material and the corresponding heterojunction material to fabricate high-voltage and high-frequency devices.

[0138] This integrated structure can realize a high-frequency and high-voltage integrated chip with good heat dissipation, effective isolation, improved floating body effect, high performance, and high integration.

[0139] In summary, the integrated structure and the corresponding manufacturing method based on the multi-material composite substrate structure provided in the above Embodiments 1 to 5 have the following technical effects:

[0140] (1) The multi-material composite substrate contains high-thermal-conductivity 3C-SiC, which can be used as a high-heat-dissipation layer for integrated circuits. The 3C-SiC layer is epitaxially grown on a Si substrate and belongs to the cubic crystal system with Si. The process is feasible, integrating the advantages of large-size and low-cost of Si and the advantages of wide-bandgap semiconductor 3C-SiC.

[0141] (2) Bond a layer of semi-insulating SiC thin film - SiC isolation layer to the multi-material composite substrate, which can effectively isolate high-frequency and high-voltage chip structures. Semi-insulating SiC and 3C-SiC belong to the same silicon carbide system, and homogeneous bonding is more likely to achieve a high-quality bonding interface without affecting the performance of the bonding materials.

[0142] (3) Heterogeneously bond or heteroepitaxially grow III-V compound semiconductor materials on the semi-insulating SiC thin film. Compared with directly bonding or epitaxially growing III-V materials on Si, it is easier to obtain III-V semiconductor epitaxial layers with good crystal quality, which is beneficial to the preparation of high-performance materials.

[0143] (4) Using a III-V material buffer layer with general crystal quality as the ground potential layer can improve the floating body phenomenon of integrated circuits.

[0144] That is, when the substrate in the prior art is Si, this integrated structure can effectively solve a series of problems such as hot carrier effect, short channel effect, latch-up effect of bulk silicon devices, power consumption, increase in parasitic resistance and capacitance. When the substrate in the prior art is SOI, it effectively solves a series of problems such as floating body effect, self-heating effect, increase in parasitic resistance and capacitance in the prior art. It realizes hetero-integration with compound semiconductors, and then realizes high-performance and high-integration high-frequency and high-voltage integrated chips.

[0145] In the description of this specification, the description with reference to terms such as "specific example" or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present invention. In this specification, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0146] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. And these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An integrated structure based on a multi-material composite substrate structure, characterized in that, Including: Multi-material composite substrate, multi-layer structure, barrier layer, trench isolation region, first channel, second channel, passivation dielectric layer, source electrode, drain electrode and gate electrode; The multi-layer structure is epitaxially provided on the multi-material composite substrate; The multi-layer structure includes a buffer layer, a high-resistance layer and a channel layer which are sequentially stacked from bottom to top; a plurality of p-type regions are spaced in the region of the channel layer; The barrier layer is epitaxially provided on the channel layer, and a two-dimensional electron gas is formed at the interface; the trench isolation region penetrates from the top of the barrier layer downward to the middle region of the multi-material composite substrate for isolating different devices; the first channel penetrates from the top of the barrier layer downward to the buffer layer for grounding the electrode; the second channel penetrates from the top of the barrier layer downward to the channel layer and contacts the p-type region for leading out the electrode of the donor PN diode; The passivation dielectric layer is deposited on the surface of the barrier layer, filled in the trench isolation region and covered on the inner wall sides of the first channel and the second channel; The source electrode, the drain electrode and the gate electrode are respectively provided in the passivation dielectric layer, wherein the drain electrode is located at the top of the second channel and contacts the electrode of the body PN diode; The multi-material composite substrate includes a Si substrate, a 3C-SiC epitaxial layer and a SiC isolation layer; The 3C-SiC epitaxial layer is epitaxially provided on the Si substrate; The SiC isolation layer is bonded on the 3C-SiC epitaxial layer, and a bonding interface layer is formed between the SiC isolation layer and the 3C-SiC epitaxial layer; The SiC isolation layer is a high-purity semi-insulating SiC thin film, or a stacked combination layer of a p-type SiC layer and a high-purity semi-insulating SiC thin film.

2. The integrated structure based on the multi-material composite substrate structure according to claim 1, characterized in that, In the multi-layer structure, the buffer layer, the high-resistance layer and the channel layer are all III-V compound semiconductor materials.

3. The integrated structure based on the multi-material composite substrate structure according to claim 2, characterized in that, The III-V compound semiconductor material is a heterojunction composed of one or at least two of GaN, GaAs, InP, Ga2O3, and AlGaN.

4. The integrated structure based on the multi-material composite substrate structure according to claim 2, wherein, A nucleation layer is provided at the bottom of the buffer layer.

5. The integrated structure based on the multi-material composite substrate structure according to claim 4, characterized in that, The buffer layer is a Ga2O3 buffer layer; the high-resistance layer is a high-resistance Ga2O3 layer; the channel layer is an unintentionally doped Ga2O3 channel layer; the barrier layer is an (Al x Ga 1-x )2O3 barrier layer, where 0 < x < 1, and the p-type region is a high-resistance quasi p-Ga2O3 layer; Or, the nucleation layer is an AlN nucleation layer; the buffer layer is a GaN buffer layer; the high-resistance layer is a high-resistance GaN layer; the channel layer is a GaN channel layer; the barrier layer is an AlGaN barrier layer, and the p-type region is a p-GaN region.

6. The integrated structure based on a multi-material composite substrate structure according to claim 1, wherein The integrated structure further includes a p-type layer; The p-type layer is provided at the bottom of the gate electrode and is located in the passivation dielectric layer.

7. The integrated structure based on a multi-material composite substrate structure according to claim 1, characterized in that The integrated structure further includes a metal connection layer; A plurality of the metal connection layers are respectively spaced on the top of the passivation dielectric layer and are respectively used for external connection to form a chip interconnection structure.

8. A manufacturing method for manufacturing an integrated structure based on a multi-material composite substrate structure as described in any one of claims 1 to 7, characterized in that, Including: Growing and depositing a layer of 3C-SiC epitaxial layer on a Si substrate to obtain a 3C-SiC / Si substrate; Bonding a SiC thin film to the 3C-SiC / Si substrate to obtain a SiC / 3C-SiC / Si substrate; Grow a multi-layer structure on the SiC / 3C-SiC / Si substrate by metal-organic chemical vapor deposition or hydride vapor epitaxy; the multi-layer structure includes a buffer layer, a high-resistance layer, and a channel layer arranged in sequence from bottom to top and stacked; Epitaxially grow a barrier layer on the channel layer; Etch the substrate locally to different depths to form vias with different depths; the channels etched into the 3C-SiC epitaxial layer are used as trench isolation regions between devices; the channels etched into the buffer layer are used for electrode grounding leads; the channels etched into the high-resistance layer are used for electrode leads of the body PN diode; Deposit a layer of p-type doped III-V material on the surface, or deposit a layer of undoped III-V material and then perform p-type ion implantation and annealing activation on it to form a p-type material, and selectively etch the p-type material to form p-type layers distributed at intervals; Deposit, locally etch, and locally fill a passivation dielectric layer. A passivation dielectric layer is covered inside the channels for grounding, and the dielectric layer at the bottom of the grounding channels is etched open to expose the buffer layer; a dielectric layer is covered on the surface of the barrier layer, and dielectric openings are made for the electrode channels; The channels of the trench isolation regions are filled with dielectric materials; Deposit metal and pattern it, and perform an ohmic annealing process to form source electrodes, drain electrodes, electrode leads of the body PN diode, and electrode preparation at the formed dielectric openings, and form gates at the p-type layers; Deposit a passivation dielectric layer again, locally etch it, and planarize it to complete the opening of the PAD electrodes and the opening of the grounding channels; Deposit PAD metal and pattern it, and fill the metal in the grounding vias to complete the multi-layer metal layer interconnection of the chip.

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