Integrated circuit layout design method, chip and electronic equipment
By designing modular transistors and assembling them using their connection methods, the problem of difficulty in reducing parasitic capacitance and chip area in the prior art is solved, and an efficient integrated circuit layout design is achieved, and circuit speed and customization capabilities are improved.
Patent Information
- Application Number
- CN202510002627.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-02
- Publication Date
- 2025-05-13
AI Technical Summary
When facing highly customized circuit design methods, it is difficult to effectively reduce parasitic capacitance and chip area, resulting in reduced circuit speed and increased manufacturing costs.
By designing transistors including polysilicon layer, oxidation diffusion layer, metal layer, first contact and second contact, each transistor is modularized by connecting the first contact and the second contact to achieve efficient assembly and connection, and reduce the interstage connection length and parasitic capacitance.
This method effectively reduces parasitic parameters such as interstage parasitic capacitance, reduces chip area, and improves the speed and customization capabilities of integrated circuits.
Smart Images
Figure CN119997611A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of integrated circuit design, and in particular to an integrated circuit layout design method, a chip and an electronic device. Background Art
[0002] There are two main schemes for integrated circuit layout design. One is in the field of analog / RF integrated circuit design, which uses the transistor layout model in the analog process design kit (Process Design Kit) provided by the process factory for design. The second is in the field of digital large-scale integrated circuit design, which uses the logic gate layout model in the digital standard cell (STD) provided by the process factory for design. Both schemes have disadvantages. The transistor layout model of the analog process design kit has inconsistent sizes and is restricted by semiconductor design rules, so that transistors of different sizes need to maintain a certain distance, which leads to too long connections between different transistors, introduces a large amount of parasitic capacitance, reduces the speed of the circuit, and because transistors need to maintain a certain distance, the chip area is greatly increased, which increases the cost of chip manufacturing. The basic unit of design in the digital standard library is the logic gate. Although the process factory has specially optimized the layout of the logic gate in the digital standard library so that it can be tightly arranged to better meet the needs of large-scale integrated circuit design, reduce the length of the inter-stage connection, and reduce the parasitic capacitance introduced, the transistor size in the basic unit of the digital standard library cannot be changed, making it difficult to achieve the layout design of highly customized circuits, and can only meet the design requirements of low-speed logic circuits.
[0003] Among the solutions to achieve layout optimization, one solution targets the delay of each level, and through the proper layout of transistors, the inter-level connections are shortened as much as possible, ensuring the minimum distance between levels to ensure the minimum parasitic capacitance and improve speed. Another method uses the method of folding the active area to reduce the area of a comparator layout. These methods propose solutions in the face of highly customized circuit layout design, but these solutions are not universal and there is still room for optimization. How to reduce parasitic parameters such as parasitic capacitance introduced by the layout and reduce the area of the chip are technical problems that still need to be solved. Summary of the invention
[0004] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes an integrated circuit layout design method, which can reduce parasitic parameters such as parasitic capacitance introduced by the layout and reduce the chip area.
[0005] The present application also proposes a chip manufactured using the above integrated circuit layout design method, and an electronic device including the chip.
[0006] According to the first aspect of the present application, the integrated circuit layout design method includes:
[0007] A transistor, the transistor comprising a polysilicon layer, an oxidized diffusion layer, a metal layer, a first contact and a second contact, wherein two ends of the polysilicon layer are respectively connected to the metal layer and the first contact, the oxidized diffusion layer is connected to the polysilicon layer, the second contact is arranged on the oxidized diffusion layer, and the number of the second contacts is at least two and they are symmetrically arranged on both sides of the polysilicon layer;
[0008] Among them, the transistors include P-type transistors, N-type transistors and PN-type transistors in terms of types. The first contact of the P-type transistor can be connected to the first contact of the N-type transistor to form the PN-type transistor. The P-type transistor can be connected to the PN-type transistor or the adjacent P-type transistor through the second contact. The N-type transistor can be connected to the PN-type transistor or the adjacent N-type transistor through the second contact.
[0009] According to the integrated circuit layout design method of the embodiment of the present application, at least the following beneficial effects are achieved: the P-type transistor and the N-type transistor can be connected to each other through the first contact to form a PN-type transistor, and the P-type transistor and the N-type transistor can also be installed side by side through the second contact to form a complete integrated circuit. This design method modularizes each transistor to facilitate mutual assembly, without considering the distance between transistors, and the inter-stage connection height is customizable, which greatly reduces parasitic parameters such as inter-stage parasitic capacitance.
[0010] According to some embodiments of the present application, the P-type transistor also includes a P-type semiconductor implant layer and an n-well layer, the P-type semiconductor implant layer and the n-well layer wrap the oxide diffusion layer, and the first contact is arranged inside, at the edge or outside the P-type semiconductor implant layer and the n-well layer.
[0011] According to some embodiments of the present application, the P-type semiconductor implantation layer and the n-well layer have the same size and are stacked on each other.
[0012] According to some embodiments of the present application, the N-type transistor further includes an N-type semiconductor implantation layer, which wraps the oxide diffusion layer, and the first contact is arranged inside, at the edge or outside of the N-type semiconductor implantation layer.
[0013] According to some embodiments of the present application, the number of the second contacts is four, and the four second contacts are divided into two groups and are symmetrically arranged on both sides of the polysilicon layer.
[0014] According to some embodiments of the present application, in the transistor, the polysilicon layer forms a gate of the transistor, and the oxide diffusion layer forms a source and a drain of the transistor.
[0015] According to some embodiments of the present application, the length of the transistor is equal to the distance from the first contact to the metal layer, and the width of the transistor is equal to the width of the oxide diffusion layer.
[0016] According to some embodiments of the present application, the first contact and the second contact are in a square, rectangular or circular shape.
[0017] The chip according to the second aspect of the present application is manufactured based on the above-mentioned integrated circuit layout design method.
[0018] An electronic device according to an embodiment of the third aspect of the present application includes a housing and a circuit board, wherein the circuit board includes the above-mentioned chip.
[0019] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The accompanying drawings are used to provide further understanding of the technical solution disclosed in the present application and constitute a part of the specification. Together with the embodiments disclosed in the present application, they are used to explain the technical solution disclosed in the present application and do not constitute a limitation on the technical solution disclosed in the present application.
[0021] Figure 1 A schematic diagram of the structure of a P-type transistor in the integrated circuit layout design method according to an embodiment of the present application;
[0022] Figure 2 A schematic diagram of the structure of an N-type transistor in the integrated circuit layout design method according to an embodiment of the present application;
[0023] Figure 3 This is a schematic diagram of the structure of a PN-type transistor in the integrated circuit layout design method according to an embodiment of the present application;
[0024] Figure 4 A schematic diagram of a circuit layout after splicing according to the integrated circuit layout design method of an embodiment of the present application;
[0025] Figure 5 A circuit diagram of a true single-phase clock divider;
[0026] Figure 6 This is a layout of a true single-phase clock divider.
[0027] Reference numerals: 100 - polysilicon layer, 200 - oxidation diffusion layer, 300 - metal layer, 400 - first contact, 500 - second contact, 600 - P-type semiconductor implantation layer and n-well layer, 700 - N-type semiconductor implantation layer. DETAILED DESCRIPTION
[0028] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.
[0029] In the description of the present application, it should be understood that descriptions involving orientation, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.
[0030] In the description of this application, "several" means more than one, "more" means more than two, "greater than", "less than", "exceed", etc. are understood to exclude the number itself, and "above", "below", "within", etc. are understood to include the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.
[0031] In the description of this application, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in this application based on the specific content of the technical solution.
[0032] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.
[0033] There are two main schemes for integrated circuit layout design. One is in the field of analog / RF integrated circuit design, which uses the transistor layout model in the analog process design kit (Process Design Kit) provided by the process factory for design. The second is in the field of digital large-scale integrated circuit design, which uses the logic gate layout model in the digital standard cell (STD) provided by the process factory for design. Both schemes have disadvantages. The transistor layout model of the analog process design kit has inconsistent sizes and is restricted by semiconductor design rules, so that transistors of different sizes need to maintain a certain distance, which leads to too long connections between different transistors, introduces a large amount of parasitic capacitance, reduces the speed of the circuit, and because transistors need to maintain a certain distance, the chip area is greatly increased, which increases the cost of chip manufacturing. The basic unit of design in the digital standard library is the logic gate. Although the process factory has specially optimized the layout of the logic gate in the digital standard library so that it can be tightly arranged to better meet the needs of large-scale integrated circuit design, reduce the length of the inter-stage connection, and reduce the parasitic capacitance introduced, the transistor size in the basic unit of the digital standard library cannot be changed, making it difficult to achieve the layout design of highly customized circuits, and can only meet the design requirements of low-speed logic circuits.
[0034] Among the solutions to achieve layout optimization, one solution targets the delay of each level, and through the proper layout of transistors, the inter-level connections are shortened as much as possible, ensuring the minimum distance between levels to ensure the minimum parasitic capacitance and improve speed. Another method uses the method of folding the active area to reduce the area of a comparator layout. These methods propose solutions in the face of highly customized circuit layout design, but these solutions are not universal and there is still room for optimization. How to reduce parasitic parameters such as parasitic capacitance introduced by the layout and reduce the area of the chip are technical problems that still need to be solved.
[0035] In this regard, the present application proposes an integrated circuit layout design method, in which a P-type transistor and an N-type transistor can be connected to each other through a first contact to form a PN-type transistor, and the P-type transistor and the N-type transistor can also be installed side by side through a second contact to form a complete integrated circuit. This design method modularizes each transistor to facilitate mutual assembly, without considering the distance between transistors, and the inter-stage connection is highly customizable, which greatly reduces parasitic parameters such as inter-stage parasitic capacitance.
[0036] In addition, the present application also proposes a chip manufactured based on the above-mentioned integrated circuit layout design method, and an electronic device including the chip.
[0037] Embodiment 1:
[0038] Reference Figure 1, the integrated circuit layout design method in the embodiment of the first aspect of the present application includes a transistor, and the transistor includes a polysilicon layer 100, an oxidized diffusion layer 200, a metal layer 300, a first contact 400, and a second contact 500. The two ends of the polysilicon layer 100 are respectively connected to the metal layer 300 and the first contact 400. The oxidized diffusion layer 200 is connected to the polysilicon layer 100, and it can also be connected to the metal layer 300 to form an interconnection. The second contact 500 is arranged on the oxidized diffusion layer 200, and the number of the second contacts 500 is at least two and is symmetrically arranged on both sides of the polysilicon layer 100.
[0039] Transistors include P-type transistors (see Figure 1 ), N-type transistor (refer to Figure 2 ) and PN transistors (refer to Figure 3 ). The power supply terminal is formed by a metal layer 300 with a fixed width above the P-type transistor, and the power supply terminal is formed by a metal layer 300 with a fixed width below the P-type transistor. The first contact 400 of the P-type transistor can be connected to the first contact 400 of the N-type transistor to form a PN-type transistor.
[0040] Reference Figure 4 The P-type transistor can be connected to the PN-type transistor or the adjacent P-type transistor through the second contact 500, and the N-type transistor can be connected to the PN-type transistor or the adjacent N-type transistor through the second contact 500. Thus, the contact layer of two adjacent transistors is shared, and a complete circuit layout is formed by splicing the transistors together.
[0041] Furthermore, the P-type transistor further includes a P-type semiconductor implantation layer and an n-well layer 600, the P-type semiconductor implantation layer and the n-well layer 600 wrap the oxide diffusion layer 200, and the first contact 400 can be arranged at the edge of the P-type semiconductor implantation layer and the n-well layer 600 (refer to Figure 1 a), external (refer to Figure 1 b) or internal (refer to Figure 1 c) Specifically, the P-type semiconductor implantation layer and the n-well layer have the same size and are stacked on each other.
[0042] Furthermore, the N-type transistor further includes an N-type semiconductor implantation layer 700, the N-type semiconductor implantation layer 700 wraps the oxide diffusion layer 200, and the first contact 400 is arranged at the edge of the N-type semiconductor implantation layer 700 (refer to Figure 2 a), external (refer to Figure 2 b) or internal (refer to Figure 2 c) in.
[0043] Based on the above-mentioned different structures of the P-type transistor and the N-type transistor, the PN-type transistor formed by combining them also has different structures accordingly (refer to Figure 3 a, b and c in FIG. 1 ). It is easy to understand that the specific structures of the P-type transistor, the N-type transistor and the PN-type transistor may also adopt other structures besides the above structures, which will not be described in detail here.
[0044] Furthermore, there are four second contacts 500, which are divided into two groups and symmetrically arranged on both sides of the polysilicon layer 100. By increasing the number of second contacts 500, the contact area of each transistor when connected through the second contacts 500 can be increased, thereby better transmitting electrical signals. In addition, the distance between each second contact 500 and the polysilicon layer 100 meets the minimum semiconductor manufacturing design rules.
[0045] Specifically, in the transistor, the polysilicon layer 100 forms the gate of the transistor, and the oxidized diffusion layer 200 forms the source and drain of the transistor. The length of the transistor is equal to the distance from the first contact 400 to the metal layer 300, and the width of the transistor is equal to the width of the oxidized diffusion layer 200.
[0046] Specifically, the first contact 400 and the second contact 500 are in the shape of a square, a rectangle or a circle. It is easy to understand that the contact shape may also be other shapes, which will not be described in detail here.
[0047] Embodiment 2:
[0048] A chip in an embodiment of the second aspect of the present application is made using the above-mentioned integrated circuit layout design method. By splicing the above-mentioned transistors, a chip layout with low parasitic capacitance, small chip area occupation and highly customized parameters can be achieved. In this splicing method, the contact layer of two adjacent transistors is shared, and the n-well layer, the P-type semiconductor implant layer and the N-type semiconductor implant layer overlap. The power terminals of two adjacent transistors are merged, and several transistors with basic unit mergers can be regarded as a column. According to design requirements, the integrated circuit layout can be divided into a multi-column layout, and one of the power terminals of the transistors in two adjacent columns overlaps. The layout is then interconnected using a metal layer 300 to achieve complete connection of the layout. Figure 4 The schematic diagram of each transistor after splicing is shown. After splicing, different transistors can form a highly consistent overall layout, which is convenient for large-scale integrated circuit integration. The size parameters of each transistor in the layout can be highly customized, and the positions of the first contact 400 and the second contact 500 can also be highly customized to minimize the length of the inter-level metal layer connection.
[0049] Figure 5 The circuit diagram of a true single-phase clock divider based on CMOS 65nm integrated circuit technology is shown. Figure 6The three-dimensional layout is shown, and the layout is drawn based on the integrated circuit layout method of this application. The true single-phase clock divider can operate at a frequency of 3.1GHz-15.4GHz under an input of 0dBm, while the divider with the same parameters can operate at 3GHz-14.9GHz under an input of 0dBm using an analog process design kit. The layout design scheme proposed in this application has obvious performance improvements.
[0050] Embodiment 3:
[0051] An electronic device in an embodiment of the third aspect of the present application includes a housing and a circuit board, and the circuit board includes the above-mentioned chip.
[0052] The embodiments of the present application are described in detail above in conjunction with the accompanying drawings, but the present application is not limited to the above embodiments. Various changes can be made within the knowledge of ordinary technicians in the relevant technical field without departing from the purpose of the present application. In addition, the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.
Claims
1. A method for designing an integrated circuit layout, characterized in that: include: A transistor, the transistor comprising a polysilicon layer, an oxidized diffusion layer, a metal layer, a first contact and a second contact, wherein two ends of the polysilicon layer are respectively connected to the metal layer and the first contact, the oxidized diffusion layer is connected to the polysilicon layer, the second contact is arranged on the oxidized diffusion layer, and the number of the second contacts is at least two and they are symmetrically arranged on both sides of the polysilicon layer; Among them, the transistors include P-type transistors, N-type transistors and PN-type transistors in terms of types. The first contact of the P-type transistor can be connected to the first contact of the N-type transistor to form the PN-type transistor. The P-type transistor can be connected to the PN-type transistor or the adjacent P-type transistor through the second contact. The N-type transistor can be connected to the PN-type transistor or the adjacent N-type transistor through the second contact.
2. The integrated circuit layout design method according to claim 1, characterized in that: The P-type transistor also includes a P-type semiconductor implantation layer and an n-well layer, the P-type semiconductor implantation layer and the n-well layer wrap the oxide diffusion layer, and the first contact is arranged inside, at the edge or outside the P-type semiconductor implantation layer and the n-well layer.
3. The integrated circuit layout design method according to claim 2, characterized in that: The P-type semiconductor implantation layer and the n-well layer have the same size and are stacked with each other.
4. The integrated circuit layout design method according to claim 1, wherein: The N-type transistor further includes an N-type semiconductor implantation layer, which wraps the oxidized diffusion layer, and the first contact is arranged inside, at the edge or outside of the N-type semiconductor implantation layer.
5. The integrated circuit layout design method according to claim 1, characterized in that: There are four second contacts, which are divided into two groups and symmetrically arranged on both sides of the polysilicon layer.
6. The integrated circuit layout design method according to claim 1, characterized in that: In the transistor, the polysilicon layer forms a gate of the transistor, and the oxide diffusion layer forms a source and a drain of the transistor.
7. The integrated circuit layout design method according to claim 1, characterized in that: The length of the transistor is equal to the distance from the first contact to the metal layer, and the width of the transistor is equal to the width of the oxide diffusion layer.
8. The integrated circuit layout design method according to claim 1, characterized in that: The first contact and the second contact are in a square, rectangular or circular shape.
9. A chip, characterized in that: The integrated circuit layout design method described in any one of claims 1 to 8 is used to make it.
10. An electronic device, characterized in that: It comprises a housing and a circuit board, wherein the circuit board comprises the chip according to claim 9.