Operational amplifier output ESD protection structure and integrated circuit

Abstract

The invention discloses an operational amplifier output ESD (Electro-Static Discharge) protection structure and an integrated circuit, the ESD protection structure comprises n MOS (Metal Oxide Semiconductor) tubes which are connected in parallel and n ESD resistors, and the grid electrodes of the n MOS tubes are connected together to serve as the input of the second stage of the operational amplifier; the source electrodes of the n MOS tubes are connected together and are connected with power supply voltage or the ground; the drain electrode of each MOS tube is connected with one end of one ESD resistor, and the other ends of the n ESD resistors are connected in parallel to serve as the output of the operational amplifier. According to the ESD protection circuit, the ESD protection effect is achieved on the output of the operational amplifier, the added ESD resistor has the current limiting effect, meanwhile, the speed and drive of the output stage are reduced to the minimum, the equivalent resistance is reduced, and the driving capacity and speed of the circuit are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an operational amplifier output ESD protection structure and an integrated circuit. Background Art

[0002] For integrated circuits, static electricity is an invisible killer. Therefore, when designing analog circuits, the circuits are always protected from static electricity (ESD). Usually, it is necessary to design an ESD protection structure to protect the input and output (IO) and power ground pins from ESD. When making an op amp chip, the core of the chip is an operational amplifier, and its output is directly connected to its application device, so the output of the op amp needs to be protected from ESD. Among them, IO can be written as the abbreviation of I / O input / output, which refers to the input and output pins of the chip.

[0003] Most of the existing op amp output ESD protection is directly done on the IO end, and the protection of the op amp output is achieved through the ESD protection of the IO itself, or an output resistor is connected in series at the output of the op amp. For the first protection method, relying solely on the protection of the IO itself will make the ESD protection effect of the op amp output not obvious. It is necessary to further connect a resistor in series at the output of the op amp to play a current limiting role, which is the second protection method. However, the second protection method also has a problem. The series resistor will affect the transmission speed of the output of the op amp and the driving ability. For example, the size of the series resistor is generally about 300 to 400 ohms. If the output load current of the op amp is 1mA, the output will lose a voltage drop of 300 to 400 millivolts on this resistor. This is unacceptable for some high-precision, high-output swing op amp circuits, so the output part of the op amp needs to be improved. Summary of the invention

[0004] The object of the present invention is to provide an operational amplifier output ESD protection structure and an integrated circuit in view of the deficiencies in the prior art.

[0005] The objective of the present invention is achieved through the following technical scheme: In a first aspect, an embodiment of the present invention provides an operational amplifier output ESD protection structure, comprising n parallel MOS tubes and n ESD resistors, wherein the gates of the n MOS tubes are connected together as the input of the second stage of the operational amplifier; the sources of the n MOS tubes are connected together and connected to the power supply voltage or ground; the drain of each MOS tube is connected to one end of an ESD resistor, and the other ends of the n ESD resistors are connected in parallel as the output of the operational amplifier.

[0006] Furthermore, the width-to-length ratios of the n parallel-connected MOS tubes are equal, which are all W2 / L2; assuming that the width-to-length ratio of the original operational amplifier MOS tube is W1 / L1, then W2= W1 / n, and L2= L1.

[0007] Furthermore, the resistance values ​​of the n ESD resistors are equal, namely R; assuming that the resistance value of the ESD resistor connected in series with the original operational amplifier MOS tube is R0, then R= R0.

[0008] Furthermore, the MOS tube is a PMOS tube or an NMOS tube. When the MOS tube is a PMOS tube, the sources of n PMOS tubes are connected together and connected to the power supply voltage; when the MOS tube is an NMOS tube, the sources of n NMOS tubes are connected together and connected to the ground.

[0009] A second aspect of an embodiment of the present invention provides an integrated circuit, comprising an operational amplifier and the above-mentioned operational amplifier output ESD protection structure, forming a two-stage operational amplifier circuit, wherein the operational amplifier serves as a first-stage operational amplifier, the ESD protection structure serves as a second-stage operational amplifier, and the output of the first-stage operational amplifier is connected to the input of the second-stage operational amplifier, that is, the output of the operational amplifier is connected to the input of the operational amplifier in the ESD protection structure, and the output of the operational amplifier in the ESD protection structure serves as the output of the two-stage operational amplifier circuit.

[0010] Furthermore, the internal structure of the operational amplifier is a folded Class AB output, and the output is a PMOS output or an NMOS output or a rail-to-rail output.

[0011] Furthermore, when the output of the operational amplifier is a PMOS output, the gates of n PMOS tubes are connected together and connected to the PMOS end of the operational amplifier; the sources of the n PMOS tubes are connected together and connected to the power supply voltage; the drain of each PMOS tube is connected to one end of a first ESD resistor, and the other ends of the n first ESD resistors are connected in parallel as the output of the secondary operational amplifier circuit; one end of the current mirror is connected to one end of the n first ESD resistors connected together, and the other end of the current mirror is connected to ground.

[0012] Furthermore, when the output of the operational amplifier is an NMOS output, the gates of the n NMOS tubes are connected together and connected to the NMOS end of the operational amplifier; the sources of the n NMOS tubes are connected together and connected to the ground; the drain of each NMOS tube is connected to one end of a second ESD resistor, and the other ends of the n second ESD resistors are connected in parallel as the output of the secondary operational amplifier circuit; one end of the current mirror is connected to one end of the n second ESD resistors connected together, and the other end of the current mirror is connected to the power supply voltage.

[0013] Furthermore, when the output of the operational amplifier is a rail-to-rail output, the gates of the n PMOS tubes are connected together and connected to the PMOS end of the operational amplifier; the sources of the n PMOS tubes are connected together and connected to the power supply voltage; the drain of each PMOS tube is connected to one end of a first ESD resistor, and the other ends of the n first ESD resistors are connected in parallel as the output of the secondary operational amplifier circuit; the gates of the n NMOS tubes are connected together and connected to the NMOS end of the operational amplifier; the sources of the n NMOS tubes are connected together and connected to the ground; the drain of each NMOS tube is connected to one end of a second ESD resistor, and the other ends of the n second ESD resistors are connected in parallel as the output of the secondary operational amplifier circuit; one end of the n first ESD resistors connected together is connected to one end of the n second ESD resistors connected together.

[0014] The beneficial effects of the present invention are as follows: the present invention splits the original MOS tube into n parallel MOS tubes, and each MOS tube is connected in series with an ESD resistor, thereby reducing the equivalent resistance while maintaining the width-to-length ratio of the MOS tube unchanged, and improving the driving ability and speed of the circuit while achieving electrostatic protection; the present invention has both an ESD protection effect on the output of the operational amplifier and enables the added ESD resistor to play a current limiting role while reducing the speed and drive of the output stage to a minimum. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a circuit diagram of an existing operational amplifier output ESD protection structure circuit; Figure 2 It is another circuit diagram of the existing operational amplifier output ESD protection structure circuit; Figure 3 It is a structural schematic diagram of the operational amplifier output ESD protection structure of the present invention; Figure 4 It is another structural schematic diagram of the operational amplifier output ESD protection structure of the present invention; Figure 5 It is a circuit diagram of an existing integrated circuit; Figure 6 is a circuit diagram of the integrated circuit of the present invention; Figure 7 is another circuit diagram of the integrated circuit of the present invention. DETAILED DESCRIPTION

[0016] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of devices and methods consistent with some aspects of the present invention as detailed in the appended claims.

[0017] The terms used in the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The singular forms "a", "the" and "the" used in the present invention and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0018] It should be understood that although the terms first, second, third, etc. may be used in the present invention to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present invention, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0019] The present invention is described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the features of the following embodiments and implementations can be combined with each other.

[0020] like Figure 1 and Figure 2 As shown in FIG. 1 , it is a circuit diagram of an existing general-purpose operational amplifier output ESD protection structure circuit. Figure 1 The circuit shown includes a PMOS tube and an ESD resistor R1. The gate of the PMOS tube serves as the input VIN of the op amp. The source of the PMOS tube is connected to the power supply voltage. The drain of the PMOS tube is connected to one end of the ESD resistor R1. The other end of the ESD resistor R1 serves as the output VOUT of the op amp. Figure 2 The circuit shown includes an NMOS tube and an ESD resistor R1, the gate of the NMOS tube serves as the input VIN of the operational amplifier, the source of the NMOS tube is grounded, the drain of the NMOS tube is connected to one end of the ESD resistor R1, and the other end of the ESD resistor R1 serves as the output VOUT of the operational amplifier.

[0021] Through Figure 1 and Figure 2The circuit shown in FIG. 1 is improved by splitting the original MOS tube into n parallel MOS tubes to ensure that the width-to-length ratio of the original MOS tube remains unchanged, and then each MOS tube is connected in series with an ESD resistor to avoid and reduce the equivalent resistance of the original ESD resistor, and finally the operational amplifier output ESD protection structure of the present invention is obtained. Figure 3 and Figure 4 The operational amplifier output ESD protection structure of the present invention comprises n parallel MOS tubes and n ESD resistors, wherein the gates of the n MOS tubes are connected together as the input of the operational amplifier; the sources of the n MOS tubes are connected together and connected to the power supply voltage or the ground; the drain of each MOS tube is connected to one end of an ESD resistor, and the other ends of the n ESD resistors are connected in parallel as the output of the operational amplifier. This structure has an ESD protection effect on the output of the operational amplifier, and at the same time, the added ESD resistor plays a current limiting role, while reducing the speed and drive of the output stage to a minimum.

[0022] Furthermore, the width-to-length ratios of the n parallel-connected MOS tubes are equal, which are all W2 / L2; assuming that the width-to-length ratio of the original op amp MOS tube is W1 / L1, then W2= W1 / n, L2= L1.

[0023] It should be understood that the width-to-length ratio of a MOS tube refers to the ratio of the width to the length of the conductive channel of the MOS tube. The width-to-length ratio W / L is an important parameter of the MOS tube, which determines the on-resistance and driving capability of the MOS tube. The larger the width-to-length ratio, the smaller the on-resistance of the MOS tube and the stronger the driving capability. In practical applications, the selection of the width-to-length ratio needs to be determined according to the specific indicators of the circuit.

[0024] Furthermore, the resistance values ​​of the n ESD resistors are equal, namely R; assuming that the resistance value of the ESD resistor connected in series with the original operational amplifier MOS tube is R0, then R= R0.

[0025] It should be understood that the above n value mainly depends on the driving requirements. For example, according to the driving capability of the MOS tube, the width-to-length ratio needs to be 100 / 1, and the ESD resistor needs to be 300 ohms. If 300 ohms is too large and 30 ohms is acceptable, then 10 300 ohms are connected in parallel. At this time, n=10, and then the MOS tube is split into 10 parallel 10 / 1, and the equivalent width-to-length ratio is still 100 / 1. The driving capability mainly depends on the resistance value of a single resistor. In theory, the larger the resistance, the better the current limiting effect. However, if 10 300 ohms are connected in parallel, the ESD is the same as that of a single 300 ohm resistor, but the driving capability is improved because the voltage loss on the resistor becomes i*300 / 10.

[0026] Furthermore, the MOS tube is a PMOS tube or an NMOS tube. When the MOS tube is a PMOS tube, the sources of n PMOS tubes are connected together and connected to the power supply voltage, such as Figure 3As shown; when the MOS tube is an NMOS tube, the sources of n NMOS tubes are connected together and connected to the ground, as shown in Figure 4 shown.

[0027] Specifically, Figure 1 The circuit shown in the figure is improved to obtain Figure 3 The output ESD protection structure of the operational amplifier is shown in Figure 1. In addition, since the width-to-length ratio of the MOS tube determines the load capacity of the circuit, Figure 1 When improving the circuit shown in the figure, it is necessary to keep the width-to-length ratio of the PMOS tube unchanged. Specifically, Figure 1 The width-to-length ratio of the original PMOS tube in is W1 / L1. The original PMOS tube is split into n parallel PMOS tubes. The width-to-length ratio of these n parallel PMOS tubes is equal, which is W2 / L2, where L2=L1, n*W2= W1. In this way, the width-to-length ratio of the n PMOS tubes connected in parallel is n*W2 / L2, which is equal to W1 / L1. In this way, the width-to-length ratio of the PMOS tubes before and after the split is consistent; each PMOS tube after the split is connected in series with a Figure 1 The original ESD resistor in the circuit has the same resistance value as the original ESD resistor, so that each PMOS tube has an ESD resistor to limit its current protection, and because the n resistors are in parallel, the equivalent resistance is 1 / n of the original ESD resistor. In this way, when carrying the same current, the voltage on the resistor is reduced to 1 / n of the original, which improves the driving ability and speed of the circuit. Figure 3 As shown, the operational amplifier output ESD protection structure includes n parallel PMOS tubes and n ESD resistors, wherein the gates of the n PMOS tubes are connected together as the input of the operational amplifier; the sources of the n PMOS tubes are connected together and connected to the power supply voltage; the drain of each PMOS tube is connected to one end of an ESD resistor, and the other ends of the n ESD resistors are connected in parallel as the output of the operational amplifier.

[0028] The same is true for the output of the PMOS tube mentioned above. Figure 2 The circuit shown in the figure is improved to obtain Figure 4 The output ESD protection structure of the operational amplifier is shown in Figure 1. In addition, since the width-to-length ratio of the MOS tube determines the load capacity of the circuit, Figure 2 When improving the circuit shown in the figure, it is necessary to keep the width-to-length ratio of the NMOS tube unchanged. Specifically, Figure 2The width-to-length ratio of the original NMOS tube in is W1 / L1. The original NMOS tube is split into n parallel NMOS tubes. The width-to-length ratio of these n parallel NMOS tubes is equal, which is W2 / L2, where L2=L1, n* W2= W1. In this way, the width-to-length ratio of the n NMOS tubes connected in parallel is n*W2 / L2, which is equal to W1 / L1. In this way, the width-to-length ratio of the NMOS tubes before and after the split is consistent; each NMOS tube after the split is connected in series with a Figure 2 The original ESD resistor in the circuit has the same resistance value as the original ESD resistor, so that each NMOS tube has an ESD resistor to limit its current protection, and because the n resistors are in parallel, the equivalent resistance is 1 / n of the original ESD resistor. In this way, when carrying the same current, the voltage on the resistor is reduced to 1 / n of the original, which improves the driving ability and speed of the circuit. Figure 4 As shown, the operational amplifier output ESD protection structure includes n parallel NMOS tubes and n ESD resistors, wherein the gates of the n NMOS tubes are connected together as the input of the operational amplifier; the sources of the n NMOS tubes are connected together and connected to the ground; the drain of each NMOS tube is connected to one end of an ESD resistor, and the other ends of the n ESD resistors are connected in parallel as the output of the operational amplifier.

[0029] It is worth mentioning that an embodiment of the present invention further provides an integrated circuit, including an operational amplifier and the operational amplifier output ESD protection structure of the above embodiment, constituting a two-stage operational amplifier circuit, realizing the functions of the two-stage operational amplifier, such as Figure 6 As shown. Among them, the operational amplifier is used as the first-stage operational amplifier, the ESD protection structure is used as the second-stage operational amplifier, and the output of the first-stage operational amplifier is connected to the input of the second-stage operational amplifier, that is, the output of the operational amplifier is connected to the input of the operational amplifier in the ESD protection structure, and the output of the operational amplifier in the ESD protection structure is used as the output of the secondary operational amplifier circuit.

[0030] Furthermore, the internal structure of the operational amplifier is a folded Class AB output, and the output can be a PMOS output, an NMOS output, or a rail-to-rail output.

[0031] It should be understood that Class AB is an op amp output structure that can achieve rail-to-rail output.

[0032] Figure 5The invention is an existing integrated circuit, which includes an operational amplifier, a PMOS tube, an NMOS tube and ESD resistors R1 and R2. The internal structure of the operational amplifier is a folded Class AB output. When the output of the operational amplifier is a rail-to-rail output, both VP and VN need to be connected to the output end of the first-stage operational amplifier, that is, the PMOS end of the operational amplifier is connected to the gate VP of the PMOS tube, the NMOS end of the operational amplifier is connected to the gate VN of the NMOS tube, the source of the PMOS tube is connected to the power supply voltage, the drain of the PMOS tube is connected in series with an ESD resistor R1, the source of the NMOS tube is grounded, the drain of the NMOS tube is connected in series with an ESD resistor R2, and the other ends of the ESD resistors R1 and R2 are connected together as the output VOUT of the secondary operational amplifier circuit. The ESD protection structure described in the present invention is used for Figure 5 The integrated circuit shown in the figure is improved. The circuit is Figure 5 Change to Figure 6 The integrated circuit of the present invention is obtained by a circuit diagram as shown in FIG. Figure 6 shown.

[0033] In this embodiment, when the output of the operational amplifier is rail-to-rail output, the gates of n PMOS tubes are connected together and connected to the PMOS terminal of the operational amplifier; the sources of the n PMOS tubes are connected together and connected to the power supply voltage; the drain of each PMOS tube is connected to one end of a first ESD resistor, and the other ends of the n first ESD resistors are connected in parallel as the output of the secondary operational amplifier circuit; the gates of n NMOS tubes are connected together and connected to the NMOS terminal of the operational amplifier; the sources of the n NMOS tubes are connected together and connected to ground; the drain of each NMOS tube is connected to one end of a second ESD resistor, and the other ends of the n second ESD resistors are connected in parallel as the output of the secondary operational amplifier circuit; one end of the n first ESD resistors connected together is connected to one end of the n second ESD resistors connected together, as shown in FIG. Figure 6 As shown. Furthermore, if loop compensation is required for the operational amplifier, it is necessary to add Maitreya compensation capacitors C1 and C2 and their corresponding protection resistors r1 and r2, wherein one end of the Maitreya compensation capacitor C1 is connected to the gates of n PMOS tubes, and the other end is connected to one end of its corresponding protection resistor r1, and the other end of the protection resistor r1 is connected to one end of n first ESD resistors connected together; wherein one end of the Maitreya compensation capacitor C2 is connected to the gates of n NMOS tubes, and the other end is connected to one end of its corresponding protection resistor r2, and the other end of the protection resistor r2 is connected to one end of n second ESD resistors connected together; r1 and r2 can be combined with the Maitreya compensation capacitors C1 and C2 to provide a zero point, as the protection resistors of the Maitreya compensation capacitors C1 and C2, to prevent static electricity from damaging the Maitreya compensation capacitors, as shown in Figure 7shown.

[0034] In some embodiments, when the output of the operational amplifier is a PMOS output, the first stage operational amplifier is a single-ended output of the PMOS tube. Figure 6 The n parallel NMOS tubes and the second ESD resistors connected in series can be replaced with current mirrors. Specifically, the gates of the n PMOS tubes are connected together and connected to the PMOS end of the operational amplifier; the sources of the n PMOS tubes are connected together and connected to the power supply voltage; the drain of each PMOS tube is connected to one end of a first ESD resistor, and the other ends of the n first ESD resistors are connected in parallel as the output of the secondary operational amplifier circuit; one end of the current mirror is connected to one end of the n first ESD resistors connected together, and the other end of the current mirror is connected to the ground. Further, if loop compensation is required for the operational amplifier, it is necessary to add the Maitreya compensation capacitor C1 and its corresponding protection resistor r1, wherein one end of the Maitreya compensation capacitor C1 is connected to the gates of the n PMOS tubes, and the other end is connected to one end of the corresponding protection resistor r1, and the other end of the protection resistor r1 is connected to one end of the n first ESD resistors connected together; r1 and the Maitreya compensation capacitor C1 provide a zero point as a protection resistor for the Maitreya compensation capacitor C1 to prevent static electricity from damaging the Maitreya compensation capacitor.

[0035] In some other embodiments, when the output of the operational amplifier is an NMOS output, the first stage operational amplifier is a single-ended output of the NMOS tube. Figure 6 The n parallel PMOS tubes and the first ESD resistors connected in series are replaced with current mirrors. Specifically, the gates of the n NMOS tubes are connected together and connected to the NMOS end of the operational amplifier; the sources of the n NMOS tubes are connected together and connected to the ground; the drain of each NMOS tube is connected to one end of a second ESD resistor, and the other ends of the n second ESD resistors are connected in parallel as the output of the secondary operational amplifier circuit; one end of the current mirror is connected to one end of the n second ESD resistors connected together, and the other end of the current mirror is connected to the power supply voltage. Further, if loop compensation is required for the operational amplifier, it is necessary to add the Maitreya compensation capacitor C2 and its corresponding protection resistor r2, wherein one end of the Maitreya compensation capacitor C2 is connected to the gates of the n NMOS tubes, and the other end is connected to one end of the corresponding protection resistor r2, and the other end of the protection resistor r2 is connected to one end of the n second ESD resistors connected together; r1 and the Maitreya compensation capacitor C1 provide a zero point as a protection resistor for the Maitreya compensation capacitor C1 to prevent static electricity from damaging the Maitreya compensation capacitor.

[0036] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0037] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. An operational amplifier output ESD protection structure, characterized in that: It includes n parallel MOS tubes and n ESD resistors, wherein the gates of the n MOS tubes are connected together as the input of the second stage of the operational amplifier; the sources of the n MOS tubes are connected together and connected to the power supply voltage or the ground; the drain of each MOS tube is connected to one end of an ESD resistor, and the other ends of the n ESD resistors are connected in parallel as the output of the operational amplifier.

2. The operational amplifier output ESD protection structure according to claim 1, characterized in that: The width-to-length ratios of the n parallel-connected MOS tubes are equal, which are all W2 / L2; assuming that the width-to-length ratio of the original operational amplifier MOS tube is W1 / L1, then W2= W1 / n, L2= L1.

3. The operational amplifier output ESD protection structure according to claim 1, characterized in that: The resistance values ​​of the n ESD resistors are equal, all of which are R; assuming that the resistance value of the ESD resistor connected in series with the original operational amplifier MOS tube is R0, then R= R0.

4. The operational amplifier output ESD protection structure according to claim 1, characterized in that: The MOS tube is a PMOS tube or an NMOS tube. When the MOS tube is a PMOS tube, the sources of n PMOS tubes are connected together and connected to the power supply voltage; when the MOS tube is an NMOS tube, the sources of n NMOS tubes are connected together and connected to the ground.

5. An integrated circuit, characterized in that: A two-stage operational amplifier circuit is formed by comprising an operational amplifier and the operational amplifier output ESD protection structure described in any one of claims 1 to 4, wherein the operational amplifier serves as a first-stage operational amplifier, the ESD protection structure serves as a second-stage operational amplifier, the output end of the first-stage operational amplifier is connected to the input end of the second-stage operational amplifier, that is, the output end of the operational amplifier is connected to the input end of the operational amplifier in the ESD protection structure, and the output end of the operational amplifier in the ESD protection structure serves as the output of the two-stage operational amplifier circuit.

6. The integrated circuit according to claim 5, characterized in that The internal structure of the operational amplifier is a folded Class AB output, and the output is a PMOS output or an NMOS output or a rail-to-rail output.

7. The integrated circuit according to claim 6, characterized in that When the output of the operational amplifier is a PMOS output, the gates of the n PMOS tubes are connected together and connected to the PMOS terminal of the operational amplifier; the sources of the n PMOS tubes are connected together and connected to the power supply voltage; the drain of each PMOS tube is connected to one end of a first ESD resistor, and the other ends of the n first ESD resistors are connected in parallel as the output of the secondary operational amplifier circuit; One end of the current mirror is connected to one end of the n first ESD resistors connected together, and the other end of the current mirror is connected to the ground.

8. The integrated circuit according to claim 6, characterized in that When the output of the operational amplifier is an NMOS output, the gates of the n NMOS tubes are connected together and connected to the NMOS terminal of the operational amplifier; the sources of the n NMOS tubes are connected together and connected to the ground; the drain of each NMOS tube is connected to one end of a second ESD resistor, and the other ends of the n second ESD resistors are connected in parallel as the output of the secondary operational amplifier circuit; One end of the current mirror is connected to one end of the n second ESD resistors connected together, and the other end of the current mirror is connected to the power supply voltage.

9. The integrated circuit according to claim 6, characterized in that: When the output of the operational amplifier is rail-to-rail output, the gates of n PMOS tubes are connected together and connected to the PMOS end of the operational amplifier; the sources of the n PMOS tubes are connected together and connected to the power supply voltage; the drain of each PMOS tube is connected to one end of a first ESD resistor, and the other ends of the n first ESD resistors are connected in parallel as the output of the secondary operational amplifier circuit; the gates of n NMOS tubes are connected together and connected to the NMOS end of the operational amplifier; the sources of the n NMOS tubes are connected together and connected to the ground; the drain of each NMOS tube is connected to one end of a second ESD resistor, and the other ends of the n second ESD resistors are connected in parallel as the output of the secondary operational amplifier circuit; one end of the n first ESD resistors connected together is connected to one end of the n second ESD resistors connected together.

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