Sensing substrate, sensing device and manufacturing method thereof

Abstract

The invention provides a sensing substrate. The sensing substrate comprises a first substrate, a circuit layer, a planarization layer, a sensing unit and a first bonding layer, the circuit layer is disposed on the first substrate. The planarization layer is disposed on the circuit layer, and the planarization layer includes an opening. The sensing unit is arranged on the planarization layer, and the sensing unit is electrically connected with the circuit layer through the open hole. The first bonding layer is disposed on the planarization layer. The invention also provides a sensing device and a manufacturing method thereof.

Description

Technical Field

[0001] The present disclosure relates to a sensing substrate, a sensing device and a manufacturing method thereof. Background Art

[0002] Sensors are widely used in various electronic products and have become an indispensable necessity in modern society. With the development of automation technology, the frequency of use of sensors has grown rapidly, and most modern instruments and equipment use sensors.

[0003] Array sensors are a common type of sensing device. Noise-equivalent temperature difference (NETD) is one of the important factors affecting the sensing ability of array sensors, and it is related to the tightness of the package. In the general sensing device manufacturing process, the uneven surface of the stacked structure easily causes poor tightness between the upper and lower substrates, which in turn affects the vacuum degree of the package after bonding. Moreover, the current packaging process is still relatively complex, with problems such as low process yield and high production cost.

[0004] Therefore, further improving the structural design of the sensing device and its manufacturing method, such as simplifying the manufacturing process or improving the yield, is still one of the topics that the industry is committed to researching. Summary of the invention

[0005] According to some embodiments of the present disclosure, a sensing substrate is provided, comprising a first substrate, a circuit layer, a planarization layer, a sensing unit and a first bonding layer. The circuit layer is disposed on the first substrate. The planarization layer is disposed on the circuit layer, and the planarization layer comprises an opening. The sensing unit is disposed on the planarization layer, and the sensing unit is electrically connected to the circuit layer via the opening. The first bonding layer is disposed on the planarization layer.

[0006] According to other embodiments of the present disclosure, a sensing device is provided, comprising a sensing substrate and an optical substrate. The sensing device comprises a first substrate, a circuit layer, a planarization layer, a sensing unit and a first bonding layer. The circuit layer is disposed on the first substrate. The planarization layer is disposed on the circuit layer, and the planarization layer comprises an opening. The sensing unit is disposed on the planarization layer, and the sensing unit is electrically connected to the circuit layer via the opening. The first bonding layer is disposed on the planarization layer. The optical substrate comprises a second substrate and a second bonding layer disposed on the second substrate. Furthermore, the optical substrate and the sensing substrate are bonded to each other via the first bonding layer and the second bonding layer.

[0007] According to some other embodiments of the present disclosure, a manufacturing method of a sensing device is provided, comprising providing a sensing substrate. Providing the sensing substrate comprises the following steps: providing a first substrate; forming a circuit layer on the first substrate; forming a planarization layer on the circuit layer, wherein the planarization layer comprises a first opening; forming a sensing unit on the planarization layer, wherein the sensing unit is electrically connected to the circuit layer via the first opening; and forming a first bonding layer on the planarization layer.

[0008] In order to make the features and advantages of the present disclosure more obvious and understandable, some embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1A to 1E A schematic diagram showing a cross-sectional structure of a sensing substrate in different process stages according to some embodiments of the present disclosure;

[0010] FIG. 2A to FIG. 2E A schematic diagram showing a cross-sectional structure of an optical substrate in different process stages according to some embodiments of the present disclosure;

[0011] Figure 3 A schematic diagram showing the cross-sectional structure of a sensing substrate and an optical substrate of a sensing device according to some embodiments of the present disclosure;

[0012] Figure 4 A schematic diagram showing a cross-sectional structure of a sensing device according to some embodiments of the present disclosure;

[0013] Figure 5 An equivalent circuit diagram of a sensing device according to some embodiments of the present disclosure is shown.

[0014]

Explanation of symbols

[0015] 1: Sensing device

[0016] 10A: Sensing substrate

[0017] 10B: Optical substrate

[0018] 11: Scan line driver components

[0019] 13: Read drive components

[0020] 15: Integrated Circuit Components

[0021] 100: first substrate

[0022] 100P: Opening

[0023] 100C: Circuit layer

[0024] 102: Conductive layer

[0025] 110: Planarization layer

[0026] 110P: Opening

[0027] 200: Sensing unit

[0028] 202: Conductive layer

[0029] 204a: Support component

[0030] 204b:Fixed component

[0031] 206a: Absorption layer

[0032] 206aP: Opening

[0033] 206b:Fixed component

[0034] 208: Insulation layer

[0035] 210: Sensing layer

[0036] 212: Insulation layer

[0037] 302: first seed layer

[0038] 302a: Sublayer

[0039] 302b: Sublayer

[0040] 304: First metal layer

[0041] 304a: Sublayer

[0042] 304b: Sublayer

[0043] 400: Second substrate

[0044] 402: Second seed layer

[0045] 402a: Sublayer

[0046] 402b: Sublayer

[0047] 404: Second metal layer

[0048] 404a: Sublayer

[0049] 404b: Sublayer

[0050] 410a: Anti-reflection layer

[0051] 410b: Anti-reflection layer

[0052] 500:Joint structure

[0053] AA: Active Area

[0054] BA: Surrounding Area

[0055] BD1: First bonding layer

[0056] BD2: Second bonding layer

[0057] BL: Bias signal line

[0058] CV: Cavity

[0059] DL: Data line

[0060] EP: End

[0061] FA: Fan-out area

[0062] OP1: Opening

[0063] OP2: Opening

[0064] P1: Opening

[0065] P2: Opening

[0066] PR1: First protection layer

[0067] PR2: Second protection layer

[0068] PX: Sensing Pixel

[0069] RS: Groove

[0070] SAC1: First sacrificial layer

[0071] SAC2: Second sacrificial layer

[0072] SL: Scan Line

[0073] TR: Thin Film Transistor DETAILED DESCRIPTION

[0074] The following is a detailed description of the sensing substrate, sensing device and manufacturing method thereof of the embodiments of the present disclosure. It should be understood that the following description provides many different embodiments for implementing different aspects of some embodiments of the present disclosure. The specific components and arrangements described below are only for simple and clear description of some embodiments of the present disclosure. Of course, these are only used as examples and are not limitations of the present disclosure. In addition, similar and / or corresponding numbers may be used in different embodiments to indicate similar and / or corresponding components to clearly describe the present disclosure. However, the use of these similar and / or corresponding numbers is only for the purpose of simply and clearly describing some embodiments of the present disclosure, and does not represent any correlation between the different embodiments and / or structures discussed.

[0075] It should be understood that relative terms, such as "lower" or "bottom" or "higher" or "top", may be used in the embodiments to describe the relative relationship of one component of the drawings to another component. It is understood that if the device in the drawings is turned upside down, the component described on the "lower" side will become the component on the "higher" side. The embodiments of the present disclosure can be understood in conjunction with the drawings, and the drawings of the present disclosure are also considered to be part of the disclosure. It should be understood that the drawings of the present disclosure are not drawn to scale, and in fact, the size of the components may be arbitrarily enlarged or reduced in order to clearly show the features of the present disclosure.

[0076] Furthermore, when a first material layer is mentioned as being located on or above a second material layer, it may include a situation where the first material layer is in direct contact with the second material layer or the first material layer and the second material layer may not be in direct contact, that is, there may be one or more other material layers between the first material layer and the second material layer. However, if the first material layer is directly located on the second material layer, it means that the first material layer and the second material layer are in direct contact.

[0077] In addition, it should be understood that the ordinal numbers used in the specification and claims, such as "first", "second", etc., to modify components, do not imply or represent any previous ordinal numbers of the component (or components), nor do they represent the order of one component and another component, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a component with a certain name clearly distinguishable from another component with the same name. The same words may not be used in the claims and the specification. For example, the first component in the specification may be the second component in the claims.

[0078] In some embodiments of the present disclosure, terms such as "connection", "interconnection", etc., related to bonding and connection, unless otherwise defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, wherein another structure is disposed between the two structures. Such terms related to bonding and connection may also include situations where both structures are movable, or both structures are fixed. In addition, the terms "electrically connected" or "coupled" include any direct and indirect electrical connection means.

[0079] In the text, the terms "about", "substantially", and "approximately" usually mean within 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. The term "range between a first value and a second value" means that the range includes the first value, the second value, and other values ​​therebetween. Furthermore, any two values ​​or directions used for comparison may have a certain error. If the first value is equal to the second value, it implies that there may be an error of about 10% between the first value and the second value; if the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

[0080] It should be understood that the following embodiments may replace, reorganize, or combine features in several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. The features of each embodiment may be used in any combination as long as they do not violate the spirit of the invention or conflict with each other.

[0081] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by those skilled in the art to which the present disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present disclosure.

[0082] According to an embodiment of the present disclosure, a sensing substrate is provided, comprising a sensing unit and a bonding layer arranged on a planarization layer, which can provide a relatively flat structural surface, improve the tightness during bonding, and further enhance the packaging vacuum tightness of the sensing device, improve the noise equivalent temperature difference (NETD) of the sensing device, and enhance the sensing capability of the sensing device.

[0083] Please refer to Figures 1A to 1E , Figures 1A to 1EA schematic diagram of the cross-sectional structure of a sensing substrate 10A at different process stages is shown according to some embodiments of the present disclosure. It should be understood that, according to some embodiments, additional operating steps may be provided before, during and / or after the manufacturing method of the sensing substrate 10A. According to some embodiments, some of the operating steps may be replaced or omitted. According to some embodiments, the order of some of the operating steps is interchangeable. Furthermore, for clarity of description, some components of the sensing substrate 10A may be omitted in the figure, and only some components are schematically shown. According to some embodiments, additional features may be added to the sensing substrate 10A described below. According to other embodiments, some features of the sensing substrate 10A described below may be replaced or omitted.

[0084] First, please refer to Figure 1A , providing a first substrate 100. The first substrate 100 may have an area corresponding to a peripheral area BA, an active area AA, and a fan-out area FA of the sensing device. According to some embodiments, the first substrate 100 may include a flexible substrate, a rigid substrate, or a combination thereof, but is not limited thereto. According to some embodiments, the material of the first substrate 100 may include glass, quartz, sapphire, ceramic, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polypropylene (PP), other suitable materials, or a combination thereof, but is not limited thereto. Furthermore, according to some embodiments, the first substrate 100 may include a metal-glass fiber composite sheet, or a metal-ceramic composite sheet, but is not limited thereto. In addition, the transmittance of the first substrate 100 is not limited, that is, the first substrate 100 may be a transparent substrate, a semi-transparent substrate, or an opaque substrate.

[0085] Then, a circuit layer 100C may be formed on the first substrate 100. According to some embodiments, the circuit layer 100C may include a buffer layer (not shown) and a thin film transistor TR disposed on the buffer layer, the thin film transistor TR may be located in the active area AA, and the circuit layer 100C may include a conductive component and a signal line electrically connected to the thin film transistor TR, an insulating layer formed between the conductive components, etc. According to some embodiments, the signal line may include, for example, a current signal line, a voltage signal line, a high frequency signal line, and a low frequency signal line, and the signal line may transmit a component operating voltage (VDD), a common ground terminal voltage (VSS), or a driving component terminal voltage, but the present disclosure is not limited thereto.

[0086] The thin film transistor TR may include a top gate thin film transistor, a bottom gate thin film transistor, a dual gate or double gate thin film transistor, or a combination thereof. According to some embodiments, the thin film transistor TR may be further electrically connected to a capacitor element, but is not limited thereto. The thin film transistor TR may include at least one semiconductor layer with a gate electrode layer, the semiconductor layer including a doped region with an appropriate dopant and a channel region located between the two doped regions, and the doped region may further have portions with different doping concentrations. Furthermore, the semiconductor layer may include amorphous silicon, low-temp polysilicon (LTPS), metal oxide, other suitable materials, or a combination thereof, but is not limited thereto. The metal oxide may include indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), other suitable materials, or a combination thereof, but is not limited thereto. It should be understood that the number of the thin film transistors TR is not limited to that shown in the figure, and according to different embodiments, the sensing substrate 10A may have other suitable numbers or types of thin film transistors.

[0087] like Figure 1A As shown, the circuit layer 100C may include a conductive layer 102, which may serve as a contact of a source electrode or a drain electrode of the thin film transistor TR, and may connect the source electrode or the drain electrode of the thin film transistor TR to a sensing unit 200 (eg, Figure 1E ) electrical connection.

[0088] Specifically, a portion of the gate dielectric layer and the dielectric layer in the circuit layer 100C may be removed by a patterning process to form an opening 100P, and then a conductive layer 102 may be formed in the opening 100P. According to some embodiments, a portion of the gate dielectric layer and the dielectric layer may be removed by one or more photolithography processes and / or etching processes to form the through hole 100P. According to some embodiments, the photolithography process may include photoresist coating (e.g., spin coating), soft baking, hard baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning and drying, etc., but is not limited thereto. The etching process may include a dry etching process or a wet etching process, but is not limited thereto.

[0089] According to some embodiments, the conductive layer 102 may include a metal material, a transparent conductive material, other suitable conductive materials, or a combination thereof, but not limited thereto. The metal material may include, for example, copper (Cu), silver (Ag), gold (Au), tin (Sn), aluminum (Al), molybdenum (Mo), tungsten (W), chromium (Cr), nickel (Ni), platinum (Pt), titanium (Ti), alloys of the aforementioned metals, other suitable materials, or a combination thereof, but not limited thereto. The transparent conductive material may include a transparent conductive oxide (TCO), for example, indium tin oxide (ITO), antimony zinc oxide (AZO), tin oxide (SnO), zinc oxide (ZnO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), antimony tin oxide (ATO), other suitable transparent conductive materials, or a combination thereof, but not limited thereto. According to some embodiments, the conductive layer 102 may be formed by a chemical vapor deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, other suitable processes, or a combination thereof. The chemical vapor deposition process may include, for example, a low pressure chemical vapor deposition process (LPCVD), a low temperature chemical vapor deposition process (LTCVD), a rapid temperature chemical vapor deposition process (RTCVD), a plasma assisted chemical vapor deposition process (PECVD), or an atomic layer deposition process (ALD), but is not limited thereto. The physical vapor deposition process may include, for example, a sputtering process, an evaporation process, a pulsed laser deposition, etc., but is not limited thereto.

[0090] Please refer to Figure 1A, a planarization layer 110 may be formed on the circuit layer 100C, and the planarization layer 110 may include an opening 110P. The planarization layer 110 may provide a relatively flat structural surface for the subsequent formation of the sensing unit 200 and the first bonding layer BD1. According to some embodiments, the planarization layer 110 may include an insulating material, and the insulating material may include an inorganic material or an organic material. According to some embodiments, the inorganic material may include silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, other suitable materials, or a combination of the foregoing, but is not limited thereto. According to some embodiments, the insulating material may be formed on the circuit layer 100C by a chemical vapor deposition process, a coating process, a printing process, other suitable processes, or a combination of the foregoing. In addition, the foregoing insulating material may be subjected to a planarization process to form the planarization layer 110 so that it has a substantially flat top surface. According to some embodiments, the planarization process may include a chemical-mechanical polishing (CMP) process, a grinding process, other suitable planarization processes, or a combination thereof.

[0091] Furthermore, a portion of the planarization layer 110 may be removed by a patterning process to form an opening 110P, and the opening 110P may expose the conductive layer 102. According to some embodiments, the patterning process may include one or more photolithography processes and / or etching processes.

[0092] Next, a conductive layer 202 may be formed in the opening 110P. The conductive layer 202 may serve as a conductive component of a sensing unit 200 formed subsequently, and the sensing unit 200 may be electrically connected to the circuit layer 100C via the opening 110P. According to some embodiments, the material and manufacturing method of the conductive layer 202 may be the same or similar to the material and manufacturing method of the conductive layer 102 described above, and will not be repeated here.

[0093] Please refer to Figure 1B , forming the sensing unit 200 on the planarization layer 110. As mentioned above, the sensing unit 200 can be electrically connected to the circuit layer 100C through the opening 110P. In detail, forming the sensing unit 200 on the planarization layer 110 can include the following steps.

[0094] First, a first sacrificial layer SAC1 may be formed on the planarization layer 110, and the first sacrificial layer SAC1 also covers the conductive layer 202. According to some embodiments, the material of the first sacrificial layer SAC1 may include an organic material, such as polyimide (PI), acrylic resin, SU-8 photoresist, parylene C, other suitable materials, or a combination thereof, but not limited thereto. According to some embodiments, the first sacrificial layer SAC1 may be formed by a chemical vapor deposition process, a coating process, a printing process, other suitable processes, or a combination thereof.

[0095] Furthermore, a portion of the first sacrificial layer SAC1 may be removed by a patterning process to form an opening P1, and the opening P1 may expose the conductive layer 202. According to some embodiments, the patterning process may include one or more photolithography processes and / or etching processes.

[0096] Next, a support component 204a may be formed on the first sacrificial layer SAC, and the support component 204a is also filled in the opening P1 of the first sacrificial layer SAC1. The support component 204a may support the sensing unit 200 and strengthen the structural strength of the sensing unit 200. According to some embodiments, the material of the support component 204a may include titanium nitride (TiN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), titanium aluminum oxide (TiAlO), aluminum titanium silicon (TiSiAl), titanium tungsten (TiW), titanium tungsten nitride (TiWN), aluminum nitride (AlNx), other suitable materials or a combination thereof, but is not limited thereto. According to some embodiments, the support component 204a may have a multilayer structure. Furthermore, according to some embodiments, the support component 204a may be formed by a chemical vapor deposition process, a physical vapor deposition process, a coating process, a printing process, other suitable processes, or a combination thereof.

[0097] In addition, the support component 204a can be patterned by one or more photolithography processes and / or etching processes. According to some embodiments, the support component 204a can have a ring structure. For example, in the top view, the support component 204a can have multiple bends or have a circular shape, but is not limited thereto. It is worth noting that the support component 204a can reduce heat conduction, reduce the heat dissipation of the sensing unit 200, and thus improve the sensing capability. A portion of the support component 204a is located in the opening P1 to form an opening 204aP, and the opening 204aP is located in the opening P1.

[0098] Next, a fixing component 204b may be formed in the opening 204aP. According to some embodiments, the fixing component 204b may be partially formed on the support component 204a. The fixing component 204b may further enhance the structural strength of the support component 204a. According to some embodiments, the material of the fixing component 204b may include molybdenum (Mo), molybdenum nitride (MoN), molybdenum tungsten (MoW), tungsten (W), other suitable materials, or a combination thereof, but is not limited thereto. According to some embodiments, the fixing component 204b may be formed by a chemical vapor deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, other suitable processes, or a combination thereof.

[0099] Next, a second sacrificial layer SAC2 may be formed on the support element 204a, and the second sacrificial layer SAC2 also covers the first sacrificial layer SAC1 and the fixing element 204b. According to some embodiments, the material and manufacturing method of the second sacrificial layer SAC2 may be the same or similar to the material and manufacturing method of the first sacrificial layer SAC1, and will not be repeated here.

[0100] Furthermore, a portion of the second sacrificial layer SAC2 may be removed by a patterning process to form an opening P2, and the opening P2 may expose the support element 204a. According to some embodiments, the patterning process may include one or more photolithography processes and / or etching processes.

[0101] Next, an absorption layer 206a may be formed on the second sacrificial layer SAC2, and the absorption layer 206a is also filled in the opening P2 of the second sacrificial layer SAC2. The absorption layer 206a may absorb light within a wavelength range to be detected. For example, according to some embodiments, the absorption layer 206a may absorb infrared (IR), such as longwave infrared (LWIR), shortwave infrared (SWIR), middle wave infrared (MWIR) or far infrared (FIR). According to some embodiments, the material of the absorption layer 206a may include titanium (Ti), titanium nitride (TiN), platinum (Pt), gold (Au), nickel (Ni), niobium (Nb), other suitable materials or combinations thereof, but are not limited thereto. According to some embodiments, the absorption layer 206 a may be formed by a chemical vapor deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, other suitable processes, or a combination thereof.

[0102] Furthermore, according to some embodiments, a portion of the absorption layer 206a is located in the opening P2 to form an opening 206aP, and the opening 206aP is located within the opening P2.

[0103] Next, a fixing element 206b may be formed in the opening 206aP. According to some embodiments, the fixing element 206b may be partially formed on the absorption layer 206a. The fixing element 206b may fix the absorption layer 206a to the support element 204a. According to some embodiments, the material and manufacturing method of the fixing element 206b may be the same or similar to the material and manufacturing method of the fixing element 204b described above, and will not be repeated here.

[0104] Next, an insulating layer 208 may be formed on the absorption layer 206a, and the insulating layer 208 also covers the second sacrificial layer SAC2 and the fixing element 206b. According to some embodiments, the material of the insulating layer 208 may include silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), other suitable materials, or a combination thereof, but is not limited thereto. According to some embodiments, the insulating layer 208 may be formed by a chemical vapor deposition process, a physical vapor deposition process, a coating process, a printing process, other suitable processes, or a combination thereof.

[0105] Furthermore, a portion of the insulating layer 208 may be removed by a patterning process to expose two end portions EP of the absorption layer 206a. According to some embodiments, the patterning process may include one or more photolithography processes and / or etching processes.

[0106] Next, a sensing layer 210 may be formed on the insulating layer 208, and the sensing layer 210 may contact the two end portions EP of the absorption layer 206a. The sensing layer 210 may have a thermo-sensitive property, and the two ends of the sensing layer 210 are connected to the absorption layer 206a, thereby forming a resistor structure. Specifically, one end of the resistor structure may be electrically connected to the conductive layer 202 and the conductive layer 102 through the support structure 204a, and then electrically connected to the thin film transistor TR of the circuit layer 100C, while the other end of the resistor structure may be electrically connected to the conductive layer 202 (for convenience of explanation, marked as 202-b) connected to the bias signal line. According to some embodiments, the material of the sensing layer 210 may include amorphous silicon (a-Si), vanadium oxide (VOx), yttrium barium copper oxide (YBaCuO), germanium silicon oxide (GeSiO), germanium silicon (SiGe), bismuth lanthanum strontium manganese oxide (BiLaSrMnO), other suitable materials or combinations thereof, but are not limited thereto. According to some embodiments, the sensing layer 210 may be formed by a chemical vapor deposition process, a physical vapor deposition process, a coating process, a printing process, other suitable processes, or a combination thereof.

[0107] Next, an insulating layer 212 may be formed on the sensing layer 210. According to some embodiments, the material and manufacturing method of the insulating layer 212 may be the same as or similar to the material and manufacturing method of the insulating layer 208, and will not be repeated here.

[0108] Please refer to Figure 1C , Figure 1D as well as Figure 1E , forming a first bonding layer BD1 on the planarization layer 110. First, a first seed layer 302 may be formed on the planarization layer 110. Specifically, the first seed layer 302 may be formed on the planarization layer 110 located in the peripheral area BA and the fan-out area FA. According to some embodiments, the first seed layer 302 may have a multi-layer structure, for example, a sub-layer 302a and a sub-layer 302b disposed on the sub-layer 302a. According to some embodiments, the material of the sub-layer 302a may include molybdenum (Mo), titanium (Ti) or other suitable materials, but is not limited thereto. According to some embodiments, the material of the sub-layer 302b may include copper (Cu) or other suitable materials, but is not limited thereto. It should be understood that although the first seed layer 302 shown in the drawings has two sub-layers, the present disclosure is not limited thereto. According to some embodiments, the first seed layer 302 may have other suitable numbers or types of sub-layers. According to some embodiments, the first seed layer 302 may include a molybdenum / copper composite layer, a titanium / copper composite layer, a molybdenum / aluminum composite layer, or a titanium / aluminum composite layer. The titanium / copper composite layer may not only serve as a seed layer, but also serve as a getter to absorb outgassing. According to some embodiments, the first seed layer 302 may be formed by a chemical vapor deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, other suitable processes, or a combination thereof.

[0109] Next, a first protective layer PR1 may be formed on the first seed layer 302. Specifically, the first protective layer PR1 may be formed on the peripheral area BA, the active area AA, and the fan-out area FA, and the first protective layer PR1 also covers the components of the sensing unit 200 formed above. According to some embodiments, the material of the first protective layer PR1 may include a photoresist material, but is not limited thereto. According to some embodiments, the first protective layer PR1 may be formed by a chemical vapor deposition process, a physical vapor deposition process, a coating process, a printing process, other suitable processes, or a combination of the foregoing.

[0110] Furthermore, a portion of the first protection layer PR1 may be removed by a patterning process to form an opening OP1, and the opening OP1 may expose the first seed layer 302. Specifically, the opening OP1 may expose a portion of the top surface of the upper sub-layer 302b in the first seed layer 302. According to some embodiments, the patterning process may include one or more photolithography processes and / or etching processes.

[0111] Next, a first metal layer 304 may be formed in the opening OP1, and the first metal layer 304 is located on the first seed layer 302. Here, the first bonding layer BD1 is substantially completed. According to some embodiments, the first metal layer 304 may have a multilayer structure, for example, a sublayer 304a and a sublayer 304b disposed on the sublayer 304a. According to some embodiments, the material of the sublayer 304a may include copper (Cu) or other suitable materials, but is not limited thereto. According to some embodiments, the material of the sublayer 304b may include tin (Sn) or other suitable materials, but is not limited thereto. It should be understood that although the first metal layer 304 shown in the drawings has two sublayers, the present disclosure is not limited thereto, and according to some embodiments, the first metal layer 304 may have other suitable numbers or types of sublayers. According to some embodiments, the first metal layer 304 may include a tin / copper composite layer, a tin / gold / nickel / copper composite layer, a tin / gold / nickel composite layer, a gold / nickel composite layer, or a gold / nickel / copper composite layer. According to some embodiments, the first metal layer 304 may be formed by a chemical vapor deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, other suitable processes, or a combination thereof.

[0112] Next, please refer to Figure 1E , remove the first protection layer PR1 to expose the first bonding layer BD1. It is worth noting that the step of removing the first protection layer PR1 can also remove the first sacrificial layer SAC1 and the second sacrificial layer SAC2 at the same time to expose the sensing unit 200. After removing the first sacrificial layer SAC1 and the second sacrificial layer SAC2, the sensing unit 200 and the sensing substrate 10A are substantially completed. According to some embodiments, the organic material can be removed by a plasma etching process, for example, the first protection layer PR1, the first sacrificial layer SAC1 and the second sacrificial layer SAC2 are removed, but it is not limited thereto.

[0113] As mentioned above, the step of removing the first sacrificial layer SAC1 and the second sacrificial layer SAC2 is performed after the step of forming the first bonding layer BD1 on the planarization layer 110 , thereby protecting the metal wiring in the sensing unit 200 and reducing the damage to the metal wiring caused by the etching process.

[0114] like Figure 1E As shown, the formed sensing substrate 10A may include a first substrate 100, a circuit layer 100C, a planarization layer 110, a sensing unit 200, and a first bonding layer BD1. The circuit layer 100C may be disposed on the first substrate 100. The planarization layer 110 may be disposed on the circuit layer 100C, and the planarization layer 110 may include an opening 110P. The sensing unit 200 may be disposed on the planarization layer 110, and the sensing unit 200 may be electrically connected to the circuit layer 100C through the opening 110P. The first bonding layer BD1 may be disposed on the planarization layer 110.

[0115] According to some embodiments, the sensing unit 200 may include an absorption layer 206a, an insulating layer 208, an insulating layer 212, and a sensing layer 210. The insulating layer 208 and the insulating layer 212 may be disposed on the absorption layer 206a, and the sensing layer 210 may be disposed between the insulating layer 208 and the insulating layer 212. According to some embodiments, the sensing unit 200 may further include a supporting component 204a, and the supporting component 204a may be disposed between the planarization layer 110 and the absorption layer 206a. According to some embodiments, the sensing unit 200 may further include a fixing component 204b, and the fixing component 204b may be disposed in an opening 204aP of the supporting component. Furthermore, according to some embodiments, the sensing unit 200 may further include a fixing component 206b, and the fixing component 206b may be disposed in the opening 206aP of the absorption layer 206a.

[0116] According to some embodiments, the first bonding layer BD1 may surround the sensing unit 200. As mentioned above, according to some embodiments, the support element 204a may have a ring structure. For example, in the top view, the support element 204a may have a plurality of bends or have a circular shape, but is not limited thereto. According to some embodiments, the first bonding layer BD1 may include a first seed layer 302 and a first metal layer 304 disposed on the first seed layer 302. According to some embodiments, the first seed layer 302 may include a molybdenum / copper composite layer, a titanium / copper composite layer, a molybdenum / aluminum composite layer, or a titanium / aluminum composite layer. According to some embodiments, the first metal layer 304 may include a tin / copper composite layer, a tin / gold / nickel / copper composite layer, a tin / gold / nickel composite layer, a gold / nickel composite layer, or a gold / nickel / copper composite layer.

[0117] It is worth noting that the aforementioned sensing unit 200 and the first bonding layer BD1 can be located on the same side of the planarization layer 110, which can provide a relatively flat structural surface and improve the sensing substrate 10A and the opposite optical substrate 10B (such as Figure 2E The tightness of the packaging vacuum tightness of the sensing device can be improved.

[0118] Please refer to FIG. 2A to FIG. 2E , FIG. 2A to FIG. 2EA schematic diagram of the cross-sectional structure of an optical substrate 10B at different process stages according to some embodiments of the present disclosure is shown. It should be understood that, according to some embodiments, additional operating steps may be provided before, during and / or after the method for manufacturing the optical substrate 10B. According to some embodiments, some of the operating steps described may be replaced or omitted. According to some embodiments, the order of some of the operating steps described is interchangeable. Furthermore, for clarity of description, some components of the optical substrate 10B may be omitted in the figure, and only some components are schematically shown. According to some embodiments, additional features may be added to the optical substrate 10B described below. According to other embodiments, some features of the optical substrate 10B described below may be replaced or omitted.

[0119] First, please refer to Figure 2A , provide a second substrate 400, and the second substrate 400 can be used as a cover. According to some embodiments, the second substrate 400 can have the function of filtering a specific band, for example, the second substrate 400 can filter out light outside the range of the band to be detected. According to some embodiments, the material of the second substrate 400 can include silicon (Si), germanium (Ge), chalcogenide glass, gallium arsenide (GaAs), other suitable materials or a combination of the foregoing, but is not limited thereto. According to some embodiments, the second substrate 400 can further include an optical coating (not shown) disposed on its surface, and the material of the optical coating can include germanium (Ge), zinc sulfide (ZnS), zinc selenide (ZnSe), magnesium fluoride (MgF 2 ), beryllium fluoride (BeF 2 ), potassium chloride (KCl), arsenic sulfide (As 2 S 3 ), other suitable materials or the combination thereof, but not limited thereto. Next, a second bonding layer BD2 may be formed on the second substrate 400. First, as Figure 2AAs shown, a second seed layer 402 may be first formed on the second substrate 400. Specifically, a first seed layer 402 may be formed on the second substrate 400 located in the peripheral area BA and the fan-out area FA. According to some embodiments, the second seed layer 402 may have a multi-layer structure, for example, a sub-layer 402a and a sub-layer 402b disposed on the sub-layer 402a. According to some embodiments, the material of the sub-layer 402a may include molybdenum (Mo), titanium (Ti) or other suitable materials, but is not limited thereto. According to some embodiments, the material of the sub-layer 402b may include copper (Cu) or other suitable materials, but is not limited thereto. It should be understood that although the second seed layer 402 shown in the drawings has two sub-layers, the present disclosure is not limited thereto. According to some embodiments, the second seed layer 402 may have other suitable numbers or types of sub-layers. According to some embodiments, the second seed layer 402 may include a molybdenum / copper composite layer or a titanium / copper composite layer. In addition to being a seed layer, the titanium / copper composite layer can also be used as a getter to absorb outgassing. According to some embodiments, the second seed layer 402 can be formed by a chemical vapor deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, other suitable processes, or a combination thereof.

[0120] Next, please refer to Figure 2B , a second protection layer PR2 may be formed on the second seed layer 402. Specifically, the second protection layer PR2 may be formed on the peripheral area BA, the active area AA, and the fan-out area FA. According to some embodiments, the material and manufacturing method of the second protection layer PR2 may be the same or similar to the material and manufacturing method of the first protection layer PR1, and will not be repeated here.

[0121] Furthermore, a portion of the second protection layer PR2 may be removed by a patterning process to form an opening OP2, and the opening OP2 may expose the second seed layer 402. Specifically, the opening OP2 may expose a portion of the top surface of the upper sub-layer 402b in the second seed layer 402. According to some embodiments, the patterning process may include one or more photolithography processes and / or etching processes.

[0122] Next, please refer to Figure 2C, a second metal layer 404 may be formed in the opening OP2, and the second metal layer 404 is located on the second seed layer 402. According to some embodiments, the second metal layer 404 may have a multilayer structure, for example, a sublayer 404a and a sublayer 404b disposed on the sublayer 404a. According to some embodiments, the material of the sublayer 404a may include copper (Cu) or other suitable materials, but is not limited thereto. According to some embodiments, the material of the sublayer 404b may include tin (Sn) or other suitable materials, but is not limited thereto. It should be understood that although the second metal layer 404 shown in the drawings has two sublayers, the present disclosure is not limited thereto, and according to some embodiments, the second metal layer 404 may have other suitable numbers or types of sublayers. According to some embodiments, the second metal layer 404 may include a tin / copper composite layer, a tin / gold / nickel / copper composite layer, or a gold / nickel / copper composite layer. According to some embodiments, the second metal layer 404 may be formed by a chemical vapor deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, other suitable processes, or a combination thereof.

[0123] Next, please refer to Figure 2D , remove the second protective layer PR2 to expose the second bonding layer BD2. It is worth noting that the step of removing the second protective layer PR2 may also remove a portion of the second substrate 400 at the same time to form a recess RS in the second substrate 400. According to some embodiments, the second protective layer PR2 and a portion of the second substrate 400 may be removed by a plasma etching process, but is not limited thereto.

[0124] Please refer to Figure 2D After removing the second protective layer PR2, an anti-reflection layer 410a and an anti-reflection layer 410b may be formed on both side surfaces of the second substrate 400, and the anti-reflection layer 410a may be disposed in the groove RS. The anti-reflection layer 410a and the anti-reflection layer 410b may reduce the reflectivity and increase the light transmittance. According to some embodiments, the materials of the anti-reflection layer 410a and the anti-reflection layer 410b may include germanium (Ge), zinc sulfide (ZnS), zinc selenide (ZnSe), magnesium fluoride (MgF 2 ), beryllium fluoride (BeF 2 ), potassium chloride, arsenic trisulfide (As 2 S 3 ), other suitable materials or the combination thereof, but not limited thereto. Furthermore, the material of the anti-reflection layer 410a may be the same as or different from the material of the anti-reflection layer 410b. According to some embodiments, the optical substrate 10B may be formed by a chemical vapor deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, other suitable processes, or a combination thereof, other suitable materials or the combination thereof, but not limited thereto. Here, the optical substrate 10B is substantially completed.

[0125] Please refer to Figure 3 , Figure 3 The cross-sectional structure diagram of the sensing substrate 10A and the optical substrate 10B of the sensing device according to some embodiments of the present disclosure is shown. Figure 3 A schematic diagram showing the sensing substrate 10A and the optical substrate 10B before being joined together. Figure 3 As shown, the first bonding layer BD1 of the sensing substrate 10A can be aligned with the second bonding layer BD2 of the optical substrate 10B. Further, the first metal layer 304 of the first bonding layer BD1 can be aligned with the second metal layer 404 of the second bonding layer BD2 so that the sensing unit 200 is opposite to the groove RS.

[0126] Please refer to Figure 4 , Figure 4 The cross-sectional structure diagram of the sensing device 1 according to some embodiments of the present disclosure is shown. In detail, Figure 4 A schematic diagram showing the sensing substrate 10A and the optical substrate 10B after being bonded together. According to some embodiments, the first bonding layer BD1 and the second bonding layer BD2 may be melted by a bonding process to bond the sensing substrate 10A and the optical substrate 10B to each other. The first metal layer 304 of the first bonding layer BD1 and the second metal layer 404 of the second bonding layer BD2 are melted to form a bonding structure 500. According to some embodiments, the bonding structure 500 may include Cu 3 Sn、Au 5 Sn, gold (Au), other suitable materials or combinations thereof, but not limited thereto. The bonding process includes heating, pressurizing, irradiating light or combinations thereof. According to some embodiments, the temperature of the bonding process may be between 100°C and 500°C, or between 150°C and 400°C, or between 200°C and 300°C.

[0127] like Figure 4 As shown, the formed sensing device 1 may include a sensing substrate 10A and an optical substrate 10B. The sensing substrate 10A may include a first substrate 100, a circuit layer 100C, a planarization layer 110, a sensing unit 200 and a first bonding layer BD1. The circuit layer 100C may be disposed on the first substrate 100. The planarization layer 110 may be disposed on the circuit layer 100C, and the planarization layer 110 may include an opening 110P. The sensing unit 200 may be disposed on the planarization layer 110, and the sensing unit 200 may be electrically connected to the circuit layer 100C through the opening 110P. The first bonding layer BD1 may be disposed on the planarization layer 110.

[0128] The optical substrate 10B may include a second substrate 400 and a second bonding layer BD2 disposed on the second substrate 400. According to some embodiments, the optical substrate 10B may include an anti-reflection layer 410a and an anti-reflection layer 410b, and the anti-reflection layer 410a and the anti-reflection layer 410b may be disposed on the surface of the second substrate 400. Furthermore, the optical substrate 10B may have a groove RS, and the groove RS may overlap with the sensing unit 200. In detail, the groove RS may overlap with the sensing unit 200 in the normal direction of the second substrate 400 (for example, the Z direction in the drawing).

[0129] Furthermore, the optical substrate 10B and the sensing substrate 10A may be bonded to each other via the first bonding layer BD1 and the second bonding layer BD2. According to some embodiments, the first bonding layer BD1 and the second bonding layer BD2 may be melt-reacted to form a bonding structure 500, and the bonding structure 500 may include Cu 3 Sn、Au 5 Sn, gold (Au), other suitable materials or a combination thereof, but not limited thereto. In detail, the first metal layer 304 of the first bonding layer BD1 and the second metal layer 404 of the second bonding layer BD2 can form a bonding structure 500 through a melt reaction. Furthermore, according to some embodiments, the first bonding layer BD1 and the second bonding layer BD2 are bonded to each other to form a cavity CV in the sensing device 1. Based on the above, the configuration of the sensing substrate 10A can improve the tightness during bonding, enhance the packaging vacuum tightness of the sensing device 1, and thereby improve the sensing sensitivity of the sensing device 1 or enhance the overall performance of the sensing device 1.

[0130] Please refer to Figure 5 , Figure 5 The equivalent circuit diagram of the sensing device 1 according to some embodiments of the present disclosure is shown. Figure 5 As shown, the sensing device 1 may have a sensing array, the sensing array may have a plurality of sensing pixels PX, and the bonding structure 500 may be disposed around the sensing array. According to some embodiments, the sensing pixel PX may include a thin film transistor TR as a driving component and a sensing unit 200, the thin film transistor TR may be electrically connected to the scan line SL, the data line DL and the sensing unit 200, respectively, and one end of the sensing unit 200 is electrically connected to the thin film transistor TR, and the other end is electrically connected to the bias signal line BL. According to some embodiments, the scan line SL may be electrically connected to the scan line driving component (row driver) 11. Furthermore, according to some embodiments, the data line DL may be electrically connected to the readout driving component (readout driver) 13. The scan line driving component 11 may be further electrically connected to the integrated circuit (IC) component 15, and the readout driving component 13 may be further electrically connected to the integrated circuit (IC) component 15, and the sensing signal is read by the integrated circuit component 15.

[0131] To summarize, according to the embodiments of the present disclosure, the provided sensing substrate can provide a relatively flat structural surface, which can improve the tightness when joined with the optical substrate, thereby improving the packaging vacuum tightness of the sensing device, improving the sensing sensitivity of the sensing device, or improving the overall performance of the sensing device.

[0132] Although the embodiments and advantages of the present disclosure have been disclosed as above, it should be understood that any person skilled in the art can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. The features between the embodiments of the present disclosure can be mixed and matched as needed as long as they do not violate the spirit of the invention or conflict with each other. In addition, the scope of protection of the present disclosure is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person skilled in the art can understand the current or future developed processes, machines, manufacturing, material compositions, devices, methods and steps from the disclosure of the present disclosure, as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein, they can all be used according to the present disclosure. Therefore, the scope of protection of the present disclosure includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps. The scope of protection of the present disclosure shall be subject to the scope of the appended claims. Any embodiment or claim of the present disclosure does not need to achieve all the purposes, advantages and features disclosed in this disclosure.

Claims

1. A sensing substrate, characterized in that: include: a first substrate; A circuit layer is disposed on the first substrate; a planarization layer disposed on the circuit layer, and the planarization layer includes an opening; a sensing unit disposed on the planarization layer, and the sensing unit is electrically connected to the circuit layer through the opening; and A first bonding layer is disposed on the planarization layer.

2. The sensing substrate according to claim 1, wherein: The sensing unit and the first bonding layer are located on the same side of the planarization layer.

3. The sensing substrate according to claim 1, wherein: The sensing unit comprises: an absorbent layer; A first insulating layer and a second insulating layer are disposed on the absorption layer; and A sensing layer is disposed between the first insulating layer and the second insulating layer.

4. The sensing substrate according to claim 3, wherein: The sensing unit further includes a supporting component, and the supporting component is arranged between the planarization layer and the absorption layer.

5. The sensing substrate according to claim 4, wherein: The sensing unit further includes a fixing component, and the fixing component is disposed in an opening of the supporting component.

6. The sensing substrate according to claim 1, wherein: The first bonding layer surrounds the sensing unit.

7. The sensing substrate according to claim 1, wherein: The first bonding layer includes a first seed layer and a first metal layer disposed on the first seed layer.

8. The sensing substrate according to claim 7, wherein: The first seed layer includes a molybdenum / copper composite layer, a titanium / copper composite layer, a molybdenum / aluminum composite layer or a titanium / aluminum composite layer.

9. The sensing substrate according to claim 7, wherein: The first metal layer includes a tin / copper composite layer, a tin / gold / nickel / copper composite layer, a tin / gold / nickel composite layer, a gold / nickel composite layer or a gold / nickel / copper composite layer.

10. A sensing device, characterized in that: include: A sensing substrate, comprising: a first substrate; A circuit layer is disposed on the first substrate; a planarization layer disposed on the circuit layer, and the planarization layer includes an opening; a sensing unit disposed on the planarization layer, and the sensing unit is electrically connected to the circuit layer through the opening; and a first bonding layer disposed on the planarization layer; and An optical substrate, comprising a second substrate and a second bonding layer disposed on the second substrate; The optical substrate and the sensing substrate are bonded to each other via the first bonding layer and the second bonding layer.

11. The sensing device according to claim 10, characterized in that The first bonding layer and the second bonding layer are reacted by melting to form a bonding structure, and the bonding structure includes Cu3Sn, Au5Sn or gold.

12. The sensing device according to claim 10, characterized in that The optical substrate further comprises an anti-reflection layer, and the reflection layer is arranged on the surface of the second substrate.

13. The sensing device according to claim 10, characterized in that The optical substrate has a groove, and the groove overlaps with the sensing unit.

14. The sensing device according to claim 10, characterized in that The first bonding layer and the second bonding layer are bonded to each other to form a cavity in the sensing device.

15. A method for manufacturing a sensing device, comprising: A sensing substrate is provided, comprising: Providing a first substrate; forming a circuit layer on the first substrate; Forming a planarization layer on the circuit layer, wherein the planarization layer includes a first opening; forming a sensing unit on the planarization layer, and the sensing unit is electrically connected to the circuit layer through the first opening; and A first bonding layer is formed on the planarization layer.

16. The method for manufacturing a sensing device according to claim 15, wherein: The step of forming the sensing unit on the planarization layer includes: forming a first sacrificial layer on the planarization layer; forming a support element on the first sacrificial layer; forming a second sacrificial layer on the support element; forming an absorption layer on the second sacrificial layer; forming a first insulating layer on the absorption layer; forming a sensing layer on the first insulating layer; and A second insulating layer is formed on the sensing layer.

17. The method for manufacturing a sensing device according to claim 16, wherein: The step of forming the sensing unit on the planarization layer further includes removing the first sacrificial layer and the second sacrificial layer, and the step of removing the first sacrificial layer and the second sacrificial layer is performed after the step of forming the first bonding layer on the planarization layer.

18. The method for manufacturing a sensing device according to claim 15, wherein: The step of forming the first bonding layer on the planarization layer comprises: forming a first seed layer on the planarization layer; forming a protective layer on the first seed layer; removing a portion of the protective layer to form a second opening, wherein the second opening exposes the first seed layer; forming a first metal layer in the second opening; and Remove the protective layer.

19. The method for manufacturing a sensing device according to claim 15, wherein: Also includes: An optical substrate is provided, comprising: providing a second substrate; and A second bonding layer is formed on the second substrate.

20. The method for manufacturing a sensing device according to claim 19, wherein: The method further comprises melting the first bonding layer and the second bonding layer through a bonding process so as to bond the sensing substrate and the optical substrate to each other.

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