Selective deposition of dielectrics on dielectrics using aniline passivation

Abstract

A method includes forming a conductive material on a first dielectric layer, exposing the conductive material to aniline to create a passivated surface of the conductive material, and forming a second dielectric layer on the first dielectric layer using a deposition process after exposing the conductive material to aniline. The deposition process is a water-free and plasma-free deposition process, and the second dielectric layer is not formed on the passivated surface of the conductive material.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to electronic device fabrication. Specifically, embodiments of the present disclosure relate to dielectric-on-dielectric (DoD) selective deposition using aniline passivation. Background Art

[0002] An electronic device manufacturing facility may include multiple chambers, such as a processing chamber and a load lock chamber. Such an electronic device manufacturing facility may use a robotic device in a transfer chamber that is configured to transport substrates between the multiple chambers. In some cases, multiple substrates are transferred together. A processing chamber may be used in an electronic device manufacturing facility to perform one or more processes on a substrate, such as a deposition process and an etching process. For many processes, a gas flows into the processing chamber.

[0003] Electronic devices, such as semiconductor devices, are manufactured by performing a series of operations (which may include deposition, oxidation, photolithography, ion implantation, etching, etc.) to form a number of patterned layers. Often, it is beneficial to align features between layers. In some cases, poor alignment of features (e.g., due to lithography and / or patterning limitations) may result in shorts and / or capacitive coupling between, for example, vias and underlying metal lines. Such shorts and / or capacitive coupling may impair the functionality of the manufactured electronic device. Summary of the invention

[0004] According to one embodiment, a method is provided. The method includes forming a conductive material on a first dielectric layer, exposing the conductive material to aniline to produce a passivated surface of the conductive material, and after exposing the conductive material to the aniline, forming a second dielectric layer on the first dielectric layer using a deposition process. The deposition process is a water-free and plasma-free deposition process, and the second dielectric layer is not formed on the passivated surface of the conductive material.

[0005] According to one embodiment, a system is provided. The system includes a passivation chamber for exposing a conductive material to aniline to produce a passivated surface of the conductive material. The conductive material is formed on a first dielectric layer disposed on a substrate. The system further includes a deposition chamber for forming a second dielectric layer on the first dielectric layer using a deposition process after exposing the conductive material to the aniline. The deposition process is a water-free and plasma-free deposition process, and the second dielectric layer is not formed on the passivated surface of the conductive material. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In the accompanying drawings, the present disclosure is illustrated by way of example and not limitation, wherein like reference numerals represent similar elements. It should be noted that different references to "a" or "one" embodiment in the present disclosure do not necessarily refer to the same embodiment, and such references mean at least one.

[0007] Figures 1A to 1D A cross-sectional view illustrating an example method of forming a device using aniline passivation to achieve dielectric-on-dielectric (DoD) selective deposition in accordance with some embodiments.

[0008] FIG. 2A to FIG. 2B Flowchart of an example method for achieving dielectric-on-dielectric (DoD) selective deposition using aniline passivation according to some embodiments.

[0009] Figure 3 is a block diagram of an example electronic device processing system that may be used to achieve dielectric-on-dielectric (DoD) selective deposition using aniline passivation in accordance with some embodiments. DETAILED DESCRIPTION

[0010] Embodiments described herein relate to selective deposition of dielectric on dielectric (DoD) using aniline passivation. An electronic device may include a dielectric material and a conductive material. For example, the electronic device may include a dielectric layer and a plurality of conductive lines disposed within the dielectric layer. More specifically, the electronic device may include a plurality of metallization levels, wherein each metallization level includes a respective set of conductive lines, and each pair of metallization levels is separated by a respective dielectric layer (e.g., an interlevel dielectric (ILD) layer). Each conductive line may be formed within a respective trench.

[0011] The electronic device may further include a plurality of vias. A via indicates an electrical connection or contact between wires within the electronic device. Each via may serve as a respective interconnection between at least two metallization levels. For example, a through via is a via that is exposed at both ends of the device (i.e., the through via is formed through each metallization level from the top of the device to the bottom of the device). As another example, a buried via is a via that is not exposed at both ends of the device (i.e., the buried via serves as an interconnection between internal metallization levels). As yet another example, a blind via is a via that is exposed at a single end of the device.

[0012] Electronic device processing techniques may involve performing patterning (e.g., photolithography). For example, patterning may include multiple and repeated deposition and etching processes using light shielding ("shielding") and resist films, such as wet etching or dry etching (e.g., plasma etching). Illustratively, suitable patterning processes may be used to form wires and vias. For example, wires and vias may be formed using a single damascene process, during which wires and vias may be formed sequentially. As another example, wires and vias may be formed using a dual damascene process, during which wires and vias may be formed simultaneously (e.g., by simultaneously filling vias and trenches with conductive materials). Wires and vias may be formed of any suitable conductive material (e.g., metal). Examples of suitable conductive materials that may be used to form wires and vias include copper (Cu), tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), and the like.

[0013] As electronic device dimensions shrink (e.g., as transistor dimensions decrease), process variations occur during lithography / patterning (e.g., nanoscale patterning). An example of process variation is shield misalignment between the shield and the patterned substrate. During exposure to light, shield misalignment can result in edge placement errors that are equal to the distance between the target placement of the feature edge and the actual placement of the feature edge. Edge placement errors can cause detrimental effects that can result in reduced device performance, such as shorts, increased resistance, capacitive coupling, etc.

[0014] Illustratively, during via patterning, shield misalignment may result in via misalignment, where at least one via is patterned to be misaligned relative to a conductor. For example, an aligned via is a via with a substantially correct edge position on a corresponding conductor (e.g., the via is centered relative to the conductor). However, due to shield misalignment during via patterning, an edge placement error relative to the edge of the via may result (e.g., the edge of the via may be formed on a portion of a dielectric layer in an area between its corresponding conductor and another adjacent conductor).

[0015] Via misalignment can result in shorts or capacitive coupling between the via and an adjacent conductor, which may be a function of the horizontal spacing between the via and the adjacent conductor (e.g., the distance between the bottom surface of the via and the top surface of the adjacent conductor). As transistor dimensions become smaller (e.g., at the nanometer (nm) scale), the effects of via misalignment become more significant. Therefore, as transistor dimensions further shrink, it is important to maintain a minimum amount of spacing to prevent shorts or capacitive coupling due to process variations that cause via misalignment.

[0016] One example of a method that can be used to solve the problem of misaligned vias is the wire groove method. During the wire groove method, after the grooves in the dielectric layer are filled with a conductive material (e.g., metal) to form the wires, an etching process can be used to recess the wires to a specific depth in their respective grooves. The vias can then be formed so that the upper surface of each wire is located below the upper surface of the dielectric layer. Therefore, if the via formed on the wire is a misaligned via, the misaligned via may have an edge formed on the dielectric layer that is located a certain distance above the upper surface of the adjacent wire. This will cause the misaligned via and the adjacent wire (e.g., the lower surface of the misaligned via and the upper surface of the adjacent wire) to be separated by a diagonal spacing. The diagonal spacing is a function of the above-mentioned horizontal spacing and also a function of the vertical distance between the misaligned via and the adjacent wire. In other words, the length of the diagonal spacing is greater than the horizontal spacing, thereby helping to prevent short circuits or capacitive coupling. However, the wire groove method has many disadvantages. For example, the wire groove method exhibits poor uniformity, high wire surface roughness, and material degradation across the wafer and at different pitch sizes.

[0017] Another example of a method that can be used to address process variations (such as misaligned vias) is a dielectric-on-dielectric (DoD) method. The DoD method utilizes a selective dielectric material deposition method that can, for example, increase the spacing between a misaligned via and an adjacent conductive line. More specifically, after a trench within a first dielectric layer (e.g., a first ILD) is filled with a conductive material (e.g., a metal) to form a conductive line, a second dielectric layer can be selectively deposited on the exposed surface of the first dielectric layer. The second dielectric layer can be formed to a height that is similar in magnitude to the depth obtained during the above-described groove method. Similar to the groove method, if the via formed on the conductive line is a misaligned via, the misaligned via can have an edge formed on the second dielectric layer that is located a distance above the upper surface of the adjacent conductive line. Similar to the groove method, the DoD method can separate the misaligned via from the adjacent conductive line by a diagonal spacing that is greater than the horizontal spacing, thereby helping to prevent short circuits or capacitive coupling.

[0018] The first dielectric layer may include any suitable dielectric material. In some embodiments, the first dielectric layer may include an oxide. In some embodiments, the first dielectric layer may include a nitride. Examples of suitable dielectric materials that can be used to form the first dielectric layer include silicon dioxide (SiO2), carbon-doped silicon oxide (e.g., SiOC, SiCOH), silicon nitride (Si3N4), etc. The second dielectric layer may include any suitable dielectric material. In some embodiments, the second dielectric layer may include an oxide. Examples of suitable dielectric materials that can be used to form the second dielectric layer include hafnium dioxide (HfO2), titanium dioxide (TiO2), aluminum oxide (Al2O3), SiO2, etc.

[0019] To implement the dielectric layer formation method, a second dielectric layer may be selectively deposited on a first dielectric layer in preference to a conductive material (e.g., copper, tungsten, cobalt, molybdenum, or ruthenium). Selectivity may be defined, for example, as the ratio of film thickness (e.g., thickness of the second dielectric layer) on a target surface (e.g., the first dielectric layer) to film thickness on a non-target surface (e.g., the conductive material). Other definitions of selectivity may be used.

[0020] Some selective deposition processes may employ an atomic layer deposition (ALD) process. Some ALD processes may use water (H2O) as an oxidant. However, ALD processes employing water as an oxidant may not achieve compatibility with embodiments in which the first dielectric layer includes a porous hydrophobic dielectric material (e.g., SiCOH). In addition, some ALD processes use plasma during film deposition (i.e., plasma enhanced ALD processes). However, similar to water, ALD processes employing plasma may not achieve compatibility with embodiments in which the first dielectric layer includes a porous hydrophobic dielectric material (e.g., SiCOH).

[0021] To address these and other shortcomings, the embodiments described herein may use aniline passivation to achieve selective deposition of dielectric on dielectric (DoD). More specifically, the embodiments described herein may enable selective deposition of a dielectric layer on another dielectric layer in preference to a conductive material. For example, a conductive material may form a plurality of wires within a first dielectric layer (e.g., a metallization level). The first dielectric layer may include any suitable dielectric material. In some embodiments, the first dielectric layer may include an oxide. In some embodiments, the first dielectric layer may include a nitride. Examples of suitable dielectric materials that can be used to form the first dielectric layer include SiO2, carbon-doped silicon oxide, such as SiOC, SiCOH, Si3N4, and the like. The conductive material may include any suitable material. In some embodiments, the conductive material includes a transition metal. Examples of suitable conductive materials include copper, tungsten, cobalt, molybdenum, ruthenium, and the like.

[0022] More specifically, performing DoD selective deposition may include passivating a conductive material (e.g., a wire) by exposing the first dielectric layer and the conductive material to aniline (e.g., vapor phase aniline). Aniline is an aromatic molecule that may include an amine functional group (e.g., C6H5NH2) attached to a phenyl group. During the aniline exposure, the aniline exhibits weak or no adsorption to the first dielectric layer, while exhibiting strong adsorption to the surface of the conductive material (e.g., a transition metal). During a subsequent deposition process to form a second dielectric layer, the passivation layer may prevent (e.g., block) a deposition precursor of a subsequent dielectric (e.g., an oxide) from being adsorbed onto the conductive layer (i.e., preventing the deposition precursor from nucleating). Thus, aniline passivation enables selective deposition of the second dielectric layer on the first dielectric layer in preference to the conductive material during a subsequent deposition process (e.g., the second dielectric layer is not deposited on the passivated metal layer).

[0023] For example, for certain conductive materials, aniline can undergo a reaction with the conductive material resulting in dissociation. More specifically, the reaction can result in deprotonation (i.e., loss of an H atom from the aniline compound), which can form a bond (e.g., a phenyl-N-metal bond) on the surface of the conductive material.

[0024] As another example, for some conductive materials (e.g., Ru), aniline can exhibit two favorable adsorption modes in which no bonds are broken within the aniline compound. One adsorption mode is an n-bonding configuration in which the entire aniline compound is bonded through delocalized n electrons. The other adsorption mode is a donor bonding configuration in which the aniline forms a bond with the conductive layer by donating a pair of electrons from N to the conductive material surface (e.g., N-metal bond).

[0025] Any suitable process parameters can be used for passivation. Examples of process parameters for performing passivation include temperature, exposure time, pressure, etc. In some embodiments, aniline is exposed to a temperature of about 100°C to about 350°C. In some embodiments, aniline is exposed to a temperature of about 250°C to about 350°C. At sufficiently high temperatures, aniline passivation degradation may occur (e.g., the temperature exceeds 350°C). Therefore, the passivation process can be performed below the threshold temperature to maintain the aniline passivation quality (e.g., less than or equal to about 350°C). In some embodiments, the pressure ranges from about 500 mTorr to about 10 Torr. In some embodiments, the pressure ranges from about 750 mTorr to about 780 mTorr.

[0026] In some embodiments, the conductive material is exposed to aniline for less than or equal to about 60 minutes. In some embodiments, the conductive material is exposed to aniline for less than or equal to about 50 minutes. In some embodiments, the conductive material is exposed to aniline for less than or equal to about 40 minutes. In some embodiments, the conductive material is exposed to aniline for less than or equal to about 30 minutes. In some embodiments, the conductive material is exposed to aniline for less than or equal to about 20 minutes. In some embodiments, the conductive material is exposed to aniline for less than or equal to about 10 minutes. In some embodiments, the conductive material is exposed to aniline for less than or equal to about 5 minutes. In some embodiments, the conductive material is exposed to aniline for less than or equal to about 1 minute.

[0027] In some embodiments, a cleaning process (i.e., pre-cleaning) may be performed before passivating the conductive material. The pre-cleaning process may be performed as appropriate to increase the selectivity of the second dielectric layer to the first dielectric layer and / or reduce the selectivity of the second dielectric layer to the conductive material. The pre-cleaning process may include surface cleaning to remove native oxides on the surface of the conductive material. The pre-cleaning process may further remove contaminants from the surface of the conductive material. The pre-cleaning process may further reduce defect growth on the conductive material. For example, the pre-cleaning process may include hot ethanol (EtOH) treatment, hydrogen radical treatment, etc.

[0028] Any suitable process parameters may be used for the pre-cleaning process. Examples of process parameters for performing pre-cleaning include time, temperature, pressure, etc. For example, the hot EtOH treatment may be performed at a temperature ranging from about 200° C. to about 300° C. (e.g., about 250° C.) for a time ranging from about 1 minute to about 30 minutes (e.g., about 5 minutes). In some embodiments, the pressure ranges from about 100 mTorr to about 10 Torr. In some embodiments, the pressure ranges from about 500 mTorr to about 10 Torr. In some embodiments, the pressure ranges from about 1 Torr to about 10 Torr.

[0029] After passivation (and optional pre-cleaning before passivation), a second dielectric layer can be selectively formed on the exposed surface of the first dielectric layer using a deposition process. The second dielectric layer may include any suitable dielectric material. In some embodiments, the second dielectric layer may include an oxide. For example, the second dielectric layer may include a metal oxide. Examples of suitable dielectric materials that can be used to form the second dielectric layer include hafnium dioxide (HfO2), titanium dioxide (TiO2), aluminum oxide (Al2O3), SiO2, etc. In some embodiments, the second dielectric layer includes a nano-laminate to ensure an amorphous structure. The second dielectric layer can be deposited on the first dielectric layer to a target thickness (e.g., by performing an appropriate number of deposition cycles). As described above, the passivation layer formed during aniline passivation can prevent (e.g., block) adsorption of deposition precursors on the conductive material. Therefore, aniline passivation can prevent (e.g., inhibit) the formation of a second dielectric layer on the conductive material. Therefore, due to aniline passivation, a dielectric layer of negligible thickness (e.g., less than about 1 nanometer thick) can be deposited on the conductive material during the deposition process.

[0030] The deposition process may be a water-free and plasma-free deposition process. For example, water and / or plasma may cause desorption of the adsorbed passivation layer. Therefore, the aniline may be exposed to the conductive material once before the deposition process (i.e., it may not be necessary to expose the conductive material to the aniline multiple times). In addition, because the deposition process is water-free, the first dielectric layer may be formed of a porous hydrophobic dielectric (e.g., SiCOH).

[0031] In some embodiments, the deposition process is a chemical vapor deposition (CVD) process. For example, the CVD process may be a pulsed CVD process. During the pulsed CVD process, the material may be formed by performing alternating deposition precursor pulses and purge gas pulses. The purge gas may be any suitable inert gas. For example, the purge gas may be argon (Ar), nitrogen (N2), etc.

[0032] The deposition process may utilize any suitable deposition precursor and any suitable process parameters. In some embodiments, the deposition process utilizes a deposition precursor to form a metal oxide (e.g., a metal alkoxide precursor). Examples of deposition precursors include hafnium tert-butoxide (Hf(OtBu)4) to form HfO2, titanium isopropoxide (Ti(O2)4) to form TiO2, and titanium tert-butoxide (Hf(O2)4) to form TiO2. i Pr)4), forming aluminum isopropoxide (Al(O iThe process parameters of the deposition process (e.g., CVD process) may depend on the deposition precursor used to form the second dielectric layer and the target thickness of the resulting second dielectric layer.

[0033] Examples of process parameters for performing a pulsed CVD process include temperature, number of deposition precursor pulses, pulse length (i.e., duration of a deposition precursor pulse), purge length (i.e., duration of a purge pulse between deposition precursor pulses), pressure deposition precursor vapor pressure, purge gas pressure, etc. In some embodiments, the pulsed CVD process may be performed at a temperature range of about 100°C to about 400°C. In some embodiments, the pulsed CVD process may be performed at a temperature range of about 300°C to about 350°C. In some embodiments, the number of deposition precursor pulses ranges from about 1 pulse to about 1000 pulses. In some embodiments, the number of deposition precursor pulses ranges from about 4 pulses to about 500 pulses. In some embodiments, the number of deposition precursor pulses ranges from about 50 pulses to about 250 pulses. In some embodiments, the pulse length ranges from about 0.1 seconds to about 4 seconds. In some embodiments, the purge length ranges from about 0.1 seconds to about 10 seconds.

[0034] The following will refer to Figures 1A to 1D , further details of forming a device using aniline passivation to achieve DoD selective deposition are described.

[0035] Figures 1A to 1D FIG. 1 is a cross-sectional view illustrating an exemplary method of forming device 100 using aniline passivation to achieve dielectric-on-dielectric selective deposition in accordance with some embodiments. Figure 1A As shown, a dielectric layer 110-1 may be provided, and a plurality of conductive lines including conductive lines 120-1 and 120-2 may be formed in the dielectric layer 110-1. More specifically, the dielectric layer 110-1 may be an interlevel dielectric (ILD) layer, and the conductive lines 120-1 and 120-2 may correspond to a first metallization level in the device 100. Forming the plurality of conductive lines may include forming a plurality of grooves in the dielectric layer 110-1 using an etching process, and forming a conductive material in the plurality of grooves to form the plurality of conductive lines. More specifically, each groove corresponds to a respective conductive line. In an embodiment, the dielectric layer 110-1 and the conductive lines 120-1 and 120-2 may be included in a base structure on a substrate (e.g., a semiconductor wafer).

[0036] Although not shown, the base structure may include one or more additional layers, such that the dielectric layer 110-1 and the plurality of conductive lines are disposed on the one or more additional layers. For example, the device 100 may further include at least one substrate layer (e.g., a silicon (Si) substrate) (not shown) as an initial layer of the device.

[0037] The dielectric layer 110-1 may include any suitable dielectric material. In some embodiments, the dielectric layer 110-1 may include an oxide (e.g., a metal oxide). In some embodiments, the dielectric layer 110-1 may include a nitride (e.g., a metal nitride). Examples of suitable dielectric materials include SiO2, carbon-doped silicon oxide (e.g., SiOC, SiCOH), Si3N4, etc. The wires 120-1 and 120-2 may be formed of any suitable conductive material (e.g., a metal). In some embodiments, the wires 120-1 and 120-2 are formed of a conductive material including a transition metal. Examples of suitable conductive materials that can be used to form the wires 120-1 and 120-2 include copper, tungsten, cobalt, molybdenum, ruthenium, etc.

[0038] like Figure 1B As shown, dielectric layer 130 is selectively deposited on dielectric layer 110-1. For example, a CVD process may be used for deposition. Other deposition processes may also be performed to produce dielectric layer 130. Dielectric layer 130 may include any suitable dielectric material. In some embodiments, dielectric layer 130 may include an oxide. For example, dielectric layer 130 may include a metal oxide. Examples of suitable dielectric materials that can be used to form the second dielectric layer include HfO2, TiO2, Al2O3, SiO2, etc.

[0039] More specifically, selectively depositing dielectric layer 130 includes performing a passivation process by exposing dielectric layer 110-1 and wires 120-1 and 120-2 to aniline (eg, vapor phase aniline). Exposure of wires 120-1 and 120-2 to aniline may produce a passivated surface on surfaces of wires 120-1 and 120-2.

[0040] More specifically, aniline reacts with the wires 120-1 and 120-2 to form a passivation layer adsorbed to the surfaces of the wires 120-1 and 120-2. The passivation layer may include byproducts of the reaction of aniline adsorbed to the surfaces of the wires 120-1 and 120-2. The passivation layer may prevent (e.g., inhibit) the growth of the dielectric layer 130 on the wires 120-1 and 120-2 by preventing (e.g., blocking) the adsorption of deposition precursors during the deposition of the dielectric layer 130. In some embodiments, the passivation layer has a single layer thickness.

[0041] The passivation process may be performed using any suitable process parameters. For example, the passivation process may be a hot aniline exposure. In some embodiments, the passivation process is performed once to form a single passivation layer. Examples of process parameters for performing the passivation process include temperature, exposure time, pressure, and the like. In some embodiments, the aniline exposure is performed in a temperature range of about 100° C. to about 400° C. In some embodiments, the aniline exposure is performed in a temperature range of about 250° C. to about 350° C. In some embodiments, the pressure ranges from about 500 mTorr to about 10 Torr. In some embodiments, the pressure ranges from about 750 mTorr to about 780 mTorr.

[0042] In some embodiments, the amount of time that wires 120-1 and 120-2 are exposed to aniline is less than or equal to about 60 minutes. In some embodiments, the amount of time that wires 120-1 and 120-2 are exposed to aniline is less than or equal to about 50 minutes. In some embodiments, the amount of time that wires 120-1 and 120-2 are exposed to aniline is less than or equal to about 40 minutes. In some embodiments, the amount of time that wires 120-1 and 120-2 are exposed to aniline is less than or equal to about 30 minutes. In some embodiments, the amount of time that wires 120-1 and 120-2 are exposed to aniline is less than or equal to about 20 minutes. In some embodiments, the amount of time that wires 120-1 and 120-2 are exposed to aniline is less than or equal to about 10 minutes. In some embodiments, the amount of time that wires 120-1 and 120-2 are exposed to aniline is less than or equal to about 5 minutes. In some embodiments, the amount of time that wires 120-1 and 120-2 are exposed to aniline is less than or equal to about 1 minute.

[0043] In some embodiments, a pre-cleaning process may be performed before passivating the wires 120-1 and 120-2. The pre-cleaning process may increase the selectivity of the dielectric layer 130 to the dielectric layer 110-1 and / or reduce the selectivity of the dielectric layer 130 to the wires 120-1 and 120-2. The pre-cleaning process may include surface cleaning to remove natural oxides on the surfaces of the wires 120-1 and 120-2. The pre-cleaning process may further remove contaminants from the surfaces of the wires 120-1 and 120-2. The pre-cleaning process may further reduce defect growth on the wires 120-1 and 120-2. For example, the pre-cleaning process may include hot EtOH treatment, hydrogen radical treatment, etc. Illustratively, the pre-cleaning process may include continuous EtOH dosing for a time ranging from about 4 minutes to about 5 minutes (e.g., about 5 minutes) at a temperature ranging from about 200° C. to about 300° C. (e.g., about 250° C.) before passivation. In some embodiments, the pressure ranges from about 100 mTorr to about 10 Torr. In some embodiments, the pressure ranges from about 500 mTorr to about 10 Torr. In some embodiments, the pressure ranges from about 1 Torr to about 10 Torr.

[0044] After passivation (and optional pre-cleaning before passivation), a deposition process can be used to form the dielectric layer 130. More specifically, the dielectric layer 130 can be selectively deposited on the exposed surface of the dielectric layer 110. The deposition process can be a waterless deposition process and a plasma-free deposition process. In some embodiments, the deposition process is a CVD process. For example, the CVD process can be a pulsed CVD process. Other deposition processes can also be used. Due to the aniline passivation, a dielectric layer of negligible thickness (e.g., less than about 1 nanometer thick) can be deposited on the conductive material during the deposition process. This thin dielectric layer can be removed during further processing (e.g., during a subsequent metal deposition process and / or cleaning process).

[0045] The deposition process may utilize any suitable deposition precursor and any suitable process parameters. In some embodiments, the deposition process utilizes a deposition precursor to form a metal oxide (e.g., a metal alkoxide precursor). Examples of deposition precursors include hafnium tert-butoxide to form HfO2, titanium isopropoxide to form TiO2, aluminum isopropoxide to form Al2O3, aluminum tri-sec-butoxide to form Al2O3, TEOS to form SiO2, TBOS to form SiO2, TMOS to form SiO2, etc. The process parameters of the deposition process (e.g., a CVD process) may depend on the deposition precursor used to form the second dielectric layer and the target thickness of the resulting second dielectric layer.

[0046] Examples of process parameters for performing a pulsed CVD process include temperature, number of pulses, pulse length (i.e., length of time during which a pulse deposits a precursor), purge length (i.e., length of time during which a purge gas (e.g., argon or N2) is introduced between pulses), deposition precursor vapor pressure, purge gas pressure, etc. For example, a pulsed CVD process may be performed at a temperature in the range of about 100°C to about 400°C. As another example, a pulse length may be in the range of about 0.1 seconds to about 4 seconds. As yet another example, a purge length may be in the range of about 0.1 seconds to about 10 seconds. More details about the deposition process will be described below with respect to FIG. 2A to FIG. 2B Give a description.

[0047] After forming the dielectric layer 130, an optional post-cleaning process may be performed. Performing the post-cleaning process may include removing the passivation layer and / or the thin dielectric layer from the surface of the conductive material. For example, performing the post-cleaning process may include heating the device to a temperature greater than or equal to 350°C. Heating the device to a temperature greater than or equal to 350°C may cause desorption of the passivation layer. As another example, performing the post-cleaning process may further include removing defects (e.g., portions of the dielectric material that may have been formed on the conductive material during the deposition process). As another example, the post-cleaning process may be a plasma cleaning process. As yet another example, the post-cleaning process may be a remote plasma cleaning process.

[0048] like Figure 1CAs shown, after selectively depositing dielectric layer 130 on dielectric layer 110-1, dielectric layer 110-2 may be formed on multiple conductive lines and dielectric layer 130. More specifically, dielectric layer 110-2 may be a second ILD layer. Dielectric layer 110-2 may include any suitable dielectric material. In some embodiments, dielectric layer 110-2 may include an oxide. In some embodiments, dielectric layer 110-2 may include a nitride. Examples of suitable dielectric materials include SiO2, carbon-doped silicon oxide (e.g., SiOC, SiCOH), Si3N4, etc. In some embodiments, dielectric layer 110-2 includes the same dielectric material as dielectric layer 110-1. In some embodiments, dielectric layer 110-2 includes a dielectric material different from dielectric layer 110-1.

[0049] As shown in FIG. 1D , at least one via 140 is formed. More specifically, via 140 may be formed to contact at least conductive line 120-2. As further shown in this illustrative example, at least one conductive line 150 is formed. More specifically, conductive line 150 may correspond to a second metallization level different from the first metallization level (i.e., at least one metallization level higher than the first metallization level).

[0050] Forming the via 140 and the conductive line 150 may include forming a trench in the dielectric layer 110-2, forming a via in the dielectric layer 110-2, and forming a conductive material in the trench and the via. In some embodiments, the via 140 and the conductive line 150 are formed simultaneously (e.g., using a dual damascene process). In some embodiments, the via 140 and the conductive line 150 are formed sequentially (e.g., using a single damascene process).

[0051] Via 140 and wire 150 may include any suitable conductive material (e.g., metal). In some embodiments, via 140 and wire 150 are formed of a conductive material including a transition metal. Examples of suitable conductive materials that can be used to form via 140 and wire 150 include copper, tungsten, cobalt, molybdenum, ruthenium, etc. In some embodiments, via 140 and wire 150 may include the same material as wires 120-1 and 120-2. In some embodiments, via 140 and wire 150 may include a different material than wires 120-1 and 120-2.

[0052] As shown in FIG. 1D , the via 140 in this example is a misaligned via, the edge of which is located on the dielectric layer 130 between the conductors 120-1 and 120-2. In FIG. 1D , the distance between the via 140 and the conductor 120-1 is represented by the diagonal line “D”. The diagonal line D has a longer length than the horizontal line, which would have represented the spacing between the via 140 and the conductor 120-1 without the dielectric layer 130. Therefore, the formation of the dielectric layer 130 can improve the performance of the device 100 by reducing the short circuit or capacitive coupling between the via 140 and the conductor 120-1. FIG. 2A to FIG. 2B Further details regarding forming device 100 are described.

[0053] Figure 2A An example method 200 for achieving DoD selective deposition using aniline passivation according to some embodiments is depicted. The method 200 may be performed in an electronic device processing system. More specifically, the method 200 may be performed in one or more processing chambers of the electronic device processing system. Figure 3 Further details regarding the electronic device processing system are described.

[0054] In step 210, a first conductive material is formed on a first dielectric layer. For example, a first dielectric layer may be provided, and the first conductive material may be formed on the first dielectric layer. In some embodiments, forming the first conductive material includes forming a plurality of conductive lines within the first dielectric layer. More specifically, the first dielectric layer may be an ILD layer, and the plurality of conductive lines may correspond to a first metallization level within the device. Forming the plurality of conductive lines may include forming a plurality of trenches within the first dielectric layer using an etching process, and forming a conductive material within the plurality of trenches to form the plurality of conductive lines. More specifically, each trench corresponds to a respective conductive line.

[0055] The first dielectric layer and the conductive material (e.g., a plurality of conductive lines) may be included in the base structure. The base structure may include one or more additional layers, such that the first dielectric layer and the conductive material are disposed on the one or more additional layers. For example, the device may further include at least one substrate layer (e.g., a silicon (Si) substrate) as an initial layer of the device.

[0056] The first dielectric layer may include any suitable dielectric material. In some embodiments, the first dielectric layer may include an oxide. In some embodiments, the first dielectric layer may include a nitride. Examples of suitable dielectric materials that can be used to form the first dielectric layer include SiO2, carbon-doped silicon oxide (e.g., SiOC, SiCOH), Si3N4, etc. The conductive material may include any suitable conductive material (e.g., a metal). In some embodiments, the conductive material includes a transition metal. Examples of suitable conductive materials include copper, tungsten, cobalt, molybdenum, ruthenium, etc.

[0057] In step 220, a second dielectric layer is selectively deposited on the first dielectric layer using a deposition process. The second dielectric layer may include any suitable dielectric material. In some embodiments, the second dielectric layer may include an oxide. For example, the second dielectric layer may include a metal oxide. Examples of suitable dielectric materials that can be used to form the second dielectric layer include HfO2, TiO2, Al2O3, SiO2, etc. More specifically, selectively depositing the second dielectric layer may include passivating the conductive material (e.g., the plurality of wires) with aniline. Figure 2B Further details regarding the selective deposition of the second dielectric layer are described.

[0058] Figure 2B An example method 220 of selectively depositing a second dielectric layer on a first dielectric layer using aniline passivation is depicted in accordance with some embodiments. The method 220 may be performed in an electronic device processing system. More specifically, the method 220 may be performed in one or more processing chambers of the electronic device processing system.

[0059] In step 222, a pre-cleaning process is performed as appropriate. More specifically, a substrate structure including a conductive material formed on a first dielectric layer (e.g., a plurality of wires disposed within the first dielectric layer) may be cleaned. The pre-cleaning process may improve the selectivity of a second dielectric layer to be formed on the first dielectric layer and / or reduce the selectivity of a second dielectric layer to be formed on the conductive material. The pre-cleaning process may include surface cleaning to remove native oxides on the surface of the conductive material. The pre-cleaning process may further remove contaminants from the surface of the conductive material. The pre-cleaning process may further reduce defect growth on the conductive material. For example, the pre-cleaning may include a hot EtOH treatment, a hydrogen radical treatment, and the like. Illustratively, the pre-cleaning process may include, prior to passivation, continuous EtOH dosing at a temperature ranging from about 200° C. to about 300° C. (e.g., about 250° C.) for a time ranging from about 4 minutes to about 6 minutes (e.g., about 5 minutes). In some embodiments, the pressure ranges from about 100 mTorr to about 10 Torr. In some embodiments, the pressure ranges from about 500 mTorr to about 10 Torr. In some embodiments, the pressure ranges from about 1 Torr to about 10 Torr.

[0060] In step 224, the first conductive material is exposed to aniline. In some embodiments, the aniline includes vapor phase aniline. More specifically, the first conductive material (and the first dielectric layer) may be exposed to aniline to produce a passivated surface of the conductive material. Aniline may react strongly with the first conductive material to form a passivation layer adsorbed to the surface of the conductive material and prevent (e.g., inhibit) the growth of the second dielectric layer on the conductive material. More specifically, the passivation layer may prevent (e.g., block) the deposition precursor from being adsorbed on the surface of the first conductive material, which surface is used to form the second dielectric layer in a subsequent deposition process. In some embodiments, the first conductive material is exposed to aniline during a single passivation process to form a single passivation layer. In some embodiments, the passivation layer has a monolayer thickness. However, according to the embodiments described herein, the passivation layer may have any suitable thickness.

[0061] The aniline exposure can be performed at a suitable temperature. For example, the aniline exposure can be performed at a temperature of about 100° C. to about 400° C. The aniline exposure can be performed for any suitable amount of time. In some embodiments, the amount of time the conductive material is exposed to aniline ranges from about 30 minutes to about 60 minutes. For example, the conductive material can be exposed to aniline for about 40 minutes.

[0062] In step 226, a second dielectric layer is formed using a deposition process. More specifically, the second dielectric layer may be selectively deposited on the exposed surface of the first dielectric layer. As described above, the passivation layer formed on the conductive material prevents (e.g., blocks) the adsorption of the deposition precursor used during the deposition process, thereby preventing the second dielectric layer from being formed. The deposition process may be an anhydrous deposition process and a plasma-free deposition process. In some embodiments, the deposition process is a CVD process. For example, the CVD process may be a pulsed CVD process. During the deposition process, due to aniline passivation, a dielectric layer of negligible thickness (e.g., less than about 1 nanometer thick) may be deposited on the conductive material.

[0063] The deposition process may utilize any suitable deposition precursor and any suitable process parameters. In some embodiments, the deposition process utilizes a deposition precursor to form a metal oxide (e.g., a metal alkoxide precursor). Examples of deposition precursors include hafnium tert-butoxide to form HfO2, titanium isopropoxide to form TiO2, aluminum isopropoxide to form Al2O3, aluminum tri-sec-butoxide to form Al2O3, TEOS to form SiO2, TBOS to form SiO2, TMOS to form SiO2, etc. The process parameters of the deposition process (e.g., a CVD process) may depend on the deposition precursor used to form the second dielectric layer and the target thickness of the resulting second dielectric layer.

[0064] Examples of process parameters for performing a pulsed CVD process include temperature, number of deposition precursor pulses, pulse length (i.e., length of time of a deposition precursor pulse), purge length (i.e., length of time of a purge pulse between deposition precursor pulses), pressure deposition precursor vapor pressure, purge gas pressure, etc. In some embodiments, the pulsed CVD process may be performed at a temperature range of about 100° C. to about 400° C. In some embodiments, the pulsed CVD process may be performed at a temperature range of about 300° C. to about 350° C. In some embodiments, the number of deposition precursor pulses ranges from about 1 pulse to about 1000 pulses. In some embodiments, the number of deposition precursor pulses ranges from about 4 pulses to about 500 pulses. In some embodiments, the number of deposition precursor pulses ranges from about 50 pulses to about 250 pulses. In some embodiments, the pulse length ranges from about 0.1 seconds to about 4 seconds. In some embodiments, the purge length ranges from about 0.1 seconds to about 10 seconds.

[0065] As an illustrative example, assume that the first dielectric layer includes SiO2 and the conductive material has been passivated by aniline exposure as described above. It is further assumed that the second dielectric layer includes HfO2. HfO2 can be deposited on SiO2 using a hafnium tert-butoxide precursor using a pulsed CVD process at a temperature range of about 250°C to about 350°C (e.g., about 300°C). The vapor pressure of the hafnium tert-butoxide precursor can be between about 0.1 mTorr and about 0.5 mTorr (e.g., about 0.3 mTorr). There can be a time interval of about 60 seconds between each pulse of the hafnium tert-butoxide precursor. During each purge pulse between the hafnium tert-butoxide precursor pulses, a purge gas (e.g., Ar or N2) having a pressure of about 120 mTorr can be used. After about 60 pulses of the hafnium tert-butoxide precursor, about 5 nanometers of HfO2 can be deposited on SiO2.

[0066] As another illustrative example, assume that the first dielectric layer includes SiO2 and the conductive material has been passivated by aniline exposure as described above. Further assume that the second dielectric layer includes Al2O3. A pulsed CVD process can be used to deposit Al2O3 on SiO2 using a tri-sec-butoxide aluminum precursor in a temperature range of about 300°C to about 375°C (e.g., about 330°C). The vapor pressure of the tri-sec-butoxide aluminum precursor can be between about 0.1 mTorr and about 0.5 mTorr (e.g., about 0.3 mTorr). There can be a time interval of about 60 seconds between each pulse of the tri-sec-butoxide aluminum precursor. During each purge pulse between the tri-sec-butoxide aluminum precursor pulses, a purge gas (e.g., Ar or N2) having a pressure of about 120 mTorr can be used. After about 200 pulses of the tri-sec-butoxide aluminum precursor, about 5 nanometers of Al2O3 can be deposited on SiO2.

[0067] In step 228, an optional post-cleaning process may be performed. More specifically, the post-cleaning process may be performed after forming the second dielectric layer. Performing the post-cleaning process may include removing the passivation layer from the surface of the conductive material. For example, performing the post-cleaning process may include heating the device to a temperature greater than or equal to 350° C. As another example, performing the post-cleaning process may further include removing defects (e.g., portions of the dielectric material that may have been formed on the conductive material during the deposition process). As another example, the post-cleaning process may be a plasma cleaning process. As yet another example, the post-cleaning process may be a remote plasma cleaning process.

[0068] Reference again Figure 2A In step 230, a third dielectric layer is formed on the second dielectric layer and the conductive material. For example, the third dielectric layer may be a second ILD layer. The third dielectric layer may include any suitable dielectric material. In some embodiments, the third dielectric layer may include an oxide. In some embodiments, the third dielectric layer may include a nitride. Examples of suitable dielectric materials that can be used to form the third dielectric layer include SiO2, carbon-doped silicon oxide (e.g., SiOC, SiCOH), Si3N4, etc. In some embodiments, the third dielectric layer includes the same dielectric material as the first dielectric layer (i.e., the first ILD layer). In some embodiments, the third dielectric layer includes a dielectric material different from the first dielectric layer.

[0069] In step 240, a second conductive material is formed on the third dielectric layer. In some embodiments, forming the second conductive material includes forming a via in the third dielectric layer. For example, a first end of the via may contact at least a portion of a first conductive line in the plurality of conductive lines. In some embodiments, forming the second conductive material further includes forming a second conductive line. More specifically, the second conductive line may be disposed at a second end of the via. The second conductive line may correspond to a second metallization level different from the first metallization level (i.e., at least one metallization level higher than the first metallization level).

[0070] Forming the via and the second conductive line may include forming a trench in the third dielectric layer, forming the via in the third dielectric layer, and forming a conductive material in the trench and the via. In some embodiments, the via and the second conductive line may be formed simultaneously (e.g., using a dual damascene process). In some embodiments, the via and the second conductive line may be formed sequentially (e.g., using a single damascene process).

[0071] The second conductive material may include any suitable conductive material (e.g., a metal). Examples of suitable conductive materials for the second conductive material include copper, tungsten, cobalt, molybdenum, ruthenium, etc. In some embodiments, the first conductive material includes the same material as the second conductive material. In some embodiments, the first conductive material includes a different material than the second conductive material. Figure 1AFurther details regarding steps 210 to 240 are described in detail in FIG. 1D .

[0072] Figure 3 3 is a block diagram of an example electronic device processing system ("system") 300 that can be used to form a device using CVD to implement DoD selective deposition according to some embodiments. For example, system 300 can be used to form the above-referenced Figure 1A The device 100 described in FIG. ID and the above referenced FIG. 2A to FIG. 2B Method 200 is described.

[0073] As shown, the system 300 includes a passivation chamber 310, a transfer chamber 320, and a deposition chamber 330. An interface 340-1 may be disposed between the passivation chamber 310 and the transfer chamber 320, and an interface 340-2 may be disposed between the transfer chamber and the deposition chamber 330. In some embodiments, the interfaces 340-1 and 340-2 are respective gate valves. The transfer chamber 320 may include a transfer robot (not shown). The transfer chamber 320, the passivation chamber 310, and the deposition chamber 330 may each maintain a vacuum under controlled conditions (e.g., little or no humidity). Although not shown, the system 300 may further include at least one load lock chamber and at least one factory interface to enable a substrate to be moved from the atmosphere to the transfer chamber 320. Thus, the substrate may be transferred between chambers without breaking the vacuum, and thus the substrate is not exposed to air and / or moisture.

[0074] The passivation chamber 310 may receive a substrate including a first dielectric layer and a conductive material, and passivate the conductive material by exposing the conductive material to aniline. For example, the aniline may include gaseous aniline. The passivation chamber 310 may be operably coupled to at least one passivation gas storage device 312. For example, at least one passivation gas storage device 312 may include an aniline storage device. At least one passivation gas storage device 312 may further include a purge gas storage device. The purge gas storage device may include any suitable inert gas (e.g., Ar or N2) for purging the passivation chamber 312 during the passivation process. The passivation process may be performed using any suitable passivation process parameters. Further details on passivating the conductive material with aniline are provided above in reference to Figures 1A to 2B Described.

[0075] After passivating the conductive material, the transfer robot may transfer the substrate to the deposition chamber 330. After receiving the substrate, the deposition chamber 330 may perform a deposition process to selectively form a second dielectric layer on the first dielectric layer. More specifically, the deposition process may be a water-free and plasma-free deposition process. In some embodiments, the deposition process is a CVD process. For example, the deposition process may be a pulsed CVD process.

[0076] The deposition chamber 330 may be operably coupled to a deposition precursor storage device 332 and a purge gas storage device 334. The deposition precursor storage device 332 may include any suitable deposition precursor for forming the second dielectric layer. The purge gas storage device 334 may include any suitable inert gas (e.g., Ar or N2) for purging the deposition chamber 330 during the deposition process. The deposition process may be performed using any suitable deposition process parameters. Figures 1A to 2B Further details regarding performing the deposition process are described.

[0077] In some embodiments, the deposition process is performed in the passivation chamber 310 (i.e., the passivation chamber 310 is a processing chamber configured to perform a passivation process and a deposition process). In these embodiments, the deposition precursor storage device 332 and the purge gas storage device 334 may be operably coupled to the passivation chamber 310. In some embodiments, the passivation process is performed in the deposition chamber 330 (i.e., the deposition chamber 330 is a processing chamber configured to perform a passivation process and a deposition process). In these embodiments, at least one passivation gas storage device 312 may be operably coupled to the deposition chamber 330.

[0078] In some embodiments, the system 300 may optionally include a cleaning chamber 350 to perform an optional cleaning process (i.e., a pre-cleaning process) before passivation and / or to perform an optional cleaning process (i.e., a post-cleaning process) after the second dielectric layer is formed. The interface 340-3 may be disposed between the cleaning chamber 350 and the transfer chamber 320. In some embodiments, the cleaning chamber 350 is an in-situ cleaning chamber, and the interface 340-3 is a gate valve. In some embodiments, the cleaning chamber 350 is an ex-situ cleaning chamber, and the interface 340-3 is a load lock chamber.

[0079] For example, the pre-cleaning process may be a thermal EtOH treatment. As another example, the pre-cleaning process may be a hydrogen radical treatment. The pre-cleaning process and / or the post-cleaning process may be performed using any suitable pre-cleaning process parameters.

[0080] For example, performing the post-cleaning process may include heating the device to a temperature greater than or equal to 350° C. As another example, performing the post-cleaning process may further include removing defects (e.g., portions of dielectric material that may have been formed on the conductive material during a deposition process). As another example, the post-cleaning process may be a plasma cleaning process. As yet another example, the post-cleaning process may be a remote plasma cleaning process. The post-cleaning process may be performed using any suitable post-cleaning process parameters.

[0081] The cleaning chamber 350 may be operatively coupled to at least one cleaning gas storage device 352. The at least one cleaning gas storage device 352 may include suitable cleaning chemicals. For example, the at least one cleaning gas storage device 352 may include an ethanol storage device for performing hot EtOH cleaning. The at least one passivation gas storage device 312 may further include a purge gas storage device. The purge gas storage device may include any suitable inert gas (e.g., Ar or N2) for purging the cleaning chamber 352.

[0082] In some embodiments, the pre-cleaning process may be performed in the same chamber as the passivation (e.g., the passivation chamber 310 or the deposition chamber 330). In these embodiments, at least one cleaning gas storage device 352 may be operably coupled to the passivation chamber 310 and / or the deposition chamber 330. In some embodiments, the post-cleaning process may be performed in the passivation chamber 310 and / or the deposition chamber 330. In these embodiments, at least one cleaning gas storage device 352 may be operably coupled to the passivation chamber 310 and / or the deposition chamber 330. Further details on performing cleaning processes (e.g., pre-cleaning processes and / or post-cleaning processes) are described above with reference to Figures 1A to 2B Described.

[0083] The foregoing description has been described many specific details, such as examples of specific systems, parts, methods, etc., in order to better understand several embodiments of the present disclosure. However, it will be apparent to those skilled in the art that at least some embodiments of the present disclosure may be implemented without these specific details. In other cases, well-known parts or methods are not described in detail or presented in a simple block diagram format to avoid unnecessarily obscuring the present disclosure. Therefore, the specific details of elaboration are merely exemplary. Specific implementations may be different from these exemplary details and are still considered to be within the scope of the present disclosure.

[0084] References to "one embodiment" or "an embodiment" in this specification refer to at least one embodiment including a particular feature, structure or characteristic associated with the embodiment. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing in various places in this specification do not necessarily refer to the same embodiment. In addition, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". When the term "about" or "approximately" is used herein, this is intended to mean that the nominal value given is accurate to within ±10%.

[0085] Although the operations of the methods herein are shown and described in a particular order, the order of operations of each method may be changed so that certain operations are performed in reverse order, or certain operations are performed at least partially simultaneously with other operations. In another embodiment, the instructions or sub-operations of different operations may have an intermittent and / or alternating manner.

[0086] It should be understood that the above description is intended to illustrate, rather than to limit. After reading and understanding the above description, many other embodiments will be apparent to those skilled in the art. Therefore, the scope of the present disclosure should be determined with reference to the full scope of the appended claims and the equivalents of such claims.

Claims

1. A method, comprising: forming a conductive material on the first dielectric layer; exposing the conductive material to aniline to produce a passivated surface of the conductive material; as well as After exposing the conductive material to aniline, a second dielectric layer is formed on the first dielectric layer using a deposition process, wherein the deposition process is a non-aqueous and non-plasma deposition process, and wherein the second dielectric layer is not formed on the passivated surface of the conductive material.

2. The method of claim 1, further comprising: Before exposing the conductive material to aniline, a pre-cleaning process is performed to reduce native oxides on the surface of the conductive material.

3. The method of claim 1, wherein the conductive material comprises a conductive line associated with a metallization level of a device, and wherein the first dielectric layer is an inter-layer dielectric (ILD) layer of the device.

4. The method of claim 1, wherein the deposition process is a pulsed chemical vapor deposition (CVD) process.

5. The method of claim 4, wherein the pulsed CVD process is performed at a temperature less than or equal to about 350°C.

6. The method of claim 1, wherein the first dielectric layer comprises at least one of: silicon dioxide, carbon-doped silicon oxide, or silicon nitride. The method of claim 1 , wherein the conductive material comprises a transition metal. The method of claim 1 , wherein the second dielectric layer comprises a metal oxide.

9. The method of claim 1, further comprising: forming a third dielectric layer on the second dielectric layer and the conductive material; as well as A second conductive material is formed on the third dielectric layer.

10. The method of claim 5, wherein the second conductive material comprises a via, and wherein the first dielectric layer is an interlayer dielectric (ILD) layer.

11. A system comprising at least one chamber, the at least one chamber being configured to: exposing a conductive material to aniline to produce a passivated surface of the conductive material, wherein the conductive material is formed on a first dielectric layer deposited on a substrate; and After exposing the conductive material to aniline, a second dielectric layer is formed on the first dielectric layer using a deposition process, wherein the deposition process is a non-aqueous and non-plasma deposition process, and wherein the second dielectric layer is not formed on the passivated surface of the conductive material.

12. The system of claim 11, wherein the at least one chamber is further configured to perform a pre-cleaning process to reduce native oxide on a surface of the conductive material prior to exposing the conductive material to aniline.

13. The system of claim 11, further comprising a deposition precursor storage device and a purge gas storage device, each of the deposition precursor storage device and the purge gas storage device being operably coupled to the at least one chamber.

14. The system of claim 13, wherein the deposition precursor storage device holds a deposition precursor selected from the group consisting of: hafnium tert-butoxide, titanium isopropoxide, aluminum isopropoxide, aluminum tri-sec-butoxide, tetraethyl orthosilicate (TEOS), tetrabutyl orthosilicate (TBOS), or methyl orthosilicate (TMOS).

15. The system of claim 11, wherein the deposition process is a pulsed chemical vapor deposition (CVD) process.

16. The system of claim 15, wherein the pulsed CVD process is performed at a temperature less than or equal to about 350°C.

17. The system of claim 11, wherein the first dielectric layer comprises at least one of: silicon dioxide, carbon-doped silicon oxide, or silicon nitride.

18. The system of claim 11, wherein the conductive material comprises a transition metal.

19. The system of claim 11, wherein the second dielectric layer comprises a metal oxide.

20. The system of claim 11, wherein the at least one chamber is further configured to: forming a third dielectric layer on the second dielectric layer and the conductive material; and A second conductive material is formed on the third dielectric layer.

Images