Optoelectronic device

Abstract

The present disclosure relates to a pixel comprising:-a light emitting element (32) and a first transistor (36) coupled in series between a reference node (40) and a power supply node (52); and a first circuit (106) comprising a first terminal coupled to a control terminal of the first transistor (36), a second terminal coupled to a reference node (40), the first circuit configured to generate a control voltage (VGS) on the first terminal, the first circuit (106) comprising a variable voltage divider (108, 110, 112, 120) configured to provide the control voltage (VGS) on the first terminal; and-a first switch (114) coupled between the first terminal of the first circuit and a conductive terminal of the first transistor (36).

Description

[0001] French Patent Application No. FR2209863, from which this application claims priority, is incorporated herein by reference to the fullest extent allowed by law. Technical Field

[0002] The present disclosure relates generally to optoelectronic devices and, more particularly, to devices including pixels and drivers thereof. Background Art

[0003] A pixel of an image corresponds to a unit element of an image displayed by a display screen. For the display of a color image, the display screen typically includes at least three components for each pixel of the displayed image, also referred to as display sub-pixels, each of which emits light radiation, referred to as a substantially monochrome (e.g., red, green, and blue) image pixel color component. The superposition of the image pixel color components emitted by the three display sub-pixels provides the observer with a colored sensation corresponding to the pixel of the displayed image. In this case, the component formed by the three display sub-pixels for displaying an image pixel is referred to as a display pixel of the display screen. Each display sub-pixel may include a light source, in particular a light emitting diode.

[0004] The display pixels may be distributed in an array, with each display pixel being located at the intersection of a row (also referred to as a line) and a column of the array. Each display pixel comprises, for example, a light emitting element and associated electronics, such as a driver. Electrodes are provided along the rows and columns to connect each display pixel to a control circuit. Typically, each row of display pixels is selected successively by a signal ROW transmitted along the row electrodes, and the display pixels of the selected row are programmed to display the desired image pixels by information COL transmitted along the column electrodes.

[0005] Each generation of screens includes more display pixels to provide more detailed images. However, the increase in the number of display pixels and therefore the number of related components generates a large amount of quiescent current and increases energy consumption. Summary of the invention

[0006] One embodiment addresses all or some of the disadvantages of known optoelectronic devices.

[0007] There is a need for a photovoltaic device that produces less quiescent current.

[0008] A more compact pixel driver is needed.

[0009] The control voltage of the transistors in the pixel needs to be optimized.

[0010] One embodiment provides a pixel, comprising:

[0011] a light emitting element and a first transistor coupled in series between a reference node and a power supply node; and

[0012] a first circuit comprising a first terminal coupled to a control terminal of the first transistor, a second terminal coupled to a reference node, the first circuit being configured to generate a control voltage at the first terminal, the first circuit comprising a variable voltage divider configured to provide the control voltage at the first terminal, the variable voltage divider comprising two capacitive branches, a ratio between the branches being variable; and

[0013] A first switch is coupled between the first terminal of the first circuit and the conduction terminal of the first transistor. This structure allows reducing the quiescent current and reducing the size of the pixel.

[0014] According to one embodiment, the voltage divider includes a first capacitor coupled between first and second terminals of the first circuit.

[0015] According to one embodiment, the first circuit comprises a third terminal coupled to an application node of the data signal.

[0016] According to one embodiment, the voltage divider includes a second capacitor coupled between the first terminal of the first circuit and a third terminal of the first circuit.

[0017] According to one embodiment, the pixel includes a second switch coupled between the second terminals of the first circuit and a third switch coupled between the second capacitor and the third terminal of the first circuit.

[0018] According to an embodiment, the voltage divider comprises at least one third capacitor configured to be coupled between the first terminal and the second or third terminal depending on the control voltage.

[0019] According to one embodiment, each of the at least one third capacitor is coupled in series with a fourth switch, one terminal of the second capacitor is coupled to the first terminal of the first circuit, the second terminal of the second capacitor is coupled to the first terminal of the fourth switch, the fourth switch includes a second terminal coupled to the second terminal of the first circuit, and the fourth switch includes a third terminal coupled to the third terminal of the first circuit.

[0020] According to one embodiment, the first circuit comprises at least two components of a second capacitor coupled in series with a fourth switch, the fourth switch being controlled by different control voltages.

[0021] According to one embodiment, the first transistor and the element are both coupled in series with the fifth switch.

[0022] According to one embodiment, the first circuit includes a sixth switch coupled between the control terminal of the transistor and an application node of the reset voltage.

[0023] Another embodiment provides a display screen including a plurality of pixels as described above.

[0024] According to one embodiment, the pixels are arranged in an array, and the third terminal of each first circuit is configured to receive a voltage common to all pixels in the same row.

[0025] According to one embodiment, the light emitting elements are coupled to a common cathode, the element of each pixel being coupled between the first transistor of said pixel and a reference node.

[0026] Another embodiment provides a method for controlling a pixel as described above, comprising:

[0027] a first phase, during which the first switch is closed and a capacitor of a voltage divider coupled between the first terminal and the second terminal of the first circuit is charged, and

[0028] The second phase, during which the first switch is opened.

[0029] According to one embodiment, the method comprises alternation of a first phase and a second phase. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The foregoing features and advantages and other features and advantages will be described in detail in the following description of specific embodiments, which are illustrated and not limited by reference to the accompanying drawings, in which:

[0031] Figure 1 An example of an optoelectronic device is shown;

[0032] Figure 2 An example of a pixel is schematically shown;

[0033] Figure 3 In more detail, the embodiment according to Figure 2 A portion of a pixel;

[0034] Figure 4 In more detail, the Figure 3 Embodiment Figure 2 A portion of a pixel;

[0035] Figure 5 Shows Figure 3 Operation of the embodiments;

[0036] Figure 6 Shows Figure 3 Another operation of an embodiment of the present invention;

[0037] Figure 7 Shows Figure 3 Another operation of an embodiment of the present invention;

[0038] Figure 8 Shown in more detail Figure 3 Different operations of embodiments of the present invention;

[0039] Fig. 9 In more detail, another embodiment of the present invention is shown. Figure 2 a part of a device;

[0040] Fig.10 In more detail, the Fig. 9 Embodiment Figure 2 A portion of a pixel;

[0041] Fig.11 Shows Fig. 9 Operation of the embodiments;

[0042] Fig.12 Shows Fig. 9 Another operation of an embodiment of the present invention;

[0043] Fig.13 Shows Fig. 9 Another operation of an embodiment of; and

[0044] Fig.14 Shown Fig. 9 Operation of the illustrated embodiment. DETAILED DESCRIPTION

[0045] In the various figures, the same features are represented by the same reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may have the same structure, size, and material properties.

[0046] For the sake of clarity, only the operations and elements that are helpful for understanding the embodiments described herein are described and illustrated in detail.

[0047] Unless otherwise specified, when referring to two elements being connected together, this means a direct connection without any intermediate elements other than conductors, and when referring to two elements being coupled together, this means the two elements may be connected or coupled through one or more other elements.

[0048] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers such as terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers such as terms "above", "below", "higher", "lower", etc., or directional qualifiers such as "horizontal", "vertical", etc., please refer to the direction shown in the figure.

[0049] Unless otherwise indicated, the expressions "about," "approximately," "substantially," and "approximately" mean within 10%, preferably within 5%.

[0050] Figure 1An example of an optoelectronic device 10 is shown.

[0051] The device 10 includes a screen 12. The screen 12 is configured to project light, pictures or videos, for example. The screen includes a pixel array 14. The screen 12 includes, for example, at least one million pixels, for example at least two million pixels, for example at least eight million pixels. The screen includes rows 16 of pixels 14 and columns 18 of pixels 14.

[0052] The device 10 also includes a row control circuit or driver 20 and a column control circuit or driver 22. The circuit 20 is configured to provide a row voltage ROW, in other words, a control voltage common to all pixels in the same row. Similarly, the circuit 22 is configured to provide a column voltage COL, in other words, a control voltage common to all pixels in the same column. For example, in an illumination mode, such as a pulse width modulation (PWM) mode, the voltage ROW corresponds to a line selection and clock signal. For example, the voltage COL corresponds to illumination data, such as video data.

[0053] The device 10 includes, for example, a controller 24 configured to provide data to the circuits 20 and 22 to generate the voltages ROW and COL. The controller 24 may also provide a clock signal to the circuits 20 and 22, and ultimately provide a clock signal to the pixel 14. The controller 24 is, for example, a timing controller.

[0054] Figure 2 One embodiment of a pixel 14 is schematically shown. The pixel 14 comprises a region 26 and a region 30.

[0055] Region 26 includes at least one light emitting element. For example, in the remainder of the specification, the light emitting element is a light emitting diode. However, the light emitting element can be any kind of light emitting component. Region 26 includes, for example, three light emitting diodes, one configured to provide blue light, one configured to provide green light, and one configured to provide red light.

[0056] Area 30 is, for example, a pixel driver. Area 30 includes analog and digital circuits. Area 30 includes peripheral circuits. Area 30 includes, for example, a power supply circuit configured to provide a power supply voltage for a pixel. Area 30 includes, for example, control logic.

[0057] For example, each pixel includes only four input pads, which are not shown. In other words, each pixel receives only four external voltages: a power supply voltage, a reference voltage (eg, ground GND), a signal ROW transmitted along a row electrode, and a signal COL transmitted along a column electrode.

[0058] Figure 3 In more detail, the embodiment according to Figure 2 A portion of pixel 14. Figure 3In the example of FIG. 4 , pixels are configured to be coupled to other pixels in a common anode.

[0059] Pixel 14 includes a light emitting diode 32. Diode 32 is coupled in series with transistor 36 and switch 38 between node 52 to which a power supply voltage VCC of the pixel is applied and node 40 to which a reference voltage (e.g., ground GND) is applied. Transistor 36 is, for example, a metal oxide semiconductor field effect transistor (MOSFET), such as a p-channel transistor. Transistor 36 includes a control terminal (e.g., a gate) and two conductive terminals (e.g., a drain and a source). Switch 38 includes two terminals 48 and 50.

[0060] Diode 32, switch 38, and transistor 36 are coupled in series between node 52 and node 40. Diode 32, transistor 36, and switch 38 are coupled so that diodes of different pixels can be coupled to a common anode. Diode 32 is coupled between node 52 and switch 38. In other words, the anode of diode 32 is coupled (preferably connected) to node 52, and the cathode of diode 32 is coupled (preferably connected) to terminal 48 of switch 38. Terminal 50 of switch 38 is coupled to node 40 through transistor 36. In other words, terminal 50 of switch 38 is coupled (preferably connected) to node 105, which is coupled (preferably connected) to a conductive terminal, such as the drain of transistor 36, and another conductive terminal (e.g., source) of transistor 36 is coupled (preferably connected) to node 40.

[0061] The control terminal of transistor 36 is coupled (preferably connected) to circuit 106 configured to generate voltage V GS .

[0062] The circuit 106 comprises a variable capacitive voltage divider. In other words, the circuit 106 comprises a voltage divider in which the ratio between the two capacitive branches is variable.

[0063] The circuit 106 is a voltage divider, so the circuit 106 includes a capacitor 108. The capacitance of the capacitor 108 is preferably constant. The capacitor 108 is coupled between the control terminal of the transistor 36 and the node 40. The first terminal of the capacitor 108 is coupled (preferably connected) to the node 109, which is coupled (preferably connected) to the control terminal of the transistor 36. The second terminal of the capacitor 108 is coupled (preferably connected) to the node 40.

[0064] The control terminal of transistor 36 is also coupled to a node 118 to which a voltage ROW1 generated by voltage ROW is applied. The control terminal of transistor 36 is coupled to node 118 via capacitor 120. The capacitance of capacitor 120 is preferably constant. More specifically, the control terminal of transistor 36 is coupled (preferably connected) to a terminal of capacitor 120. In other words, said terminal of capacitor 120 is coupled (preferably connected) to node 109. The other terminal of capacitor 120 is coupled (preferably connected) to node 118.

[0065] The voltage divider further comprises at least one capacitor 110 coupled in parallel with the capacitor 108 or the capacitor 120 according to the control signal. The capacitance of the capacitor 110 is, for example, constant. The capacitance of the capacitor 110 is, for example, substantially equal.

[0066] exist Figure 3 In the example of , the distributor comprises three capacitors 110 which are labeled 110a, 110b and 110c. In general, the number of capacitors 110 depends on the application.

[0067] Each capacitor 110 is coupled in series with a switch 112. In other words, capacitor 110a is coupled in series with switch 112a, capacitor 110b is coupled in series with switch 112b, and capacitor 110c is coupled in series with switch 112c.

[0068] A terminal of each capacitor 110 is coupled (preferably connected) to node 109. Another terminal of each capacitor 110 is coupled (preferably connected) to an input terminal of a corresponding switch 112. Each switch 112 includes its first output terminal coupled (preferably connected) to node 40 and a second output terminal coupled (preferably connected) to node 118. Each switch 112 is configured to connect the corresponding capacitor 110 to node 40 or node 118 according to a control voltage. Each switch 112 is preferably controlled by its own control voltage (e.g., independent of the control voltages of other switches 112).

[0069] Therefore, the value of voltage VGS is determined by the control voltage of switch 112, which determines the capacitance quotient of the two branches of the voltage divider.

[0070] The circuit 106 further includes a switch 114 coupled between the node 109 and the node 105. The circuit 106 further includes a switch 115 coupled between the node 109 and a node 111 to which a reset voltage VRS is applied.

[0071] The switch 115 comprises a control terminal, for example coupled (preferably connected) to an application node of the control voltage SW1. The switch 115 is configured for resetting the voltage divider. The switch 114 comprises a control terminal, for example coupled (preferably connected) to a node to which the control voltage SW2 is applied.

[0072] The control terminal of the switch 38 is, for example, coupled (preferably connected) to an application node of the control voltage SW3 .

[0073] Figure 3 The circuit includes, for example, a calibration step in which known capacitance values ​​are assigned to the branches of the voltage divider. The capacitor coupled between nodes 109 and 40 is charged, Figure 3 The voltage CTL not shown in the figure has a first value. Then, the voltage CTL takes a second value, and the voltage VGS determined by the capacitive voltage divider is applied to the transistor 36. The diode is then lit by the known data. The brightness of the diode is measured and compared with the desired brightness. The control voltage value of the switch 112 is modified according to the difference between the desired brightness and the measured brightness. The brightness of the diode is measured again. For example, the calibration step can be applied again to further correct the brightness value of the diode.

[0074] Figure 4 In more detail, the Figure 3 Embodiment Figure 2 An example of an implementation of a portion of a pixel. More specifically, Figure 4 A circuit 200 is shown that generates control voltages SW1 , SW2 , and SW3 .

[0075] The control voltages SW1, SW2 and SW3 are obtained from the signal line, the voltage CTL and the voltage PWM-D

[0076] The voltage CTL indicates that the driver is in PWM mode. In other words, the voltage CTL is, for example, a binary value and takes a first value when the driver is in PWM mode and takes another value when the driver is in video data writing mode. The voltage PWM-D corresponds to a binary signal, for example. The voltage PWM-D corresponds to data of the PWM mode.

[0077] Circuit 200 includes an input node 202 configured to receive a signal ROW, an input node 204 configured to receive a voltage CTL, and an input node 206 configured to receive a signal PWM-D. Circuit 200 includes an output node 208 on which a voltage SW1 is applied, an output node 210 on which a voltage SW2 is applied, and an output node 212 on which a voltage SW3 is applied.

[0078] Circuit 200 includes a logic gate NAND 214. A first input of gate 214 is coupled (preferably connected) to node 204. A second input of gate 214 is coupled to node 202 via inverter 216. In other words, an input of inverter 216 is coupled (preferably connected) to node 202, and an output of inverter 216 is coupled (preferably connected) to a second input of gate 214.

[0079] Circuit 200 includes a logic gate AND 218. An output of gate 218 is coupled (preferably connected) to node 212. A first input of gate 218 is coupled (preferably connected) to node 206. A second input of gate 218 is coupled (preferably connected) to an output of logic gate 214.

[0080] Circuit 200 includes a logic gate NOR 220. An output of gate 220 is coupled (preferably connected) to node 210. A first input of gate 220 is coupled (preferably connected) to an output of logic gate 214. A second input of gate 220 is coupled to node 222. Node 222 is coupled to the output of logic gate 214 via delay circuit 224. In other words, one terminal of delay circuit 224 is coupled (preferably connected) to the output of gate 214, and another terminal of delay circuit 224 is coupled (preferably connected) to node 222.

[0081] Circuit 200 includes a logic gate NOR 226. An output of logic gate 226 is coupled (preferably connected) to node 208. A first input of gate 226 is coupled (preferably connected) to an output of gate 214. A second input of gate 226 is coupled to node 222 via inverter 228. In other words, an input of inverter 228 is coupled (preferably connected) to node 222, and an output of inverter 228 is coupled (preferably connected) to a second input of gate 226.

[0082] Figure 5 , 6 7 and 8 show the sequential steps of pixel operation. Figure 5 and Figure 6 A refresh of the driver is shown. Figure 7 A PWM mode is shown. Preferably, during the PWM driving of the pixels (eg before each data transmission), a refresh is regularly applied.

[0083] Figure 5 Shows Figure 3 More specifically, Figure 5 The reset steps are shown.

[0084] During this step, the control voltages SW1, SW2, and SW3 are such that switch 115 is closed, switch 114 is open, and switch 38 is open. Thus, the voltage on the gate of transistor 36 is substantially equal to the reset value VRS.

[0085] Figure 6 Shows Figure 3 Another operation of an embodiment of the present invention. Figure 6 The programming steps are shown.

[0086] During this step, the control voltages SW1, SW2, and SW3 are such that switch 115 is open, switch 114 is closed, and switch 38 is open. Therefore, the voltage on the gate of transistor 36 is substantially equal to the threshold value Vth of transistor 36.

[0087] Figure 7 Shows Figure 3 Another operation of the embodiment of the present invention. This operation corresponds to the PWM mode.

[0088] During this step, the control voltages SW1, SW2 and SW3 cause switch 115 to be open and switch 114 to be open. Switch 38 is opened and closed according to the PWM data. The voltage on the gate of transistor 36 depends on the signal ROW1.

[0089] Figure 8 Shown in more detail Figure 3 More specifically, Figure 8 Signal ROW1 , voltage CTL, control voltage SW1 , control voltage SW2 , and control voltage SW3 during PWM mode (A) and video data write mode (B) are shown.

[0090] During the video data write mode (B), voltage CTL takes a low value, in this example, indicating that the pixel is not in PWM mode. In addition, voltages SW1, SW2, and SW3 have high values, high values, and low values, respectively. Switches 115, 114, and 38 are open. Signal ROW1 corresponds to the clock signal received on signal COL for writing data.

[0091] The PWM pattern (A) consists of alternating periods (C) and (D).

[0092] During each period (D), the light emitting element 32 is lit according to at least one data (eg, a single data). Each period (D) corresponds to Figure 7 . Therefore, voltages SW1, SW2 both have high values, corresponding to an off state. Voltage SW3 causes switch 38 to open and close according to the programmed illumination of the pixel. Voltage CTL has a high value indicating PWM mode. Signal ROW1 has a high value.

[0093] The period (C) corresponds to the driver's refresh, in other words, to Figure 5 and Figure 6 During the beginning of cycle (C), in other words, at Figure 5 During the step of , signal ROW1 has a low value, voltage CTL has a high value, voltage SW1 has a low value, voltage SW2 has a high value, and voltage SW3 has a low value. During the rest of period (C), in other words, during Figure 6 During step , signal ROW1 has a low value, voltage CTL has a high value, voltage SW1 has a high value, voltage SW2 has a low value, and voltage SW3 has a low value.

[0094] Preferably, the cycles (C) have the same duration. The cycles (D) have, for example, the same duration. Alternatively, the cycles (D) are binary weighted cycles. In other words, the duration (D) of some cycles is equal to 1 / (2^n) times the maximum duration of the cycle (D), where n is a positive integer value. Alternatively, the cycles (C) occur periodically, for example in the PWM mode (A).

[0095] Fig. 9 In more detail, another embodiment of the present invention is shown. Figure 2 part of the device.

[0096] Fig. 9 Examples and Figure 3 The difference of the embodiment is that Fig. 9 An embodiment includes a switch 230 and a switch 232 .

[0097] Switch 230 is coupled in series with capacitor 120 between node 109 and node 118. In other words, one terminal of capacitor 120 is coupled (preferably connected) to node 109, and the other terminal of capacitor 120 is coupled (preferably connected) to node 234. One terminal of switch 230 is coupled (preferably connected) to node 234, and the other terminal of switch 230 is coupled (preferably connected) to node 118.

[0098] The switch 232 is coupled between the nodes 40 and 234. In other words, one terminal of the switch 232 is coupled (preferably connected) to the node 234, and the other terminal of the switch 232 is coupled (preferably connected) to the node 40.

[0099] Switches 230 and 232 are configured to have opposite states. In other words, when one of switches 230 and 232 is open, the other is closed. Switch 230 includes a control terminal configured to receive a control voltage SW4. Switch 232 includes a control terminal configured to receive a control voltage SW4'. Control voltages SW4 and SW4' are, for example, complementary binary voltages. Voltage SW4 is, for example, equal to voltage CTL.

[0100] Fig.10 In more detail, the Fig. 9 Embodiment Figure 2 More precisely, Figure 4 A circuit 200 is shown that generates control voltages SW1 , SW2 , and SW3 .

[0101] The control voltages SW1, SW2 and SW3 are obtained from the signal line, the voltage CTL and the voltage PWM-D.

[0102] Circuit 200 includes an input node 202' configured to receive a signal ROW, an input node 204' configured to receive a voltage CTL, and an input node 206' configured to receive a signal PWM-D. Circuit 200 includes an output node 208' to which a voltage SW1 is applied, an output node 210' to which a voltage SW2 is applied, and an output node 212' to which a voltage SW3 is applied.

[0103] Circuit 200 includes a logic gate NAND 214'. A first input of gate 214' is coupled (preferably connected) to node 204'. A second input of gate 214' is coupled to node 202' via inverter 216'. In other words, an input of inverter 216' is coupled (preferably connected) to node 202', and an output of inverter 216' is coupled (preferably connected) to a second input of gate 214'.

[0104] Circuit 200 includes a logic gate AND 218'. An output of logic gate 218' is coupled (preferably connected) to node 212'. A first input of gate 218' is coupled (preferably connected) to node 206'. A second input of gate 214' is coupled (preferably connected) to an output of logic gate 214'.

[0105] Circuit 200 includes a logic gate NOR 220'. An output of logic gate 220' is coupled (preferably connected) to node 210'. A first input of gate 220' is coupled (preferably connected) to node 204'. A second input of gate 220' is coupled to node 222'. Node 222' is coupled to node 204' via a delay circuit 224'. In other words, one terminal of delay circuit 224' is coupled (preferably connected) to node 204', and another terminal of delay circuit 224' is coupled (preferably connected) to node 222'.

[0106] Circuit 200 includes a logic gate NOR 226'. The output of logic gate 226' is coupled (preferably connected) to node 208'. A first input of gate 226' is coupled (preferably connected) to node 204'. A second input of gate 226' is coupled to node 222' via inverter 228'. In other words, an input of inverter 228' is coupled (preferably connected) to node 222', and an output of inverter 228' is coupled (preferably connected) to a second input of gate 226'.

[0107] Fig.11 , 12 1 and 13 show the sequential steps of pixel operation.

[0108] Fig.11 Shows Fig. 9 More specifically, Fig.11 The reset steps are shown.

[0109] During this step, the control voltages SW1, SW2, SW3 and SW4 cause switches 38, 114 and 230 to be open and switches 115 and 232 to be closed. Therefore, the voltage on the gate of transistor 36 is substantially equal to the reset value VRS.

[0110] Fig.12 Shows Fig. 9 Another operation of the illustrated embodiment. Fig.12 The programming steps are shown.

[0111] During this step, control voltages SW1, SW2, SW3 and SW4 cause switches 38, 115 and 230 to be open, and switches 114 and 232 to be closed. Thus, the voltage on the gate of transistor 36 is substantially equal to the value Vth of transistor 36.

[0112] Fig.13 Shows Fig. 9 Another operation of the embodiment of the present invention. This operation corresponds to the PWM mode.

[0113] During this step, control voltages SW1, SW2, SW3 and SW4 cause switches 114, 115 and 232 to be open, and switch 230 to be closed. Switch 38 is opened and closed according to the PWM data. The voltage on the gate of transistor 36 depends on signal ROW1.

[0114] Fig.14 Shows Fig. 9 More specifically, Fig.14 The signal ROW1 , the voltage CTL, in other words, the control voltage SW4 , the control voltage SW1 , the control voltage SW2 , and the control voltage SW3 during the PWM mode (A) and the video data writing mode (B) are shown.

[0115] During PWM mode, control voltages SW1 and SW2 are maintained at high values. In other words, switches 115 and 114 are both kept closed. Voltage CTL, in other words, voltage SW4 is maintained at a high value. Therefore, during PWM mode, switches 230 and 232 are respectively kept closed and open. Signal ROW is maintained at a low value during period (C) and at a high value during period (D). Period (C) occurs periodically, for example, during PWM mode (A). During period (C), voltage SW3 is maintained at a low value, corresponding to the open state of switch 38. During period (D), voltage SW3 alternates between a high value and a low value depending on the desired illumination of the pixel.

[0116] The PWM mode (A) includes alternation of periods (C) and (D). The operation of the pixel includes alternation of the PWM mode (A) and the data writing mode (B).

[0117] The data writing mode includes a first period (E) followed by a second period (F). The first period (E) corresponds to the start of the data writing mode.

[0118] During the first period (E), the signal ROW, the voltage CTL, and the voltages SW1 and SW3 are maintained at low values. The voltage SW2 is maintained at a high value.

[0119] During the second period (F), voltage CTL takes a low value, which in this example indicates that the pixel is not in PWM mode. In addition, voltages SW1, SW2, and SW3 have high values, high values, and low values, respectively. Switches 115 and 38 are open. Switch 114 is closed. Signal ROW1 corresponds to the clock signal received on signal COL for writing data.

[0120] An advantage of the described embodiment is that the control circuit of transistor 36 is simplified, which makes it less expensive and smaller. In particular, the analog part of each pixel is reduced.

[0121] Another advantage of the described embodiment is that the control circuit is a passive device, which reduces quiescent current.

[0122] Another advantage of the described embodiment is that voltage VGS is generated based on voltages ROW and COL.

[0123] Another advantage of the described embodiment is that the voltage VGS can be simply optimized to calibrate each pixel independently.

[0124] An advantage of the above-described embodiment is that the capacitance value of the capacitive voltage divider for each pixel can be changed. The capacitive voltage divider can be used to calibrate the pixels, for example using fine tuning. It allows compensation for efficiency variations from one pixel to another. By correcting the pixels individually, it is possible to make all pixels emit the same level of light. This uniformity cannot be obtained by a non-variable capacitive voltage divider such as the voltage divider disclosed in US20170084220 because it is impossible to calibrate the pixels individually. In fact, it is impossible to apply different variable voltages to the input of the voltage divider for each pixel. Typically, the display pixels are distributed in an array, and the voltage applied to the voltage divider is the same for several pixels, for example for all pixels in a row of a pixel display array because they receive the same signal.

[0125] Various embodiments and variations have been described. It will be appreciated by those skilled in the art that certain features of these embodiments may be combined, and that other variations will be readily apparent to those skilled in the art.

[0126] Finally, based on the functional description provided above, the actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art. In particular, there are multiple ways to implement a capacitive voltage divider comprising two capacitive branches, the ratio between the two branches being variable, the voltage divider being configured to ensure that the voltage division ratio between the two branches is modified by modifying the capacitance value of at least one branch. An example of such a voltage divider 106 is described in this specification. However, the description of such a voltage divider is not restrictive, as those skilled in the art may envision capacitive voltage dividers having the same functional features and different implementations.

Claims

1. A pixel, comprising: - a light emitting element (32) and a first transistor (36) coupled in series between a reference node (40) and a power supply node (52); as well as a first circuit (106), the first circuit comprising a first terminal coupled to a control terminal of a first transistor (36), a second terminal coupled to a reference node (40), the first circuit being configured to generate a control voltage (VGS) at the first terminal, the first circuit (106) comprising a variable voltage divider (108, 110, 112, 120) configured to provide the control voltage (VGS) at the first terminal, the variable voltage divider comprising two capacitive branches, a ratio between the branches being variable; as well as - a first switch (114) coupled between the first terminal of the first circuit and a conduction terminal of the first transistor (36).

2. The pixel according to claim 1, wherein: The voltage divider includes a first capacitor (108) coupled between the first terminal and the second terminal of the first circuit (106).

3. The pixel according to claim 1 or 2, wherein: The first circuit includes a third terminal (118) coupled to an application node of a data signal (ROW).

4. The pixel according to claim 3, wherein: The voltage divider includes a second capacitor (120) coupled between the first terminal of the first circuit (106) and the third terminal (118) of the first circuit.

5. The pixel of claim 4, comprising a second switch (232) coupled between the second terminals of the first circuit and a third switch (230) coupled between the second capacitor and the third terminal of the first circuit.

6. The pixel according to any one of claims 3 to 5, wherein: The voltage divider includes at least one third capacitor (110a, 110b, 110c) configured to be coupled between the first terminal and the second terminal or the third terminal according to a control voltage (CTL).

7. The pixel according to claim 6, wherein: Each of at least one third capacitor is coupled in series with a fourth switch (112a, 112b, 112c), one terminal of the second capacitor is coupled to the first terminal of the first circuit, a second terminal of the second capacitor is coupled to the first terminal of the fourth switch, the fourth switch includes a second terminal coupled to the second terminal of the first circuit, and the fourth switch includes a third terminal coupled to the third terminal of the first circuit.

8. The pixel according to claim 7, wherein: The first circuit includes at least two components of a second capacitor coupled in series with a fourth switch, the fourth switch being controlled by different control voltages.

9. The pixel according to any one of claims 1 to 8, wherein: The first transistor (36) and the element (32) are both coupled in series with a fifth switch (38).

10. The pixel according to any one of claims 1 to 9, wherein: The first circuit includes a sixth switch (115) coupled between a control terminal of the transistor (36) and an application node of a reset voltage.

11. A display screen comprising a plurality of pixels according to any one of claims 1 to 10.

12. The display screen according to claim 11, wherein: The pixels are arranged in an array, and the third terminal (118) of each first circuit is configured to receive a common voltage of all the pixels in the same row.

13. The display screen according to claim 11 or 12, wherein: The light emitting elements are coupled to a common cathode and the element (32) of each pixel is coupled between a first transistor (36) of the pixel and a reference node (40).

14. The method for controlling a pixel according to any one of claims 1 to 10, comprising: a first phase during which the first switch (114) is closed and the capacitor of the voltage divider coupled between the first terminal and the second terminal of the first circuit is charged, and - a second phase, during which the first switch (120) is opened.

15. A method according to claim 14, comprising alternating the first phase and the second phase.

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