Memory repair

Abstract

Memory devices can be protected (e.g., repaired) from hard bit errors by remapping logical pages to valid physical addresses and excluding those physical addresses with hard bit errors from being mapped. The remapping can be done in units of finer granularity than a row of memory cells, such that those valid memory cells within a row can still be used for the remapping, although the row may contain unavailable memory cells.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor memories and methods, and more particularly to apparatus, systems, and methods for memory repair. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuit systems in computers or other electronic systems. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), etc. Non-volatile memory can provide persistent data by retaining stored data when power is not applied and may include NAND flash memory, NOR flash memory, ferroelectric random access memory (FeRAM), and resistance variable memory (e.g., phase change random access memory (PCRAM)), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), etc.

[0003] The memory device may be coupled to a host (e.g., a host computing device) to store data, commands, and / or instructions for use by the host during operation of a computer or electronic system. For example, during operation of a computing or other electronic system, data, commands, and / or instructions may be transferred between the host and the memory device. A controller may be used to manage the transfer of data, commands, and / or instructions between the host and the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a block diagram of an apparatus in the form of a computing system including a host, a controller, and a memory device according to several embodiments of the present disclosure.

[0005] Figure 2 is a block diagram of a controller and a memory device according to several embodiments of the present disclosure.

[0006] Figure 3 is a block diagram illustrating several memory banks of an access memory device according to several embodiments of the present disclosure.

[0007] Figure 4 is a diagram illustrating a logical-to-physical (L2P) table indicating logical pages that are remapped in response to a repair being performed according to several embodiments of the present disclosure. DETAILED DESCRIPTION

[0008] Systems, apparatus, and methods related to memory repair are described. Memory devices may be accessed according to various interface protocols, such as a double data rate (DDR) protocol. For example, various memory devices, such as DRAM devices, FeRAM devices, etc., may be accessed according to the DDR protocol. In order to protect the memory device from hard bit errors, the memory device may be "repaired" by remapping logical pages that were previously remapped to those "bad" memory cells that were determined to be unreliable (e.g., having hard bit errors) to different memory cells of the memory device. In some methods, this repair has been accomplished by remapping the logical pages to different rows of memory cells and completely retiring (e.g., not using) the "unreliable" rows of memory cells. In other words, in various memory repair methods, each row of memory cells is a replacement unit, which may waste those "good" memory cells from the row that is considered unreliable.

[0009] Aspects of the present disclosure address the above and other challenges of this type of repair performed on various memory devices (e.g., DRAM devices, FeRAM devices, etc.) In several embodiments, the memory devices may be accessed according to the DDR protocol, but operate at a finer granularity than a typical DRAM device, which may provide benefits such as reducing the number of "good" memory cells that would otherwise be wasted via existing memory repair methods (e.g., existing methods that may remap entire rows of cells).

[0010] As used herein, the singular forms "a", "an", and "the" include singular and plural referents unless the content clearly dictates otherwise. In addition, the word "may" is used throughout this application in a permissive sense (i.e., likely to, able to) rather than in a mandatory sense (i.e., must). The term "include" and its derivatives mean "including but not limited to". The term "coupled" means connected directly or indirectly.

[0011] The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number and the remaining digits identify the element or component in the figure. Similar elements or components between different figures may be identified by using similar numerals. For example, 124 may refer to Figure 1 Element "24" in and similar elements in Figure 2 It can be marked as 224.

[0012] Similar elements within the drawings may be referenced by hyphens and additional numbers or letters. Figure 1, 121-N. Such similar elements may generally be referred to without hyphens and additional numbers or letters. For example, elements 221-1, ..., 121-N may be collectively referred to as element 121. As used herein, the indicators "N", "X", "Y" in particular with respect to reference numerals in the drawings indicate the number of specific features that may be included as such. It will be appreciated that the elements shown in the various embodiments herein may be added, exchanged and / or eliminated in order to provide several additional embodiments of the present disclosure. In addition, it should be appreciated that the proportions and relative dimensions of the elements provided in the figures are intended to illustrate certain embodiments of the present invention and should not be understood in a limiting sense.

[0013] Figure 1 1 is a block diagram of an apparatus in the form of a computing system 100 including a host 102, a controller 110, and memory devices 120-1, ..., 120-N (collectively referred to as memory devices 120) according to several embodiments of the present disclosure. As used herein, the host 102, the controller 110, or the memory device 120 may also be individually considered as an "apparatus".

[0014] In various embodiments, host 102 may be a host system, such as a personal laptop computer, a desktop computer, a digital camera, a smart phone, a memory card reader, and / or a device with Internet of Things capabilities, as well as various other types of hosts. Host 102 may include a system motherboard and / or a backplane, and may include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of control circuitry). System 100 may include a separate integrated circuit or host, and host 102 and memory device 120 may be on the same integrated circuit. For example, system 100 may be a server system and / or a high performance computing (HPC) system and / or a portion thereof.

[0015] The controller 110 may control the execution of memory operations in response to receiving a request from the host 102. Examples of memory operations include a read operation to read data from the memory device 120 or a write operation to write data to the memory device 120. The controller 110 may further provide various error correction / detection capabilities, such as to correct (e.g., soft and / or hard) bit errors on the data read from the memory device 120. Such capabilities may be provided using various types of error correction codes (ECC), such as Hamming codes, Reed Solomon (RS) codes, Bose-Chaudhuri-Hokwenheim (BCH) codes, cyclic redundancy check (CRC) codes, Golay codes, Reed-Muller codes, Gopa codes, and Denniston codes, among others. As a non-limiting example, the controller 110 may operate based on a Hamming code and generate parity symbols (as ECC symbols). The controller 110 may include circuitry and / or firmware to perform ECC operations.

[0016] The controller 110 can be connected to the network through a plurality of input / output (I / O) paths (not shown). Figure 1 1 and 12. The memory controller 110 may be coupled to the host 102 by any number of I / O paths, such as eight, sixteen, or another number of I / O paths. In at least one embodiment, the interface coupling between the memory controller 110 and the host 102 may be a PCIe physical and electrical interface operating according to the CXL protocol.

[0017] One example of the memory device 120 is a random access memory (RAM) operated according to a protocol such as low power double data rate (LPDDRx), which may be referred to herein as an LPDDRx device, LPDDRx memory, etc. One or more of the memory devices 120 may include FeRAM, PCRAM, RRAM, MRAM, DRAM, and STTRAM, etc. The "x" in LPDDRx refers to any of the generations of the protocol (e.g., LPDDR5). In at least one embodiment, at least one of the memory devices 120 is operated as an LPDDRx device with low power features enabled, and at least one of the memory devices 120-N is operated as an LPDDRx device with at least one low power feature disabled. In some embodiments, although the memory device 120 is an LPDDRx memory device, the memory device 120 does not include circuitry configured to provide low power functionality for the memory device 120, such as a dynamic voltage frequency scaling core (DVFSC), a sub-threshold current reduction circuit (SCRC), or other low power functionality providing circuitry. Providing the LPDDRx memory device 120 without such circuitry may advantageously reduce the cost, size, and / or complexity of the LPDDRx memory device 120. As an example, the LPDDRx memory device 120 with reduced low-power functionality providing circuitry may be used in applications other than mobile applications (e.g., if the memory is not intended for use in mobile applications, some or all low-power functionality may be sacrificed to reduce the cost of producing the memory).

[0018] As in Figure 1 , the controller may further include a memory (shown as "L2P") 114 that may store logical to physical (L2P) mapping or translation data and / or a lookup table in the memory array to track the location of data in the memory device. The L2P memory 114 may be a cache memory, such as an SRAM memory.

[0019] In some embodiments, L2P information may be managed at a device level, such as at a respective memory device 120. For example, each memory device 120 may include a respective memory (shown as "L2P") 116-1, ..., 116-N that may store logical-to-physical mapping or translation data and / or a lookup table corresponding to the physical locations of the respective memory device 120.

[0020] As in Figure 1 As described in , the controller 110 may further include a repair component 112. Figure 1 2 , in order to avoid obscuring the diagram, but the repair component 112 may include various circuit systems to facilitate the performance of the operations described herein. For example, the repair component 112 may determine whether at least a portion of the memory device 120 (e.g., one or more memory cells) is unreliable (e.g., due to a hard bit error), and perform a repair operation by remapping the logical page to exclude those "bad" memory cells of the memory bank 221 (e.g., memory cells determined to be unreliable) from being mapped. Instead, those "good" memory cells in the row (e.g., having a size of 2kB, 8kB, etc.) with the "bad" memory cells may still be used and mapped to the logical page. As used herein, the term "bad memory cell" (alternatively referred to as "unreliable memory cell") refers to a memory cell determined to have a hard bit error. As used herein, the term "hard bit error" refers to an error caused by physical damage, failure, and / or defect of the memory cell storing the bit error so that the memory cell is unreliable (because reprogramming of the memory cell may not be able to correct the hard bit error). In contrast, the term "soft error" refers to an error that is not caused by physical damage, failure, and / or defect of the memory cell such that the bit error may be correctable (e.g., by reprogramming the memory cell and / or via an ECC scheme, etc.). In some embodiments, some logical pages may be mapped to memory cells in different banks of each memory device 120, such as in conjunction with Figure 3 and 4 Further explanation.

[0021] may be executed by the repair component 112 to determine a particular portion of the memory device 120 (e.g., Figure 2The scanning operation to determine whether the memory bank 221 described in the embodiment is unreliable may be performed at initialization (e.g., power-on) or operation (e.g., when the memory device 120 is in operation). For example, the scanning operation may be performed at initialization in response to a power event (e.g., power-on) of the memory device 120. For example, when the system 100 and / or the memory device 120 is powered on, the controller 110 may write a (e.g., predetermined) data pattern to the memory device 120, read the data pattern from the memory device 120, and determine whether the data pattern matches. Although the embodiment is not limited, the data pattern written to the memory device 120 may be a predetermined data pattern, which may be all "0" or "1", or include both bit values ​​"0" and "1". The determination that the two data patterns do not match may indicate one or more hard bit errors, and the controller 110 may repair those physical addresses (e.g., rows or row portions) indicated as having hard bit errors in response (e.g., by remapping the logical address to exclude the physical address).

[0022] In some embodiments, the scan operation may be performed "on the fly" (e.g., as a background operation that may be performed independently of the host 102). In some embodiments, the scan operation may be performed with the ECC feature of the controller 110 disabled so as not to confuse hard bit errors with soft bit errors. For example, with the ECC feature disabled, a data pattern may be read from the memory device without correcting soft bit errors.

[0023] All memory banks (e.g., Figure 2 1 ) performs (e.g., repeatedly) a scan operation on the memory device 120. After the scan operation and / or repair performed by the controller 110, the controller 110 may report the total size of the memory device 120 (e.g., the size of the memory device 120 excluding those "bad" memory cells) to the host 102 (e.g., BIOS / SOC).

[0024] Figure 2 2 is a block diagram of a system 200 including a controller 210 and a memory device 220 according to several embodiments of the present disclosure. The controller 210 (together with a repair component 212 and a memory 214) and the memory device 220 (together with a memory 216) may be similar to Figure 1 Controller 110 (along with repair component 112 and memory 114) and memory device 120 (along with memory 216) are illustrated in FIG.

[0025] Memory device 220 (eg, memory die) may include a number of memory banks 221-1, 221-2, ..., 221-M (eg, collectively referred to as memory bank 221), which may include a memory array 230 including multiple rows and columns of memory cells and sensing circuitry 223. Figure 22, but each of the memory banks 221 may include control circuitry (e.g., a memory bank processor) to control and / or coordinate the performance of memory operations in response to instructions received from the control logic 224. In some embodiments, for example, each of the memory banks 221 may be individually addressed by the control logic 224.

[0026] The array 230 may include memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines (which may be referred to herein as data lines or digital lines). The memory array 230 may include various / different types of memory cells. For example, the memory array 230 may be FeRAM, PCRAM, RRAM, MRAM, DRAM, and STTRAM, etc. As an example, a FeRAM memory may include a ferroelectric capacitor and may perform bit storage based on a voltage or amount of charge applied thereto. In such examples, relatively small and relatively large voltages allow the FeRAM memory to exhibit characteristics similar to normal dielectric materials (e.g., dielectric materials with relatively high dielectric constants), but at various voltages between such relatively small and large voltages, the FeRAM memory may exhibit polarization reversal that produces nonlinear dielectric behavior.

[0027] Memory device 220 may include address circuitry 222 to latch address signals for data provided by I / O circuitry 228 via input / output “I / O” bus 107 (e.g., data bus and / or address bus) (e.g., provided to external ALU circuitry and DRAM DQs via local I / O lines and global I / O). For example, an internal I / O bus may transfer data between memory banks 221 and I / O pins (e.g., DQs).

[0028] Address signals from address circuitry 222 may be provided to row decode circuitry 226, column decode circuitry 225, and / or bank control logic 229. Bank control logic 229 may activate row decode circuitry 226 and / or column decode circuitry 225 corresponding to the bank address received from address circuitry 222.

[0029] In response to being activated by the bank control logic 229, the column decoding circuitry 225 and the row decoding circuitry 226 may each decode a signal received from the address circuitry 222 to access the memory array 230. The row decoding circuitry 226 may include logic (e.g., multiplexer circuitry) that may selectively couple the shared I / O lines to a subset of the sensing components corresponding to the row address and / or bank address received from the address circuitry 222 and the bank control logic 229, respectively. The column decoding circuitry 225 may latch the column address and apply the latched column address to a decoder of the column decoding circuitry 225.

[0030] Address signals are received by address circuitry 222 and decoded by row decoder 226 and column decoder 225 to access memory array 230. Data can be read from memory array 230 by sensing voltage and / or current changes on sense lines (digit lines) using sense circuitry 223. Sense circuitry 223 can read and latch data of various data sizes (e.g., a physical sub-page, a physical page, or a row of memory cells) from memory array 230. Although Figure 2 2, but the sensing circuit system 223 may further include sense amplifiers, buffers, etc. that may be used to read and latch data. The I / O circuit system 228 may be used to communicate bidirectional data with the controller 202 via the data bus 207 (e.g., a 64-bit wide data bus). The number of circuits (e.g., sense amplifiers, buffers, etc.) of the sensing circuit system 223 may correspond to the size of a row of memory cells of the array 230. For example, if a row of the array has a size of 2kB, the sensing circuit system 223 may include 16k sense amplifiers (e.g., 2kB*8 bits / byte=16k). In another example, if a row of the array has a size of 8kB, the sensing circuit system 223 may include 64k sense amplifiers (e.g., 8kB*8 bits / byte=64k).

[0031] The control logic 224 may decode signals (e.g., commands) provided from the controller 210 via the control bus 203. These signals may include chip enable signals, write enable signals, and / or address latch signals, which may be used to control operations performed on the memory array 230, including data sensing, data storage, data movement (e.g., copying, transferring, and / or transmitting data values), data writing, and / or data erasing operations, among other operations. In addition, status and / or exception information may be provided from the control logic 224 on the memory device 220 to the controller 210 and / or logic resources via the out-of-band bus 205. The control logic 224 may be a state machine, a sequencer, or some other type of controller.

[0032] Each memory bank 221 may be the smallest unit that can independently execute commands from the control logic 224 (e.g., one at a time). The memory banks 221-1, ..., 221-M may be accessed substantially simultaneously. As used herein, the term "substantially" means that the characteristic need not be absolute, but close enough to achieve the advantages of the characteristic. For example, "substantially simultaneously" is not limited to operations performed absolutely simultaneously, and may include timing that is expected to be simultaneous but may not be precisely simultaneous due to manufacturing limitations. For example, due to the read / write delays that various interfaces (e.g., LPDDR5 and PCIe) may exhibit, the media controllers utilized "substantially simultaneously" may not start or end at exactly the same time. For example, the memory banks 221 may be accessed so that they write data to the memory banks 221 and / or read data from the memory banks 221 simultaneously, regardless of whether access to the respective memory banks 221 starts or ends before the other.

[0033] As used herein, the term "physical page" may refer to a group of memory cells located on the same row of an array in a contiguous manner. In addition, as used herein, a physical subpage may refer to a portion of memory cells corresponding to a physical page. For example, a physical page having a size of 128 bytes may include two subpages, each having 64 bytes. As further used herein, a physical subpage may be simply referred to as a "subpage." A physical page may have a size corresponding to a logical page. As used herein, a logical page may refer to a portion of memory cells that is allocated by an operating system (e.g., Figure 1 Therefore, the size of the logical page can be defined by the host.

[0034] In some embodiments, the respective sense circuitry 223 may operate with multiple "cuts" that may be independently activated to access a (e.g., physical) sub-page of the memory array 230. For example, each slice may include those circuits, such as sense amplifiers, buffers, master input / output (MIO) of the I / O circuitry 228, etc., that may be activated to access the respective sub-page. For example, when accessing a single sub-page, the respective slice corresponding to the sub-page may be activated, while the other slices may remain deactivated (e.g., maintaining the deactivated states of the other slices). This may provide the benefit of accessing the memory array 230 at a finer granularity (e.g., in units of sub-pages) than those DRAM devices in a manner that reduces the power consumption associated with each read access (e.g., to the memory bank 221). For example, consider an example in which a DRAM page of size 128 bytes is stored on a row of memory cells of size 8kB. In this example, accessing a single DRAM page may still involve reading 8 kB (corresponding to a row) into a sense amplifier and / or read buffer, from which only the single DRAM page is further transferred to control logic (e.g., control logic 224), a controller (e.g., controller 210), and / or a host (e.g., host 102). In contrast, in several embodiments, accessing a sub-page (e.g., having a size of 64 bytes) may involve activating a portion of the sense circuitry 223 (e.g., sense amplifiers, read buffers, MIOs, etc.) in order to read 64 bytes (corresponding to a sub-page) without having to read data from an entire (e.g., entire) row of memory cells.

[0035] Therefore, repair can be completed in units of subpages rather than in units of a row of memory cells. For example, when a hard bit error is detected in one or more subpages on a row of memory cells (thereby making it a "bad" subpage), those "good" subpages on the row can still be used and mapped to the logical page. These "good" subpages can usually be mapped to the logical page together with other subpages on different (e.g., spare) storage bodies and / or rows of memory cells on different storage bodies. For example, a logical page can be mapped to a "good" subpage in a first storage body, and to a "good" (e.g., spare) subpage in a second storage body. In this example, read access to the logical page can be completed by accessing two subpages (e.g., each having 64 bytes) from two different storage bodies 221 substantially at the same time. In some embodiments, the control logic 224 can mark the "bad" subpage as unavailable (alternatively referred to as a "retired subpage").

[0036] In some embodiments, a logical page may be mapped to two subpages (e.g., but in different rows) of the same memory bank 221. In this example, the two subpages on the same memory bank 221 may be accessed serially (e.g., "back-to-back") rather than substantially simultaneously.

[0037] Although the memory banks 221 may be accessed substantially simultaneously, accessing one memory bank as well as the other memory bank may be delayed if the memory bank is already open (e.g., currently executing another command from the control logic 224). This may be taken into account when mapping logical addresses to physical addresses in the memory banks 221 and / or scheduling policies between command executions (e.g., by the control logic 224 and / or the controller 210) to reduce latency when accessing the memory banks 221 for a single read / write access.

[0038] Figure 3 321 -1, . . . , 321 -X (collectively referred to as storage banks 321 ) of a memory device 320 according to several embodiments of the present disclosure. The memory device 320 and the storage banks 321 may be similar to Figure 2 In addition, the controller 310 may be similar to the memory device 220 and the storage body 221 in FIG. Figure 2 Controller 210 in.

[0039] At 332, a logical page (e.g., having a size of 128 bytes) is mapped to a physical page (e.g., having a size of 128 bytes) of memory bank 321-1. However, embodiments are not limited to a particular size that a logical page or physical page may have. For example, a logical / physical page may have a size of 64 bytes, 256 bytes, etc. In some embodiments, a physical page may correspond to a single row of memory cells of a corresponding memory bank 321. Thus, an access request received at controller 310 to access a physical page (e.g., a 128-byte physical page) from memory bank 321 may be implemented by accessing memory bank 321-1 to obtain data (e.g., corresponding to a page size of 128 bytes).

[0040] At 334, as a result of the repair performed on memory bank 321, a logical page (e.g., having a size of 128 bytes) is mapped to physical sub-pages (e.g., each having a size of 64 bytes) located at memory banks 321-1 and 321-X, respectively. The repair procedure can reduce the number of "good" memory cells that would otherwise be wasted via existing memory repair methods that can remap entire rows of cells. In several embodiments, accesses to different sub-pages (e.g., in different memory banks) mapped to the same logical page can be performed not only in a substantially simultaneous manner, but also in a deterministic manner. In other words, accesses to sub-pages mapped to the same logical page are guaranteed to occur within a predictable and known timing window.

[0041] Figure 4 is a diagram illustrating a logical-to-physical (L2P) table 440 indicating logical pages that are remapped in response to a repair performed according to several embodiments of the present disclosure. The L2P table 440 may be stored in the memory 114 and managed by the controller 110, or stored in the memory 116 and managed by the control logic 224.

[0042] Rows 442-1, ..., 442-Y of table 440 correspond to logical-to-physical mapping entries, respectively, where each logical page is mapped to a physical page that may correspond to one or more physical pages (e.g., Figure 2 As used herein, the term "device page" refers to memory cells that can be accessed together as a unit accessed by a host. Although a device page may have a size corresponding to the size of a logical page, the memory cells corresponding to the device page may be distributed over different rows of memory cells, so that a logical page mapped to one device page can be accessed by accessing different rows of memory cells. When a device page is "mapped" to a single physical page or multiple physical pages (e.g., portions thereof), the logical page mapped to this device page may also be referred to as being mapped to a single physical page or multiple physical pages (e.g., portions thereof).

[0043] As in Figure 4 As described in Figure 4 , the logical page "4012" (e.g., having a size of 128 bytes) shown in FIG. 1 is mapped to a device page corresponding to the physical page "4201", row 442-2 indicates that the logical page "4201" is mapped to a device page having two different sub-pages (e.g., as a result of repair), which may be on different banks 221, and row 442-Y indicates that the logical page "7890" is mapped to a device page corresponding to the physical page "9999". More specifically, as shown in FIG. Figure 4 The logical page "4201" shown in the figure is mapped to half of the physical page "4304" on the storage body "0" (e.g., a sub-page with 64 bytes) and half of the physical page "7890" on the storage body "1" (e.g., a sub-page with 64 bytes).

[0044] although Figure 4, but each entry includes one or more bits indicating whether the corresponding logical page is "repaired" (e.g., so that the logical page is mapped to multiple sub-pages instead of being mapped to a single physical page). For example, a bit with a first bit value (e.g., "0") may indicate that the corresponding logical page is repaired, while a bit with a second bit value (e.g., "1") may indicate that the corresponding logical page has not been repaired (e.g., so that the logical page is mapped to a single physical page).

[0045] If a storage bank (for example, Figure 2 221) does not have more small portions (e.g., subpages) available for repair, then the last device page can be used for repair. For example, consider a memory device (e.g., Figure 2 ), the device pages each have 10,000 physical pages, and two of the 10,000 physical pages (e.g., physical pages “4012” and “5048”) are partially determined to be unreliable. In this example, the logical page previously mapped to physical page “4012” may be mapped to a subpage of “4012” and a subpage of “5048” that is still valid (e.g., not unreliable). In addition, the logical page previously mapped to physical page “5048” may be mapped to physical page “10,000” that previously corresponded to the last device page. Due to this remapping procedure performed using the last device page, the total number of device pages is reduced to 9,999, and the last device page “10,000” that existed before the remapping is eliminated.

[0046] Although specific embodiments have been illustrated and described herein, it will be appreciated by those skilled in the art that arrangements calculated to achieve the same results may be substituted for the specific embodiments shown. The present disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. It should be appreciated that the above description has been made in an illustrative and non-restrictive manner. After reviewing the above description, those skilled in the art will understand the combination of the above embodiments and other embodiments not explicitly described herein. The scope of one or more embodiments of the present disclosure includes other applications using the above structures and processes. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the attached claims and the full range of equivalents enjoyed by such claims.

[0047] In the foregoing detailed description, some features are grouped in a single embodiment for the purpose of simplifying the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the disclosed embodiments of the disclosure must use more features than those explicitly recited in each claim. Rather, as the appended claims reflect, the inventive subject matter resides in less than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

1. A method comprising: determining whether at least a portion of one or more arrays of memory cells of a memory device is bad; as well as In response to one or more first memory cells of a first row of memory cells of a first array of memory cells being determined to be bad, repairing the array by remapping one or more logical pages to: one or more second memory cells of said first row of memory cells; and One or more additional memory cells.

2. The method according to claim 1, wherein: The one or more additional memory cells are located on a second row of memory cells further on a second array of memory cells; and The method further includes accessing data corresponding to the one or more logical pages by accessing the first array and the second array of memory cells substantially simultaneously.

3. The method of any one of claims 1 to 2, further comprising performing a scan operation on the array to determine whether the at least the portion of the array of memory cells is bad by: writing corresponding data patterns to portions of the array of memory cells; reading the data pattern from the plurality of portions; as well as A determination is made as to whether the data pattern read from the plurality of portions matches the data pattern written to the plurality of portions to further determine whether the at least the portion of the array of memory cells is bad.

4. The method of claim 3, further comprising performing the scanning operation with an error correction code (ECC) feature disabled to not correct soft bit errors on the data pattern read from the plurality of portions. 5 . The method of claim 3 , further comprising performing the scan operation as a background operation in response to a power event of the memory device or during operation of the memory device.

6. A device comprising: an array of memory cells; and a controller coupled to the array of memory cells, the controller configured to, in response to one or more first memory cells of a first row of memory cells of the array being determined to be bad, remap one or more logical pages to: one or more second memory cells of said first row of memory cells; and One or more spare memory cells of the second row of memory cells.

7. The apparatus of claim 6, further comprising sensing circuitry coupled to the array of memory cells, the controller being configured to, in order to access the one or more second memory cells or the one or more spare memory cells mapped to the one or more logical pages: activating a first portion of the sensing circuitry coupled to the one or more second memory cells or the one or more spare memory cells; and A second portion of the sensing circuitry not coupled to the one or more second memory cells or the one or more spare memory cells is maintained in a deactivated state.

8. The apparatus according to any one of claims 6 to 7, wherein: The array of memory cells is one of a plurality of arrays of memory cells corresponding to a plurality of memory banks, respectively; and The first and the second rows of memory cells are located in a first memory bank of the plurality of memory banks.

9. The apparatus according to any one of claims 6 to 7, wherein: The array of memory cells is one of a plurality of arrays of memory cells corresponding to a plurality of memory banks, respectively; and The first row of memory cells is located in a first memory bank of the plurality of memory banks, and the second row of memory cells is located in a second memory bank of the plurality of memory banks.

10. The apparatus of any one of claims 6-7, wherein the one or more first memory cells and the one or more second memory cells correspond to a physical page having a dynamic random access memory (DRAM) page size.

11. The apparatus of any one of claims 6-7, further comprising sensing circuitry coupled to the array of memory cells, the sensing circuitry comprising at least a plurality of sense amplifiers respectively coupled to the array of memory cells.

12. A device comprising: a plurality of arrays of memory cells, each corresponding to a plurality of memory banks; and a controller coupled to the array of memory cells; The controller is configured to access the array of memory cells according to a double data rate (DDR) protocol; wherein the controller is further configured to, in response to one or more first memory cells of a first row of memory cells of a first memory bank being determined to be bad, remap the one or more logical pages to: one or more second memory cells of the first row of memory cells of the first bank; and One or more third memory cells of the second row of memory cells of the second memory bank.

13. The apparatus of claim 12, wherein the controller is further configured to store a logical-to-physical (L2P) table indicating mappings between logical addresses and physical addresses of the plurality of arrays.

14. The apparatus of claim 13, wherein the controller is configured to store the L2P table in a cache of the controller.

15. The apparatus of claim 13, wherein the L2P table further comprises a number of bits, each of the number of bits indicating whether a logical address of a corresponding entry is mapped to a different row of memory cells.

16. The apparatus of claim 12, further comprising a memory device comprising the plurality of arrays of memory cells, and wherein: The controller is configured to communicate with the memory device according to the DDR protocol; and The memory device includes control logic configured to access the plurality of arrays of memory cells in response to commands from the controller.

17. The apparatus of claim 16, wherein the control logic is configured to store a logical-to-physical (L2P) table indicating mappings between logical addresses and physical addresses of the plurality of arrays.

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