Semiconductor substrate, method and apparatus for manufacturing semiconductor substrate, and method for manufacturing semiconductor device

Abstract

The present invention is provided with: a template substrate including a first seed region and a growth suppression region arranged side by side in a first direction; and a first semiconductor section positioned above the template substrate. The first semiconductor section has: a first base section positioned on the first seed region; and a first wing portion connected to the first base portion and facing the growth suppression region with a first gap therebetween, the first wing portion including a wing end located above the growth suppression region, the ratio of the width of the first gap in the first direction to the thickness under the wing end being 5.0 or more.

Description

Technical Field

[0001] The present disclosure relates to semiconductor substrates and the like. Background Art

[0002] The development of technology for forming semiconductor devices using GaN (gallium nitride) on silicon substrates and sapphire substrates is being promoted. However, if a GaN layer is formed on a different substrate, the thickness of the GaN layer on the sapphire substrate will be 10 8 cm -2 The defect density is about 10. 9 cm -2 The defect density of about 100% generates through dislocations from the interface of heterogeneous materials (the interface between the substrate and the formed film), which will reduce the characteristics and reliability of the device formed thereon. Therefore, as a technology for forming a GaN layer with a low defect density on a heterogeneous substrate, the ELO (Epitaxial Lateral Overgrowth) method is being studied. For example, a mask pattern in which a GaN layer is not grown can be formed on a base substrate including a heterogeneous substrate and a seed layer (GaN layer, etc.), and the GaN layer is grown laterally on the mask part by using the seed layer exposed in the opening of the mask part as the growth starting point, thereby reducing the defect density of the GaN layer on the mask part (Patent Document 1). However, due to the contact between the laterally grown GaN layer and the mask part, depending on the film forming conditions, there will be a problem of reduced flatness of the GaN layer.

[0003] In Patent Document 2, a semiconductor layer is grown laterally on the void, and a device layer (semiconductor stacked film) is also formed on the lower surface (back surface) of the semiconductor layer.

[0004] Prior Art Literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2013-251304

[0007] Patent Document 2: JP 2017-535051 Summary of the invention

[0008] Problems to be solved by the invention

[0009] The technology of Patent Document 2 has a problem that it is difficult to form a wide device layer.

[0010] Means for solving problems

[0011] The semiconductor substrate involved in the present disclosure comprises: a template substrate including a first seed crystal region and a growth inhibition region arranged side by side in a first direction; and a first semiconductor portion located above the template substrate, the first semiconductor portion having: a first base portion located on the first seed crystal region; and a first wing portion connected to the first base portion and facing the growth inhibition region across a first gap, the first wing portion including a wing end located above the growth inhibition region, and a ratio of a width of the first gap in the first direction to a thickness below the wing end being greater than 5.0.

[0012] Effects of the Invention

[0013] A wide device layer (functional layer) can be formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a plan view showing the structure of a semiconductor substrate according to the present embodiment.

[0015] Figure 2 It is a cross-sectional view showing the structure of a semiconductor substrate according to the present embodiment.

[0016] Figure 3 It is a cross-sectional view showing the structure of a semiconductor substrate according to the present embodiment.

[0017] Figure 4 It is a cross-sectional view showing the structure of a semiconductor substrate according to the present embodiment.

[0018] Figure 5 It is a cross-sectional view showing the structure of a semiconductor substrate according to the present embodiment.

[0019] Figure 6 It is a cross-sectional view showing the structure of a semiconductor substrate according to the present embodiment.

[0020] Figure 7 It is a cross-sectional view showing the structure of a semiconductor substrate according to the present embodiment.

[0021] Figure 8 It is a cross-sectional view showing the structure of a semiconductor substrate according to the present embodiment.

[0022] Fig. 9 It is a plan view showing the structure of a semiconductor substrate according to the present embodiment.

[0023] Fig. 10A This is a flowchart showing a method for manufacturing a semiconductor substrate according to the present embodiment.

[0024] Fig. 10B This is a flowchart showing a method for manufacturing a semiconductor substrate according to the present embodiment.

[0025] Fig.11 It is a block diagram showing a semiconductor substrate manufacturing apparatus according to the present embodiment.

[0026] Fig.12 This is a cross-sectional view showing the structure of the semiconductor substrate according to Example 1.

[0027] Fig.13 It is a cross-sectional view showing the method for manufacturing the semiconductor substrate according to the first embodiment.

[0028] Fig.14 These are Raman spectra of the base and wing of the ELO layer according to the comparative example.

[0029] Fig.15 1 and 2 are Raman spectra of the base and wing of the ELO layer (semiconductor portion) according to Example 1.

[0030] Fig.16 It is a top view of the semiconductor substrate including the upper layer portion.

[0031] Fig.17 It is a cross-sectional view of a semiconductor substrate including an upper layer portion.

[0032] Fig.18 This is a top view showing the method of separating the elements in Example 1.

[0033] Fig.19 This is a cross-sectional view showing the method of element separation in Example 1.

[0034] Fig. 20 It is a schematic diagram showing the structure of the electronic device involved in Example 1.

[0035] Fig.21 It is a cross-sectional view showing the structure of a semiconductor substrate of Example 4.

[0036] Fig. 22 This is a graph showing the results of XRD reflection scanning measurement of the ELO layer of the comparative example.

[0037] Fig.23 This is a graph showing the results of XRD reflection scanning measurement of the semiconductor portion in Example 1.

[0038] Fig.24 It is a top view showing the structure of the semiconductor substrate of Example 5.

[0039] Fig.25 This is a cross-sectional view showing the structure of a semiconductor substrate of Example 5.

[0040] Fig.26 Yes means Fig.25 A cross-sectional view of a method for manufacturing a semiconductor substrate.

[0041] Fig. 27 Yes means Fig.25 A cross-sectional view of a method for manufacturing a template substrate.

[0042] Fig.28 It is a cross-sectional view showing a method for manufacturing a template substrate.

[0043] Fig.29 It is a cross-sectional view showing a method for manufacturing a template substrate.

[0044] Fig.30 It is a cross-sectional view showing the structure of the semiconductor substrate of Example 6.

[0045] Fig.31 It is a cross-sectional view showing the structure of the semiconductor substrate of Example 6.

[0046] Fig.32 It is a cross-sectional view showing the structure of the semiconductor substrate of Example 7.

[0047] Fig.33 It is a flowchart showing the manufacturing method of the semiconductor device of Example 8.

[0048] Fig.34 It is a cross-sectional view showing the manufacturing method of the semiconductor device of Example 8. DETAILED DESCRIPTION

[0049] Figure 1 It is a plan view showing the structure of a semiconductor substrate according to the present embodiment. Figure 2 is a cross-sectional view showing the structure of a semiconductor substrate according to this embodiment. Figure 1 as well as Figure 2 As shown, the semiconductor substrate 10 includes: a template substrate TS including a first seed region S1 and a growth inhibition region (non-seed region) DA arranged side by side in a first direction X1; and a first semiconductor portion 8A located above the template substrate TS. The first semiconductor portion 8A includes: a first base B1 located on the first seed region S1; and a first wing F1 connected to the first base B1 and facing the growth inhibition region DA across a first gap J1. The first wing F1 includes: an edge (wing end) E1 located above the growth inhibition region DA. The ratio of the width WJ of the first gap J1 in the first direction X1 to the thickness TJ (the aspect ratio of the gap) is 5.0 or more. In this way, a wide device layer (functional layer) can be formed on the first wing F1. The thickness TJ can be the thickness below the wing end E1 of the first gap J1 (the length in the c-axis direction between the lower surface of the wing end E1 and the surface of the template substrate TS). The width of the first wing portion F1 in the first direction X1 may be 5.0 times or more the thickness TJ of the first gap J1.

[0050] The template substrate TS may have a mask pattern 6, which includes: a mask portion 5 that functions as a growth inhibition region DA; and a first opening portion K1 that functions as a first seed crystal region S1 (exposing the upper surface of the seed crystal 3 as the first seed crystal region S1). Specifically, the surface (upper surface) of the mask portion 5 becomes the growth inhibition region DA. The template substrate TS may include: a main substrate 1 (heterogeneous substrate) having a lattice constant different from that of the first semiconductor portion 8A; and a seed crystal portion 3. The template substrate TS may have a ridge R on the upper surface side, and the first seed crystal region S1 is provided on the upper surface of the ridge R. Specifically, the surface (upper surface) of the seed crystal portion 3 becomes the first seed crystal region S1.

[0051] The so-called first gap J1 is a space sandwiched by the growth inhibition area DA and the first wing F1. The direction from the main substrate 1 to the first semiconductor portion 8A is set to "upward". Observing an object with a line of sight parallel to the normal direction of the semiconductor substrate 10 (including perspective) is called "top view". The first seed crystal region S1 (the surface of the seed crystal portion 3) and the growth inhibition area DA (the surface of the mask portion 5) are located in different positions in the thickness direction (up and down direction) of the substrate, and can be arranged side by side in the first direction X1 (the direction orthogonal to the thickness direction of the substrate) when viewed from above.

[0052] The first semiconductor portion 8A includes a nitride semiconductor as a main component. Nitride semiconductors can be characterized, for example, as AlxGayInzN (0≤x≤1; 0≤y≤1; 0≤z≤1; x+y+z=1), and specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). GaN-based semiconductors are semiconductors containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN.

[0053] The first semiconductor portion 8A may be a doped type (e.g., n-type containing a donor) or a non-doped type. The so-called semiconductor substrate refers to a substrate containing a semiconductor, and the main substrate 1 of the template substrate TS may contain a semiconductor (e.g., silicon, silicon carbide) or may not contain a semiconductor. As the main substrate 1 not containing a semiconductor, for example, there is a sapphire substrate. The main substrate 1 may be a self-supporting substrate (wafer). Sometimes the main substrate 1 and the seed crystal portion 3 are included and referred to as a base substrate. Sometimes the template substrate TS including the base substrate and the mask pattern 6 is referred to as a growth substrate.

[0054] The first direction X1 may be the a-axis direction (<11-20> direction) of the first semiconductor portion 8A (nitride semiconductor such as GaN). The second direction X2 may be the m-axis direction (<1-100> direction) of the first semiconductor portion 8A. The thickness direction Z of the semiconductor substrate 10 may be the c-axis direction (<1-100> direction) of the first semiconductor portion 8A. <0001> direction).

[0055] The first semiconductor portion 8A can be formed by the ELO (Epitaxial Lateral Overgrowth) method using the seed crystal portion 3 exposed under the first opening K1 as a starting point. The base portion B1 located above the first opening K1 in the first semiconductor portion 8A becomes a dislocation inheritance portion with many threading dislocations, and the first wing portion F1 located above the mask portion 5 becomes a low-defect portion with a smaller threading dislocation density than the dislocation inheritance portion. The second semiconductor portion 8C uses the seed crystal portion 3 exposed under the second opening K2 as a starting point, grows laterally on the mask portion 5, and stops growing before joining the first semiconductor portion 8A.

[0056] In this way, by forming the edge E1 of the first wing F1 above the growth suppression area DA, the aspect ratio of the first gap J1 (the ratio of the width W1 in the first direction X1 to the thickness TJ) is set to 5.0 or more, and the first wing F1 with high crystallinity (low defect density) and wide width can be quickly formed, and the flatness of the first wing F1 can be improved. In addition, when the upper layer portion (device layer, functional layer) including the active layer is formed on the first semiconductor portion 8A, the phenomenon that the upper layer material is wrapped around the back of the first wing F1 can be suppressed. The upper layer portion may include, for example, a nitride semiconductor layer (including the active layer).

[0057] The semiconductor substrate 10 may include: a second semiconductor portion 8C located above the template substrate TS. The template substrate TS may include: a second seed crystal region S2 adjacent to the first seed crystal region S1 across the growth inhibition region DA when viewed from above. The second semiconductor portion 8C includes: a second base portion B2 located on the second seed crystal region S2; and a second wing portion F2 connected to the second base portion B2 and facing the growth inhibition region DA across the second gap J2, the first wing portion F1 and the second wing portion F2 are arranged side by side in the first direction X1 across the gap GP, and the second gap J2 may have a ratio of a width WJ in the first direction X1 to a thickness TJ of 5.0 or more. The thickness TJ may be the thickness below the wing end E2 of the second gap J2.

[0058] In the following, the first semiconductor portion 8A and the second semiconductor portion 8C are sometimes collectively represented as the semiconductor portion (semiconductor layer) 8, the first wing portion F1 and the second wing portion F2 are collectively represented as the wing portion F, the first base portion B1 and the second base portion B2 are collectively represented as the base portion B, the first gap J1 and the second gap J2 are collectively represented as the gap J, the first opening portion K1 and the second opening portion K2 of the mask pattern 6 are collectively represented as the opening portion K, and the first seed crystal region S1 and the second seed crystal region S2 are collectively represented as the seed crystal region S.

[0059] The ratio of the width of the first wing F1 in the first direction X1 to the thickness may be 2.0 or more, 5.0 or more, 10 or more, 20 or more, 50 or more, 100 or more, or 200 or more. By setting the ratio of the thickness of the first wing F1 to the width to 1 / 2 or less, the deviation between the c-axis direction of the first base B1 and the c-axis direction of the tip of the first wing F1 can be set to 0.2° or less. The width of the first wing F1 in the first direction X1 may be 7.0 [μm] or more, 10.0 [μm] or more, 20.0 [μm] or more, 40.0 [μm] or more, or 100 [μm] or more. The width of the first wing F1 in the first direction X1 may be 80.0 [μm] or less. Thus, the possibility of the semiconductor portion 8 warping in the substrate direction due to gravity can be reduced. The thickness of the first wing portion F1 may be, for example, 10.0 [μm] or less, 5.0 [μm] or less, or 2.0 [μm] or less. Figure 2 As shown in FIG. 1 , the width of the gap GP may be greater than the thickness of the first gap J1. The ratio of the width of the first wing F1 to the width of the first base B1 may be greater than 3.0. The thickness of the first gap J1 may be less than 3.0 [μm]. The thickness of the first wing F1 and the first base B1 may be the same. The thickness of the mask portion 5 may be less than 1 [μm] or less than 50 [nm]. The seed portion 3 may contain 2×10 18 / cm 3 The above argon or oxygen nitride semiconductors (AlN, AlON, GaN-based semiconductors, etc.).

[0060] like Figure 1 As shown, the first seed crystal region S1 and the growth inhibition region DA may each be shaped such that the second direction X2 perpendicular to the first direction X1 is the long side direction. The main substrate 1 is a silicon substrate, a sapphire substrate or a silicon carbide substrate, and the first semiconductor portion 8A may include a nitride semiconductor (e.g., a GaN-based semiconductor).

[0061] like Figure 2As shown, the template substrate TS has a ridge R on the upper surface side, and the seed crystal portion 3 may be included in the ridge R. The upper surface of the ridge R may be composed of the seed crystal portion 3, and the side surface of the ridge R may be composed of the mask portion 5. That is, the upper surface of the ridge R may have the seed crystal portion 3, and the side surface of the ridge R may have the mask portion 5. In addition, the seed crystal portion 3 may be provided on the upper surface of the ridge R, and the side surface of the ridge R may be composed of the mask portion 5 without the seed crystal portion 3. The seed crystal portion 3 may be partially arranged on the ridge R, and may not be arranged under the mask portion 5.

[0062] The main substrate 1 includes a protrusion Q on the upper surface side, and the seed crystal portion 3 can be located on the protrusion Q. The side surface of the ridge R may not be in contact with the first wing portion F1. The side surface of the ridge R may face the first gap J1 as a whole. As a result, the contact area between the ridge R and the wing portion F1 is reduced, which can reduce the defects of the wing portion F1. The seed crystal portion 3 may not be arranged under the mask portion 5. The compound semiconductor contained in the first semiconductor portion 8A is a GaN-based semiconductor, and the first gap J1 may have a ratio of width to thickness of more than 20.0. The first semiconductor portion 8A may have two pairs of first wing portions F1 extending from the first base portion B1 to the first direction X1 and the opposite direction thereof.

[0063] Figure 3 is a cross-sectional view showing the structure of a semiconductor substrate according to this embodiment. Figure 3 As shown, the ridge portion R may include a buffer portion 2 and a seed portion 3. In this case, the base portion composed of the buffer portion 2 and the seed portion 3 may be arranged in a stripe shape.

[0064] Figure 4 is a cross-sectional view showing the structure of a semiconductor substrate according to this embodiment. Figure 4 As shown, the thickness of the first wing portion F1 may be greater than the thickness of the first base portion B1. The side surface of the ridge portion R (mask portion 5) may also be in contact with the first wing portion F1. Since the gap J1 can be formed if the first wing portion F1 does not contact the growth inhibition area DA (mask portion 5), there is no problem.

[0065] Figure 5 is a cross-sectional view showing the structure of a semiconductor substrate according to this embodiment. Figure 5 As shown, the ridge R may be located on the flat upper surface of the main substrate 1 .

[0066] Figure 6 is a cross-sectional view showing the structure of a semiconductor substrate according to this embodiment. Figure 6 As shown, the buffer portion 2 includes a lower portion 2a and an upper portion 2b. The lower portion 2a is planar. The seed crystal portion 3 and the upper portion 2b may not be disposed under the mask portion 5, but the lower portion 2a may be disposed. The ridge portion R may include the upper portion 2b of the buffer portion 2.

[0067] Figure 7 is a cross-sectional view showing the structure of a semiconductor substrate according to this embodiment. Figure 7 As shown, the first wing portion F1 can be divided into a plurality of portions PA arranged side by side in the second direction X2 orthogonal to the first direction X1.

[0068] Figure 8 It is a cross-sectional view showing the structure of a semiconductor substrate according to the present embodiment. Fig. 9 FIG. 1 is a top view showing the structure of a semiconductor substrate according to the present embodiment. Figure 8 as well as Fig. 9 As shown, the semiconductor substrate 10 is located above the first semiconductor portion 8A and may include an upper layer portion 9 including an active layer and a p-type layer. The upper layer portion 9 may be provided with an anode EA and a cathode EC.

[0069] Fig. 10A : is a flowchart showing a method for manufacturing a semiconductor substrate according to the present embodiment. The method for manufacturing a semiconductor substrate according to the present embodiment includes: step S10, preparing a template substrate TS including a first seed crystal region S1 and a growth inhibition region DA arranged side by side in a first direction X1; and step S20, growing a first semiconductor portion 8A having a first base B1 located on the first seed crystal region S1 and a first wing F1 connected to the first base B1 and facing the growth inhibition region DA across a first gap J1, so that the width of the first wing F1 in the first direction X1 becomes 5.0 times or more the thickness of the first gap J1. Step S30 may also be performed, in which the growth of the first wing F1 and the second wing F2 growing in a direction close to the first wing F1 is stopped before the first wing F1 and the second wing F2 growing in a direction close to the first wing F1 meet. The template substrate TS may have a seed crystal portion 3 including the first seed crystal region S1, and the seed crystal portion 3 is formed by sputtering.

[0070] Fig. 10B 1 is a flow chart showing a method for manufacturing a semiconductor substrate according to the present embodiment. Fig. 10B As shown, step S20B may be performed, in which, after step S10, a first semiconductor portion 8A having a first base portion B1 located on the first seed crystal region S1 and a first wing portion F1 connected to the first base portion B1 and facing the growth inhibition region DA across a first gap J1 is grown so that a width (Ws) of the first semiconductor portion 8A (including the entirety of the two wings) in the first direction X1 becomes more than 5.0 times the thickness (Th) of the first semiconductor portion 8A.

[0071] Fig.11FIG. 10 is a block diagram showing a semiconductor substrate manufacturing apparatus according to the present embodiment. The semiconductor substrate manufacturing apparatus 50 includes: an apparatus M10 for performing step S10 of FIG. 10 ; Fig. 10A Process S20A ( Fig. 10B and a control device MC for controlling the device M10 and the device M20. The device M20 may be a MOCVD device, and the control device MC may perform the step S30 via the device M20.

[0072] [Example 1]

[0073] As the host substrate 1 , a silicon substrate, a silicon carbide substrate (4H—SiC, 6H—SiC substrate), a sapphire substrate, a nitride substrate (GaN, AlN substrate, etc.), a ScMgAlO substrate, or the like can be used.

[0074] The seed crystal portion 3 is formed above the main substrate 1, and the semiconductor portion 8 becomes the starting point of growth. The seed crystal portion 3 only needs to be formed in at least a part of the opening portion K (of the mask pattern 6), and can be in a planar shape or a patterned shape (e.g., a stripe shape). As the seed crystal portion 3, a GaN layer, an AlN layer, an AlGaN layer, an AlInN layer, AlGaInN, Al, etc. formed at a low temperature (below 500°C) can be used. The thickness of the seed crystal portion 3 is about 10nm to 500nm.

[0075] A buffer portion 2 can be formed between the main substrate 1 and the seed crystal portion 3 (e.g., a GaN layer), and the buffer portion 2 improves the crystallinity and flatness of the seed crystal portion 3. The buffer portion 2 can be planar or patterned (e.g., strip-shaped) to match the seed crystal portion 3. As the buffer portion 2, a GaN layer, an AlN layer, an AlGaN layer, an AlInN layer, AlGaInN, Al, etc. formed at a low temperature (below 500°C) can be used. The thickness of the buffer portion 2 is about 10nm to 500nm. When a silicon substrate is used as the main substrate 1, in order to suppress melting back, it is desired that the buffer portion 2 connected to the silicon substrate does not contain gallium.

[0076] Sometimes the layer between the main substrate 1 and the semiconductor part 8 is called the base layer (including at least one of the buffer part 2 and the seed crystal part 3). As the base layer (such as the seed crystal part 3), a GaN layer can be formed by sputtering. In this case, for example, a sputtering target with gallium nitride as the main component (containing more than 25atm% of gallium) and an oxygen content of less than 5atm% can be used, and the sputtering gas pressure is set to less than 0.3Pa. As a sputtering method, DC sputtering, RF sputtering, AC sputtering, DC magnetron sputtering, ECR (Electron cyclotron Resonance) sputtering, RF magnetron sputtering, PSD (Pulsesputter deposition) method, laser ablation method, etc. can be appropriately selected.

[0077] In order to improve the crystallinity of the entire film, the sputtering target used can have an oxygen content of less than 5 atm%, less than 3 atm%, or less than 1 atm%. As for the purity, it is also expected to be as high as possible, and the content of metal impurities can be less than 0.1% or less than 0.01%. In the case of forming a GaN layer by sputtering, by using a gallium nitride target with a low oxygen content, effects such as surface flatness, improved crystallinity, and suppression of the formation of surface hillocks (protrusions) can be seen.

[0078] When a nitride semiconductor (AlN, GaN, etc.) is formed by sputtering as a base layer, the vacuum degree in the device before film formation can be set to 3×10 -5 Pa or less or 1×10 -5 Pa or less. The organic layer and unevenness on the surface of the base substrate can be removed by pre-treating the base substrate (main substrate, buffered main substrate, etc.) before film formation, so that epitaxial growth can be performed. Specific examples of pre-treatment include reverse sputtering treatment, acid treatment, UV treatment, etc., but reverse sputtering treatment is preferred from the perspective of preventing re-adhesion of impurities, etc. after treatment. The so-called reverse sputtering treatment is a method of cleaning the surface of the base substrate by causing plasmatized atoms to collide with the side of the base substrate. The substrate temperature during film formation can be room temperature, but by performing it in a heated state of the substrate (for example, 400° to 1000°), the film quality can be further improved.

[0079] The power density during discharge can be set to 5W / cm 2 Below or 1.5W / cm 2 The lower limit of power density can be 0.1 W / cm 2 or 0.3W / cm 2 The power density is a value obtained by dividing the power applied during discharge by the area of ​​the sputtering target. If the power density is too high, the raw material may be sputtered from the target in a clustered state.

[0080] In Example 1, the base layer (e.g., seed crystal portion) of the GaN layer is formed by RF sputtering. A gallium nitride target (oxygen content: 0.4 atom%) is used, the film forming pressure is set to 0.1 Pa, and 20 to 40 sccm of nitrogen gas is introduced. In Example 1, argon gas is not used, but of course argon gas can also be introduced. The discharge density is 125 W / cm 2 , the film forming temperature is room temperature.

[0081] When the base layer (including at least one of the buffer portion 2 and the seed crystal portion 3) is formed by sputtering, laser ablation, etc., the internal stress can be controlled from compressive stress to tensile stress by the film forming conditions, so the stress on the semiconductor portion 8 can be controlled. The internal stress can also be controlled by the amount of argon introduced into the base layer. The stress on the semiconductor portion 8 can also be controlled by forming the base layer locally (patterned) on the base substrate.

[0082] The mask pattern 6 is formed on the base substrate using a material that inhibits the longitudinal growth (growth in the c-axis direction) of the nitride semiconductor, and is a mask pattern that realizes lateral growth (for example, growth in the a-axis direction). The opening K of the mask pattern 6 (the exposed portion of the seed crystal portion 3) becomes the growth starting point of the semiconductor portion 8. As materials for the mask portion 5 of the mask pattern 6, silicon nitride, silicon carbide, silicon carbonitride, diamond-like carbon, silicon oxide, silicon nitride oxide, etc., silicon-free titanium nitride, molybdenum nitride, tungsten nitride, tantalum carbide, etc., and further, high melting point metals (molybdenum, tungsten, platinum, etc.) can be cited. The mask portion 5 can be a single-layer film containing one of these materials, or a multilayer film combining these materials. The thickness of the mask portion 5 can be about 5nm to 2μm.

[0083] Fig.12 is a cross-sectional view showing the structure of a semiconductor substrate according to Example 1. Fig.12 In the present invention, a silicon substrate is used as a main substrate 1, and a seed crystal portion 3 is formed on a part of the upper surface of the main substrate 1. A ridge R including the seed crystal portion 3 and the main substrate 1 is formed in a strip shape. A mask portion 5 is formed on the side surface of the ridge R and the surface of the main substrate 1. The mask pattern 6 has a first opening portion K1 at least on a part of the upper surface of the ridge R. A first semiconductor portion 8A is formed on the first opening portion K1, and a first gap J1 is provided under the first wing portion F1. That is, the first wing portion F1 is separated from the mask portion 5 (growth inhibition area DA). The width WJ of the first gap J1 is the distance in the first direction X1 from the side surface of the ridge R to the edge E of the first semiconductor portion 8A. The thickness (height) TJ of the first gap is the distance from the upper surface of the mask portion 5 to the lower surface (back surface) of the first semiconductor portion 8A. The ridge width WR is 5 μm, and the ridge pitch width PR is 55 μm.

[0084] Fig.13 : is a cross-sectional view showing a method for manufacturing a semiconductor substrate according to Example 1. The semiconductor substrate of Example 1 can be manufactured as follows. A silicon substrate (Si (111) surface) is used as a main substrate 1, and an AlN film (seed crystal portion 3) is formed on the silicon substrate by sputtering. By using parallel flat plate type, magnetron sputtering, pulse sputtering, etc. as a sputtering method, low-temperature and low-cost film formation can be achieved. In addition, by using the MOCVD method, a highly crystalline AlN film can be formed.

[0085] The thickness of the seed crystal portion 3 is set to 100 nm. At high temperatures, there is a problem of mutual reaction between silicon and gallium (so-called melting back), and in order to suppress this problem, the thickness of the seed crystal portion 3 can be set to 50 to 500 nm.

[0086] The film formation temperature of the seed crystal part 3 is 400°C, a mixed gas of argon gas and nitrogen gas (gas ratio is about 1:1), an input power of 500W, and a back pressure of 0.3Pa during film formation. When a sapphire substrate is used, AlN is directly formed, but when an AlN layer is formed on a silicon substrate, a high-quality AlN layer can be formed without nitriding the silicon substrate by first forming an Al layer of a few nm (buffer part 2) and then forming the AlN layer. In the formation of the Al layer, only Ar gas is used (without introducing nitrogen) to sputter the Al target. In this way, the Al layer and the AlN layer can be continuously formed without moving the substrate in and out of the same chamber. In addition, when an MOCVD device is used to form an Al layer and an AlN layer, first, only TMA (trimethylaluminum) is introduced to form an Al layer of a few nm on the silicon substrate, and then NH 3 , thereby obtaining a stacked structure of Si substrate / Al layer / AlN layer.

[0087] Next, a stripe-shaped resist Z with a width of about 3 [μm] is formed on the upper part of the seed crystal part 3 using a photolithography process, and a ridge R is formed using a dry etching process. At this time, the seed crystal part 3 and a part of the main substrate 1 are etched. For example, if the etching thickness of the seed crystal part 3 (AlN layer) is set to 100 [nm], and the etching thickness of the main substrate is set to about 300 [nm] to form the ridge R, the ridge height becomes about 400 nm. Here, the resist Z is not removed, and a silicon nitride film SF (for example, 10 nm) is formed on the resist Z to become the mask part 5.

[0088] When the ELO layer contacts the mask portion (growth inhibition region), the thickness of the mask portion needs to be at least 100 nm, and sometimes the surface flatness of the ELO layer is lost due to the interference between the mask portion and the ELO layer. However, in Example 1, since the wing portion F floats in mid-air and does not contact the mask portion 5, even if the mask portion 5 is made very thin, the growth of the wing portion F is not hindered. By thinning the mask portion 5, the flatness of the back side of the wing portion F is improved. If the thickness of the mask portion 5 is set to 50 [nm] or less, the flatness is improved, and it can also be set to 30 [nm] or less.

[0089] Next, the resist Z is removed and the silicon nitride film SF on the ridge R is peeled off to form a first opening K1 to form a template substrate TS (selective growth substrate). Thus, by manufacturing the template substrate TS without using MOCVD, significant cost reduction can be achieved, which is a great industrial advantage.

[0090] Furthermore, when the AlN layer (base layer) is formed by sputtering, Ga will not adhere to the surface of the silicon substrate. When the AlN layer is formed by using the MOCVD device used in the formation of the GaN layer, during the temperature rise process before film formation, the Ga in the furnace sometimes adheres to the surface of the silicon substrate and melts back, which becomes a problem of reduced yield. Therefore, the maintenance of the MOCVD device (such as cleaning of parts inside the device such as trays and covers) becomes high frequency, which becomes a cause of high costs. On the other hand, the present embodiment is a method of forming the semiconductor part 8 with an MOCVD device and forming the AlN layer (base layer) and the mask layer with a sputtering device different from the device. When the MOCVD device is introduced, the surface of the silicon substrate is covered with AlN (base layer) and the mask part, and the reduction in yield due to melting back will not occur. Therefore, the industrial advantage is great.

[0091] Next, the template substrate TS is transported to the MOCVD device, and the semiconductor portion 8 is formed on the template substrate TS by the ELO method. In Example 1, the semiconductor portion 8 is a GaN layer, the growth temperature is set to 1000-1200 degrees, the V / III ratio is set to 500-20000, and the growth pressure is set to 50 kPa. In addition, since the semiconductor portion 8 is set to n-type, SiH 4 Even if SiH is not introduced 4 , it is also possible to use a material containing Si in the mask portion, such as SiO 2、SiN is used to dope Si with Si evaporated from there. The film forming conditions are preferably set in at least two stages. In the first stage, the film forming temperature is set to about 1030°C, V / III is set to about 2000, and the growth nucleus (vertical growth portion) of the ELO layer (semiconductor portion 8) is formed on the opening K. The thickness (height) of the growth nucleus is set to about 0.2 to 3.0 [μm], and its width can be set to the same degree as the width of the ridge R, or slightly exceeding the size in the a-axis direction (<11-20> direction). In the second stage, the film forming temperature is increased by about 100°C, so that the GaN layer grows from the growth nucleus in the lateral direction (a-axis direction), and the width of the gap GP between the semiconductor portions 8 (GaN layers) growing in opposite directions on the gap becomes a specified value (less than 10μm), and the growth is stopped. The semiconductor substrate 10 (semiconductor portion 8 exposed state) obtained by the above can be taken out from the MOCVD device and stored, or an upper layer including an active layer, etc. can be formed in the MOCVD device next.

[0092] In Example 1, it can be seen that even if the crystallinity on the opening K is poor, the wing F on the gap (above the mask part) is unlikely to inherit the poor crystallinity, and the crystallinity of the wing F is improved (the defect density is significantly reduced). In addition, when a nitride semiconductor layer is formed on a seed layer formed by sputtering without using the ELO method, since the defects of the seed layer are inherited by the nitride semiconductor layer on the entire surface, it is difficult to obtain a high-quality device.

[0093] Fig.14 1 and 2 are Raman spectra of the base and wing of the ELO layer according to the comparative example. The ELO layer of the comparative example is formed on a seed layer formed by MOCVD. Fig.15 : is the Raman spectrum of the base and wing of the ELO layer (semiconductor part) involved in Example 1. The seed layer is formed by sputtering. Fig.14 It can be seen that in the comparative example, the half-peak width of the spectrum of GaN in the base is 2.2 cm -1 The half-peak width of the spectrum of GaN on the wing is 2.0 cm -1 .from Fig.15 It can be seen that in Example 1, the half-peak width of the spectrum of GaN in the base is 2.8 cm -1 The half-peak width of the spectrum of GaN on the wing is 2.0 cm -1 The wing portion is a very high-quality crystal that is unchanged from the comparative example (seed crystal portion formed by MOCVD). This is a very significant discovery in the industry. This is because a high-quality semiconductor portion is obtained using a low-cost template substrate including an inexpensive silicon substrate and a base portion (seed crystal portion or a stacked portion of a buffer portion and a seed crystal portion) formed by a non-MOCVD device such as a sputtering device or an EB device.

[0094] With respect to the upper layer portion 9 (device layer, functional layer) formed on the semiconductor portion 8, by forming an active region (e.g., a light-emitting region) at least above the wing portion, a very high-quality element can be manufactured. In the first embodiment, the template substrate TS is formed without using an MOCVD device, and there is an advantage that the semiconductor portion 8 and the upper layer portion 9 can be continuously formed using an MOCVD device.

[0095] Fig.16 It is a top view of the semiconductor substrate including the upper layer portion. Fig.17 It is a cross-sectional view of a semiconductor substrate including an upper portion. After the growth of the semiconductor portion 8 is stopped, the film forming conditions can be changed (for example, the film forming temperature is lowered by about 100°C) to form the upper portion 9 on the semiconductor portion 8. The upper portion 9 can include at least one of a p-type layer, an n-type layer, and an electron blocking layer in addition to the active layer. When the upper portion 9 is formed on the semiconductor substrate 10, the back-winding phenomenon of the upper component material supplied to the back side of the semiconductor portion 8 is also greatly suppressed, and the problem of light absorption caused by the back-winding phenomenon is also eliminated.

[0096] exist Fig.16 as well as Fig.17 In the semiconductor substrate 10 described above, an anode EA and a cathode EC are formed above the wing F of the semiconductor portion 8. In a general LED, an active region (light-emitting region) is formed directly below the anode EA formed of a transparent electrode such as ITO (indium tin oxide). In Example 1, since the wraparound phenomenon is suppressed, the problem of light emitted from the active region being absorbed by the back side of the wing F is eliminated. At least a portion of the anode EA may be located above the wing F, or the entire anode EA may be located above the wing F. Since the area directly below the cathode is generally not an active region, the cathode EC may also be formed above the ridge R. Fig.16 as well as Fig.17 In the embodiment, the anode EA and the cathode EC are formed on the same wing F, but the present invention is not limited thereto. Figure 8 In this way, the anode EA is formed on one of the two wing portions F facing each other with the ridge portion R interposed therebetween, and the cathode EC is formed on the other.

[0097] In the conventional ELO method, cracks may sometimes occur in the semiconductor layer due to the difference in thermal expansion coefficients between the heterogeneous substrate and the semiconductor layer. On the other hand, in Example 1, by using a heterogeneous substrate (Si substrate, SiC substrate, etc.), the adjacent semiconductor portions 8 do not meet (having a gap GP) and the semiconductor portion 8 is located on the gap and physically isolated from the mask portion 5, the internal stress is effectively relaxed and the generation of cracks is suppressed. By widening the width of the wing portion F (for example, setting it to 7 μm or more), stress relaxation based on the wing portion F can be achieved.

[0098] In Example 1, the width WJ of the gap J is 20 μm, the ridge height is 300 nm, and the width of the gap GP is 10 μm. Since the back surface of the semiconductor portion 8 is at the same level as the upper surface of the ridge R, the thickness of the gap J is 300 nm, and the aspect ratio of the gap J is 66.6. It can be seen that although the upper layer 9 is formed on the semiconductor portion 8, the active layer material and the like are not stacked on the back surface of the semiconductor portion 8, and the wraparound phenomenon is suppressed.

[0099] The width WR of the ridge R, which is the starting point of growth, can be 1 μm to 20 μm or 2 μm to 10 μm. The thickness TJ of the gap can be 5 μm or less, 2 μm or less, 1 μm or less, 0.6 μm or less, or 0.3 μm or less. The thickness TJ of the gap can be 0.05 μm (50 nm) or more. Thus, the mask portion 5 can be easily removed. The pitch PR of the ridges can be 20 μm or more. The thickness TJ of the gap can be supplemented by 0.5 μm (500 nm). Thus, the morphology formation on the back side can be reduced, and the quality of the device formed on the wing F can be improved. The aspect ratio of the gap J can be set to be greater than 5.0, greater than 10, greater than 20, greater than 30, greater than 50, or greater than 100. In this way, the upper layer 9 can be formed on the wide wing F while suppressing the wraparound phenomenon, and a high-quality (for example, high light extraction efficiency) semiconductor element can be formed. The aspect ratio of the gap J can be, for example, 100 to 1000. Thus, the possibility of the semiconductor portion 8 warping in the upward direction due to gravity is reduced. In addition, by setting the width of the gap GP to less than 30 μm, or less than 10 μm, the wraparound phenomenon can be more effectively suppressed. In other words, there is no stacking of active layer materials on the back of the wing F formed in this way. Therefore, the possibility of current leakage in the device formed on the wing F is small. The width of the gap GP can be set to 1 / 5 to 1 / 100 of the width of the wing F. Thus, the wide wing F can be formed while suppressing the wraparound phenomenon, which can increase the degree of freedom of the device.

[0100] Fig.18 This is a top view showing the method of separating the elements in Example 1. Fig.19 2 is a cross-sectional view showing the method of separating the components in Example 1. Fig.18 as well as Fig.19As shown, the element body 20 (including the wing portion F, the upper portion 9, the anode EA, and the cathode EC) is separated from the template substrate. Since there is a gap J under the wing portion F, by applying downward pressure to the element body 20 with an adhesive pressing body YS (adhesive plate, adhesive sheet, etc.), the root portion of the element body 20 (the portion connected to the template substrate TS) is easily broken, and the element body 20 is separated from the template substrate TS. Specifically, the element body 20 is peeled off from the template substrate TS while being held by the pressing body YS. In this way, the gap J also functions effectively in the separation of the element body, and the element body 20 can be peeled off without damaging the element body 20.

[0101] Specific examples of the element body 20 include a light emitting diode (LED), a semiconductor laser, a Schottky diode, a photodiode, a transistor (including a power transistor and a high electron mobility transistor), and the like.

[0102] Fig. 20 : is a schematic diagram showing the structure of the electronic device involved in Example 1. The electronic device 30 includes: an element body 20; a drive substrate 23 on which the element body 20 is mounted; and a control circuit 25 that controls the drive substrate 23. The control circuit 25 may also include a processor. Examples of the electronic device 30 include a display device, a laser emitting device (including a Fabry-Perot type and a surface emitting type), a lighting device, a communication device, an information processing device, a sensing device, a power control device, and the like.

[0103] exist Fig. 20 In the embodiment, the element body 20 is bonded and electrically connected to the drive substrate 23 in a state where it is peeled off from the template substrate TS, but it may also be bonded and electrically connected to the drive substrate 23 in an unpeeled state (the template substrate TS and the element body 20 thereon).

[0104] [Example 2]

[0105] In Example 2, the formation Figure 3A semiconductor substrate 10 is provided. Specifically, a silicon substrate is used as the main substrate 1, and an Al layer (not shown) is formed on the main substrate 1. Then, as the buffer portion 2, an AlN layer with a thickness of 200 nm is formed by sputtering. The film forming temperature is set to 400°C, and a mixed gas of argon gas and nitrogen gas is used. The gas ratio is about 1:1, the input power is 500W, and the back pressure during film formation is 0.3Pa. Next, a GaN target is used to form a GaN layer with a thickness of 400nm as the seed crystal portion 3 on the buffer portion 2 (AlN layer) by sputtering. After that, the ridge R and the SiN film are formed by the above-mentioned method, and the SiN film on the ridge is peeled off, thereby making a template substrate TS (selective growth substrate) containing a mask pattern 6. The bottom surface of the ridge R reaches the main substrate 1, and the main substrate 1 is dug in by about 400nm. After that, the semiconductor portion 8 is formed on the template substrate TS by using the MOCVD method to obtain the semiconductor substrate 10.

[0106] In Example 2, the height of the ridge R is 200nm (thickness of the AlN layer) + 400nm (thickness of the GaN layer) + 400nm (depth of the digging of the main substrate) = 1000nm (1.0μm). The width of the ridge R is 3μm, the pitch width of the ridge is 40μm, the width of the gap GP is 5μm, and the width WJ of the gap J is 16μm. Since the upper surface of the ridge R and the back surface of the semiconductor part 8 are at the same height, the thickness TJ of the gap J is 1μm, and the aspect ratio of the gap J is 16.0.

[0107] In Example 2, by changing the film forming conditions of the ELO method (for example, by changing the partial pressures of nitrogen and hydrogen used in the gas flow to increase the amount of hydrogen), it is possible to make the height of the back surface of the wing portion F lower than the upper surface of the ridge portion R. Figure 4 In this case, since the film formation on the back of the wing F ends at a position about 600 nm lower than the upper surface of the ridge R, the thickness TJ of the gap J becomes 400 nm. The width of the ridge R is 8 μm, the pitch width of the ridge is 78 μm, and the width of the gap GP is 30 μm. Therefore, the width WJ of the gap J becomes 20 μm, and the aspect ratio of the gap J becomes 50.

[0108] [Example 3]

[0109] In Example 3, the formation Figure 2A semiconductor substrate 10 is provided. Specifically, a sapphire substrate is used as the main substrate 1, and an AlN layer with a thickness of 200 nm is formed on the main substrate 1 by sputtering as a seed crystal portion 3. The film forming temperature is set to 500°C, and a mixed gas of argon gas and nitrogen gas is used. The gas ratio is about 1:1, the input power is 500W, and the back pressure during film formation is 0.3Pa. Thereafter, the ridge R and the SiN film are formed by the above-mentioned method, and the SiN film on the ridge is peeled off to make a template substrate TS (selective growth substrate) containing a mask pattern 6. The bottom surface of the ridge R reaches the main substrate 1 (sapphire substrate), and the main substrate 1 is dug in by about 10nm. Thereafter, a semiconductor portion 8 is formed on the template substrate TS by MOCVD.

[0110] In Example 3, the height of the ridge R is 200nm (thickness of the AlN layer) + 10nm (depth of the digging of the main substrate) = 210nm. The width of the ridge R is 2μm, the pitch width of the ridge is 30μm, the width of the gap GP is 2μm, and the width WJ of the gap J is 13μm. Since the upper surface of the ridge R and the back surface of the semiconductor portion 8 are at the same height, the thickness TJ of the gap J is 200nm and the aspect ratio of the gap J is 65. It can be seen that although the upper layer 9 is formed on the semiconductor portion 8, the stacking of the active layer material and the like to the back surface of the semiconductor portion 8 is not confirmed, and the wraparound phenomenon is suppressed.

[0111] [Example 4]

[0112] Fig.21 : is a cross-sectional view showing the structure of the semiconductor substrate of Example 4. In Example 4, in the template substrate TS, a seed crystal portion 3 having a two-layer structure of an AlGaN layer (2μm) and a GaN layer (1.5μm) is formed by MOCVD on the AlN layer (200nm) as the buffer portion 2. The height of the ridge R is 300nm, and the bottom surface of the ridge R is located in the GaN layer (the lower layer of the seed crystal portion 3). On the template substrate TS, the semiconductor portion 8 is formed by MOCVD.

[0113] In Example 4, the width WR of the ridge R is 3 μm, the pitch width PR of the ridge is 55 μm, the width of the gap GP is 10 μm, and the width WJ of the void J is 21 μm. The back surface of the wing F is about 50 nm lower than the upper surface of the ridge R, and the thickness TJ of the void J is 250 nm. Therefore, the aspect ratio of the void J is 84.

[0114] Fig. 22 : is a graph showing the results of XRD reflection scanning measurement of the ELO layer of the comparative example. The ELO layer of the comparative example was grown in the lateral direction so as to be in contact with the mask portion. Fig.23 : is a graph showing the results of XRD reflection scanning measurement of the semiconductor part of Example 1. Fig. 22 In the , three peaks corresponding to the base and the two wings (pairs of wings) sandwiching it are detected. The central peak is the peak of the base, and the crystal axis of the c-plane (c-axis) is substantially perpendicular to the surface of the mask part. Fig. 22 The angle difference Δ from the peaks of the two wings is 1.1 degrees. As can be seen from the results, in the comparative example, the c-axes of the two wings deviate from the center to the opposite side by about 0.5 degrees each time. Such a c-axis inclination indicates a low degree of flatness of the ELO layer. On the other hand, in Fig.23 The angle difference Δ from the peaks of the two wings is 0.17 degrees, which is less than 1 / 5 of that in the comparative example. From this result, it can be seen that in Example 1, the flatness of the semiconductor portion 8 is greatly improved compared with the comparative example. In addition, in other embodiments, a value of Δ=0.2 degrees or less can also be obtained. It is believed that the main reason is that the wing portion F is grown on the gap J; the gap GP is not formed by allowing adjacent semiconductor portions 8 to meet each other. It can be seen that by being able to obtain such good flatness in the wide wing portion F (for example, more than 7μm), in the formation of the upper portion 9 (for example, reference Fig.17 ), the incorporation of In (indium) is uniformed within the surface, and the quality (eg, luminous efficiency) and yield of the element body 20 are greatly improved.

[0115] [Example 5]

[0116] Fig.24 It is a top view showing the structure of the semiconductor substrate of Example 5. Fig.24 is a cross-sectional view showing the structure of a semiconductor substrate of Example 5. Fig.24 as well as Fig.25 As shown, it has: a template substrate TS including a first seed crystal region S1 and a growth inhibition region (non-seed crystal portion) DA arranged side by side in a first direction X1; and a first semiconductor portion 8A located above the template substrate TS, the first semiconductor portion 8A having: a first base B1 located above the first seed crystal region S1; and a first wing F1 connected to the first base B1 and facing the growth inhibition region DA across a first gap J1, the first wing F1 including: a wing end (edge) E1 located above the growth inhibition region DA, the ratio of the width of the first gap J1 in the first direction X1 to the thickness TJ being 5.0 or more. In this way, a wide device layer (functional layer) can be formed on the first wing F1. The thickness TJ of the first gap J1 can be the thickness z below the wing end E1 of the first gap J1.

[0117] In the semiconductor substrate 10, the template substrate TS includes a main substrate 1 and a base layer 4. In the first seed crystal region S1, the base layer 4 is unmodified, and in the growth inhibition region DA, the base layer 4 is modified. Furthermore, the first semiconductor portion 8A includes a first raised portion R1 located on the first seed crystal region S1, and a growth inhibition film 7 connected to the first raised portion R1 is provided. The first raised portion R1 is formed in a table shape on the first seed crystal region S1 and is connected to the first base B1. The growth inhibition film 7 can be connected to the side and upper surface of the first raised portion R1 and can be located on the growth inhibition region DA.

[0118] Fig.26 Yes means Fig.25 A cross-sectional view of a method for manufacturing a semiconductor substrate. Fig.26 The process includes the following steps: preparing a template substrate TS including a first seed crystal region S1 and a growth inhibition region DA; forming a first raised portion R1 starting from the first region S1 above the template substrate TS; forming a growth inhibition film 7 connected to the first raised portion R1; forming a first base B1 located above the first raised portion R1, and a first wing F1 connected to the first base B1, separated from the growth inhibition region DA and located on the gap J1.

[0119] like Fig.26 As shown in FIG. 1 , the first base B1 and the first wing F1 can be formed with the corner RC of the first raised portion R1 as the growth starting point. The corner RC can be used as the growth starting point in this way, but the present invention is not limited thereto. A defect (e.g., a tiny opening) can be formed in the growth inhibiting film 7 on the first raised portion R1, and the defect in the growth inhibiting film 7 can be used as the growth starting point of the first base B1 and the first wing F1.

[0120] The first raised portion R1, the growth inhibiting film 7, the first base B1, and the first wing F1 can be formed continuously using an MOCVD device. The first raised portion R1 includes a GaN-based semiconductor, the growth inhibiting film 7 is a silicon nitride, and a raw material serving as a gallium source (organic raw materials such as trimethyl gallium (TMG) and triethyl gallium (TEG)) and a raw material serving as a nitrogen source (ammonia gas (NH 3 )) to form the first raised portion R1, by stopping the supply of the raw material that becomes the gallium source while maintaining the supply of the raw material that becomes the nitrogen source, and supplying the silicon-based material (e.g., SiH 4), to form a growth inhibition film 7. The first base B1 and the first wing F1 include GaN-based semiconductors, and the first base B1 and the first wing F1 can be formed by stopping the supply of silicon-based materials while maintaining the supply of a raw material that serves as a nitrogen source and supplying a raw material that serves as a gallium source. In addition, the supply of a small amount of silicon-based materials can be continued at a doping level. Since the first raised portion R1 is the same GaN-based semiconductor as the first wing F1, lattice defects caused by the difference in lattice constant between the first raised portion R1 and the first wing F1 are reduced.

[0121] By forming the growth inhibition film 7 in this way, the film formation can be continuously performed while the first gap J1 is formed under the wing portion F without being removed from the MOCVD device, which can reduce the manufacturing time and manufacturing cost. By forming the first gap J1, the wing portion F is formed without contacting the base layer 4 (growth inhibition area DA), and the stress from the main substrate 1 and the base layer 4 applied to the semiconductor portion 8 can be effectively alleviated.

[0122] Fig. 27 Yes means Fig.25 A cross-sectional view of a method for manufacturing a template substrate. Fig. 27 As shown in FIG. 1 , the substrate 4 can be obtained by performing a step of forming a base layer 4 including a base material, a step of forming a film of a resist RZ on the base layer 4, a step of patterning the resist RZ, a step of plasma treating the exposed base material, and a step of removing the resist RZ. Fig.25 The base layer 4 can be formed by sputtering.

[0123] In the plasma treatment, for example, the exposed surface 4D of the base layer 4 is irradiated with argon plasma to perform surface modification of the irradiated area, thereby forming a growth inhibition area DA. By introducing not only argon gas but also oxygen gas, nitrogen gas, hydrogen gas, etc. into the chamber, in the plasma treatment, not only argon plasma but also oxygen plasma, nitrogen plasma, hydrogen plasma, or mixed plasma thereof can be used. Thus, the growth inhibition area DA can contain argon, oxygen, nitrogen, etc. as impurities. In such a case, the base material can be aluminum nitride, and the growth inhibition area DA can be aluminum oxynitride. In addition, the base material can be AlScN (aluminum scandium nitride), and the growth inhibition area DA can be AlScON (aluminum scandium oxynitride).

[0124] Fig.28 is a cross-sectional view showing a method for manufacturing a template substrate. Fig.28As shown, the following steps can be performed: patterning a resist RZ on the base layer 4 (e.g., an AlN layer); forming a film CM (e.g., a silicon nitride film of about 10 nm) covering the base layer 4 and the resist RZ; removing the resist RZ (stripping the pattern to form a film CM); annealing the film CM and the base layer 4 (e.g., heating at 1000°C); and removing the film CM (e.g., removing the silicon nitride film by BHF). In this way, a growth inhibition area DA located under the film CM can be formed on the surface of the base layer 4 through the mutual diffusion phenomenon between the film CM and the base layer 4 during annealing. In addition, by forming the film CM by sputtering, the surface modification under the film CM can be performed without undergoing annealing. The base material can be AlScN, ScN, ZnO, CrN, etc. containing dissimilar materials such as Sc (scandium), Zn, Cr, etc. (e.g., metal elements other than group III). The base layer 4 can be a single-layer structure or a multi-layer structure. It can also be a multi-layer structure containing a periodic structure.

[0125] Fig.29 is a cross-sectional view showing a method for manufacturing a template substrate. Fig.29 As shown, the following steps can be performed: patterning a resist RZ on a base layer 4 (e.g., an AlN layer); subjecting the exposed base material to an implantation treatment of impurity ions; and removing the resist RZ. As impurities, Si (silicon), Fe (iron), Mg (magnesium), etc. can be cited. In the implantation treatment, the surface is modified by embedding impurity ions in the exposed surface 4D of the base layer 4 to form a growth inhibition area DA. The base material can be AlScN, ScN, ZnO, CrN, etc. containing heterogeneous materials such as Sc (scandium), Zn, Cr, etc. (e.g., metal elements other than group III). The base layer 4 can be a single-layer structure or a multi-layer structure. It can also be a multi-layer structure including a periodic structure.

[0126] [Example 6]

[0127] Fig.30 as well as Fig.31 is a cross-sectional view showing the structure of a semiconductor substrate of Example 6. Fig.30 as well as Fig.31As shown, it comprises: a template substrate TS including a first seed region S1 and a growth inhibition region (non-seed region) DA arranged side by side in a first direction X1; and a first semiconductor portion 8A located above the template substrate TS, the first semiconductor portion 8A having: a first base portion B1 located above the first seed region S1; and a first wing portion F1 connected to the first base portion B1 and facing the growth inhibition region DA via a first gap J1, the first wing portion F1 including a wing end (edge) E1 located above the growth inhibition region DA, and a ratio of a width (WJ) of the first gap J1 in the first direction X1 to a thickness TJ of 5.0 or more. The width (single wing width Wf) of the first wing portion F1 in the first direction X1 may be 5.0 times or more of the thickness TJ of the first gap J1. The thickness TJ may be a thickness below the wing end E1 of the first gap J1, or may be a distance (interval) from the growth inhibition region DA to the wing end E1. In this way, a wide device layer (upper layer, functional layer) can be formed on the first wing portion F1. The threading dislocation density of the first wing portion F1 can be 5×10 6 〔pcs / cm 2 The first wing portion F1 may have a width in the first direction X1 (single wing width Wf) with respect to a thickness Th (wing thickness) of 5.0 or more.

[0128] Fig.30 The template substrate TS includes a main substrate 1, a buffer portion (planar buffer layer) 2 and a seed portion 3. The buffer portion 2 is a growth inhibition layer (a layer that inhibits the growth of nitride semiconductor crystals) and includes a ridge portion (convex portion) R1. The buffer portion 2 may include at least one of a 4H-SiC layer, a 6H-SiC layer, a 3C-SiC layer, a sapphire layer, a diamond layer and a ScAlMgO layer. A seed portion 3 (e.g., AlN) including a first seed region S1 is formed on the ridge portion R1, and an area on the upper surface of the buffer portion 2 that does not overlap with the seed portion 3 functions as a growth inhibition region DA. The main substrate 1 can use a silicon substrate, a silicon carbide substrate, a sapphire substrate, etc.

[0129] Fig.31 The template substrate TS includes a main substrate 1 and a seed crystal portion 3. The main substrate 1 is a growth inhibition substrate (a substrate for inhibiting the growth of nitride semiconductor crystals) and includes a ridge portion (convex portion) R1. The main substrate 1 can be a 4H-SiC substrate, a 6H-SiC substrate, a 3C-SiC substrate, a sapphire substrate, a diamond substrate, or a ScAlMgO substrate. A seed crystal portion 3 (for example, AlN) including a first seed crystal region S1 is formed on the ridge portion R1, and a region of the upper surface of the main substrate 1 that does not overlap with the seed crystal portion 3 functions as a growth inhibition region DA.

[0130] [Example 7]

[0131] Fig.32It is a cross-sectional view showing the structure of the semiconductor substrate of Example 7. Fig.32 The semiconductor substrate 10 comprises: a template substrate TS including a first seed crystal region S1; and a first semiconductor portion 8 located above the template substrate TS, the first semiconductor portion 8 having: a first base B1 located on the first seed crystal region S1; and a first wing F1 adjacent to the first base B1 in a first direction X1 and connected to the first base B1, the template substrate TS comprising: a growth inhibition region DA facing the first wing F1 across a first gap J1, the first wing F1 comprising a wing end (edge) E1 located above the growth inhibition region DA, and a ratio of a length WJ of the first gap J1 in the first direction X1 to a thickness TJ of the first gap J1 being greater than 5.0.

[0132] The template substrate TS includes: a main substrate 1 having a lattice constant different from that of the first semiconductor portion 8; and a seed crystal portion 3 located above the main substrate 1, wherein the upper surface of the seed crystal portion 3 is the first seed crystal region S1, and the side surfaces of the seed crystal portion 3 may be covered with the same material as the growth inhibition region DA.

[0133] like Fig.32 In this way, a flat buffer portion 2 (e.g., a planar AlN layer) can be formed on the main substrate 1, and a table-shaped seed crystal portion 3 (ridge R1) including the first seed crystal region S1 can be formed on the buffer portion 2. The seed crystal portion 3 can be a GaN-based semiconductor. By making the seed crystal portion 3 the same GaN-based semiconductor as the first semiconductor portion 8, lattice defects caused by the difference in lattice constant between the seed crystal portion 3 and the first semiconductor portion 8 can be reduced. Fig.32 In the example shown, the thickness TJ of the first gap J1 below the wing tip is 482 [nm], the width of the first gap J1 is 20.1 [μm], the width of the opening K is 3.06 [μm], the width of the first semiconductor portion 8 including both wings (length in the first direction) Ws is 44.1 [μm], and the thickness of the first semiconductor portion 8 (wing thickness) Th is 2.22 [μm]. Regarding the thickness of the first gap J1, the thickness below the wing root may differ from the thickness below the wing tip by about 0 to 5%. In this case, the thickness of the first gap J1 may be the thickness (TJ) below the wing tip or the minimum thickness throughout the entire first gap J1.

[0134] [Example 8]

[0135] Fig.33 It is a flowchart showing the manufacturing method of the semiconductor device of Example 8. Fig.34 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 8. Fig.33 as well as Fig.34As shown in FIG. 1 , the element body 20 (semiconductor device) can be obtained by performing step S60 of preparing the semiconductor substrate 10, step S7 of forming the upper layer 9 above the first wing F1, and step S80 of peeling the first wing F1 from the template substrate TS while the first wing F1 and the upper layer 9 are kept on the transfer substrate PS, and the semiconductor device 21 including the element body 20 and the transfer substrate PS can also be obtained. In step S70, the upper layer 9 does not need to be formed below (on the back side) of the first wing F1. The upper layer 9 (functional layer) can be, for example, a nitride semiconductor layer (for example, a GaN-based semiconductor layer) including an active layer, and an electrode, an insulating film, etc. can be provided on the upper layer 9. The semiconductor device (20, 21) can include an electrode, an insulating film, etc.

[0136] In the semiconductor substrate 10 of Fig. 35, since the growth inhibiting film 7 is provided on the first raised portion R1, the first raised portion R1 is weakly bonded to the first wing portion F1, and the first wing portion F1 can be easily peeled off. Since the first raised portion R1 and the first base portion B1 are nitride semiconductor crystals, cleavage can be performed at the boundary between the two.

[0137] (Note)

[0138] The above disclosure is for the purpose of illustration and description, and is not intended to be limiting. Based on these illustrations and descriptions, many modifications are obvious to those skilled in the art, and it is to be noted that these modifications are also included in the embodiments.

[0139] Explanation of symbols

[0140] 1 Main base board

[0141] 2 Buffer

[0142] 3 Seed crystal

[0143] 4 Basal layer

[0144] 5 Mask Department

[0145] 6 Mask Pattern

[0146] 8A 1st Semiconductor Division

[0147] 8C Semiconductor Division 2

[0148] 9 Upper part

[0149] 10 Semiconductor substrate

[0150] 20 Component body (semiconductor device)

[0151] 21 Semiconductor devices

[0152] 50 Semiconductor substrate manufacturing device

[0153] R Ridge

[0154] E1 Edge

[0155] B1 1st base

[0156] B2 Second base

[0157] F1 Wing 1

[0158] F2 2nd Wing

[0159] J1 1st gap

[0160] J2 2nd gap

[0161] S1 1st seed crystal area

[0162] S2 Second seed crystal area

[0163] DA growth inhibition region

[0164] TS template substrate.

Claims

1. A semiconductor substrate comprising: a template substrate including a first seed region and a growth inhibition region arranged side by side in a first direction; and a first semiconductor portion located above the template substrate, The first semiconductor portion includes: a first base located on the first seed crystal region; and a first wing portion connected to the first base portion and facing the growth inhibition region across a first gap, The first wing portion includes: a wing end located above the growth inhibition region, A ratio of the width of the first gap in the first direction to the thickness below the wing tip is 5.0 or more.

2. The semiconductor substrate according to claim 1, wherein A ratio of the width of the first wing portion in the first direction to the thickness thereof is 5.0 or more.

3. The semiconductor substrate according to claim 1 or 2, wherein: The width of the first wing portion in the first direction is 7.0 [μm] or more.

4. The semiconductor substrate according to any one of claims 1 to 3, wherein The semiconductor substrate comprises: a second semiconductor portion located above the template substrate; The template substrate includes: a second seed crystal region adjacent to the first seed crystal region across the growth suppression region in a plan view; The second seed crystal region is located above the growth inhibition region, The second semiconductor portion has: a second base located on the second seed crystal region; and a second wing portion connected to the second base portion and facing the growth inhibition region across a second gap, The second wing portion includes: a wing end located above the growth inhibition region, The first wing portion and the second wing portion are arranged side by side in the first direction with a gap therebetween. A ratio of the width of the second gap in the first direction to the thickness below the wing tip is 5.0 or more.

5. The semiconductor substrate according to claim 4, wherein: The width of the gap is greater than the thickness of the first space below the wing end.

6. The semiconductor substrate according to any one of claims 1 to 5, wherein The template substrate has a ridge portion on the upper surface side, The first seed region is located on the upper surface of the ridge.

7. The semiconductor substrate according to any one of claims 1 to 6, wherein A ratio of the width of the first wing portion to the width of the first base portion is 3.0 or more.

8. The semiconductor substrate according to any one of claims 1 to 7, wherein The first wing portion and the first base portion have the same thickness.

9. The semiconductor substrate according to any one of claims 1 to 7, wherein The first wing portion is thicker than the first base portion.

10. The semiconductor substrate according to any one of claims 1 to 9, wherein The thickness of the first gap below the wing end is 3.0 [μm] or less.

11. The semiconductor substrate according to any one of claims 1 to 10, wherein The first seed crystal region and the growth suppression region each have a shape whose longitudinal direction is a second direction perpendicular to the first direction.

12. The semiconductor substrate according to any one of claims 1 to 11, wherein The template substrate comprises: a main substrate having a lattice constant different from that of the first semiconductor portion; and Seed crystal part.

13. The semiconductor substrate according to claim 12, wherein: The main substrate is a silicon substrate, a sapphire substrate, or a silicon carbide substrate, and the first semiconductor portion includes a nitride semiconductor.

14. The semiconductor substrate according to claim 12 or 13, wherein: The template substrate has a mask pattern including: a mask portion functioning as the growth suppression region; and an opening portion functioning as the first seed crystal region.

15. The semiconductor substrate according to claim 14, wherein The template substrate has a ridge portion on the upper surface side, The seed portion is included in the ridge portion.

16. The semiconductor substrate according to claim 15, wherein The seed crystal portion is not disposed under the mask portion.

17. The semiconductor substrate according to claim 15 or 16, wherein: The upper surface of the ridge portion is formed by the seed portion, and the side surface of the ridge portion is formed by the mask portion.

18. The semiconductor substrate according to any one of claims 15 to 17, wherein The main substrate includes a protrusion on the upper surface side, and the seed crystal portion is located on the protrusion.

19. The semiconductor substrate according to any one of claims 15 to 17, wherein The ridge is located on the flat upper surface of the main substrate.

20. The semiconductor substrate according to claim 17, wherein The side surface of the ridge portion does not contact the first wing portion.

21. The semiconductor substrate according to claim 17, wherein The side surface of the ridge portion is in contact with the first wing portion.

22. The semiconductor substrate according to any one of claims 14 to 21, wherein The thickness of the mask portion is 50 nm or less.

23. The semiconductor substrate according to any one of claims 12 to 22, wherein The seed crystal portion contains 2×10 18 / cm 3 Argon or oxygen nitride semiconductors as above.

24. The semiconductor substrate according to claim 13, wherein The nitride semiconductor is a GaN-based semiconductor, A ratio of the width to the thickness of the first gap is 20.0 or more.

25. The semiconductor substrate according to claim 11, wherein The first wing portion is divided into a plurality of portions arranged side by side in a second direction orthogonal to the first direction.

26. The semiconductor substrate according to any one of claims 1 to 25, wherein The first semiconductor portion includes two first wing portions forming a pair extending from the first base portion in a first direction and in an opposite direction thereof.

27. The semiconductor substrate according to any one of claims 1 to 26, wherein The semiconductor substrate includes an upper layer portion located above the first semiconductor portion and including an active layer and a p-type layer.

28. The semiconductor substrate according to any one of claims 1 to 27, wherein The first semiconductor portion includes: a raised portion located on the first seed crystal region; The semiconductor substrate is provided with a growth inhibiting film in contact with the protrusion.

29. The semiconductor wafer according to any one of claims 1 to 11, wherein The template substrate comprises a main substrate and a base layer. In the first seed crystal region, the base layer is unmodified, In the growth inhibition region, the base layer is modified.

30. The semiconductor substrate according to any one of claims 1 to 11, wherein The template substrate comprises: a main substrate and a buffer portion; and a seed crystal portion located above the buffer portion, The seed crystal portion includes the first seed crystal region, A region of the upper surface of the buffer portion that does not overlap with the seed crystal portion functions as the growth suppression region.

31. The semiconductor substrate according to any one of claims 1 to 11, wherein The template substrate comprises: a main substrate; and The seed crystal portion is located above the main substrate. The seed crystal portion includes the first seed crystal region, A region of the upper surface of the main substrate that does not overlap with the seed crystal portion functions as the growth suppression region.

32. A method for manufacturing a semiconductor substrate, comprising the following steps: preparing a template substrate including a first seed crystal region and a growth inhibition region arranged side by side in a first direction; and A first semiconductor portion having a first base located on the first seed crystal region and a first wing portion connected to the first base and facing the growth inhibition region across a first gap is grown so that the width of the first wing portion in the first direction becomes more than 5.0 times the thickness under the wing end of the first gap.

33. The method for manufacturing a semiconductor substrate according to claim 32, wherein: The method for manufacturing the semiconductor substrate comprises the following steps: Before the first wing portion and the second wing portion growing in a direction approaching the first wing portion meet, the growth of the first wing portion and the second wing portion is stopped.

34. The method for manufacturing a semiconductor substrate according to claim 33, wherein: By setting the ratio of the thickness to the width of the first wing portion to 1 / 2 or less, the deviation between the c-axis direction of the first base portion and the c-axis direction of the tip of the first wing portion is set to 0.2° or less.

35. The method for manufacturing a semiconductor substrate according to any one of claims 32 to 34, wherein: The template substrate comprises: a seed crystal portion including a first seed crystal region; The seed crystal portion is formed by a sputtering method.

36. The method for manufacturing a semiconductor substrate according to claim 35, wherein: After using a sputtering device to cover the surface of a silicon substrate serving as a main substrate with the seed crystal portion that does not contain gallium and the mask portion that functions as the growth inhibition region, the silicon substrate and the template substrate including the seed crystal portion and the mask portion are introduced into an MOCVD device to form the first semiconductor portion including a GaN-based semiconductor.

37. A semiconductor substrate manufacturing apparatus, which performs the steps described in claim 32.

38. A method for manufacturing a semiconductor device, comprising the following steps: Preparing a semiconductor substrate according to any one of claims 1 to 31; forming an upper layer portion above the first wing portion; and The first wing portion is peeled off from the template substrate while the first wing portion and the upper layer portion are held on the transfer substrate.

39. The method for manufacturing a semiconductor device according to claim 38, wherein: The upper layer portion is not formed below the first wing portion.

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