Isotropic silicon nitride removal

Abstract

An example method of etching a silicon-containing material may include flowing a first fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber. The method may include flowing a sulfur-containing precursor into a remote plasma region of a semiconductor processing chamber. The method may include forming a plasma within a remote plasma region to produce a first fluorine-containing precursor and a plasma effluent of a sulfur-containing precursor. The method may include flowing a plasma effluent into a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The substrate may include a trench formed through a plurality of stacked layers including alternating silicon nitride layers and silicon oxide layers. The method may include isotropically etching the silicon nitride layer while substantially maintaining silicon oxide.

Description

Technical Field

[0001] This application claims priority under the Patent Law to U.S. patent application No. 17 / 963,687, filed on October 11, 2022, entitled "ISOTROPIC SILICONNITRIDE REMOVAL," which is incorporated herein by reference in its entirety.

[0002] The present technology relates to semiconductor processes and equipment. More particularly, the present technology relates to etching materials isotropically relative to other materials. Background Art

[0003] Integrated circuits are fabricated by processes that produce intricately patterned layers of material on a substrate surface. Producing the patterned material on a substrate requires a controlled method of removing exposed material. Chemical etching is used for a variety of purposes, including transferring a pattern in a photoresist into an underlying layer, thinning a layer, or thinning the lateral dimensions of a pre-existing feature on a surface. It is often desirable to have an etching process that etches one material faster than another to facilitate, for example, a pattern transfer process. Such an etching process is said to be selective to the first material. Due to the diversity of materials, circuits, and processes, etching processes that are selective to a variety of materials have been developed.

[0004] Depending on the materials used in the process, the etching process can be denoted as wet or dry. Wet HF etching preferentially removes silicon oxide over other dielectrics and materials. However, wet processes may have difficulty penetrating certain confined trenches and may sometimes deform the remaining material. Dry etching produced in a localized plasma formed within the substrate processing area can penetrate more confined trenches and exhibit less deformation of the fine remaining structure. However, the localized plasma may damage the substrate by creating arcs when it discharges.

[0005] Therefore, there is a need for improved systems and methods that can be used to produce high quality devices and structures. The present technology can meet these and other needs. Summary of the invention

[0006] An exemplary method of etching a silicon-containing material may include flowing a first fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber. The method may include flowing a sulfur-containing precursor into a remote plasma region of a semiconductor processing chamber. The method may include forming a plasma in the remote plasma region to produce plasma effluents of a first fluorine-containing precursor and a sulfur-containing precursor. The method may include flowing the plasma effluent into a processing region of the semiconductor processing chamber. A substrate may be disposed within the processing region. The substrate may include grooves formed through a plurality of stacked layers, the stacked layers including alternating silicon nitride layers and silicon oxide layers. The method may include isotropically etching a layer of silicon nitride while substantially maintaining silicon oxide.

[0007] In some embodiments, the method may include flowing a second fluorine-containing precursor to a processing region of a semiconductor processing chamber. The second fluorine-containing precursor may bypass the remote plasma region. The method may include stopping the flow of the first fluorine-containing precursor and the sulfur-containing precursor after a first period of time. The method may include purging the processing region with a purge precursor. The sulfur-containing precursor may be or may include hydrogen sulfide or carbon disulfide. The method may include flowing an additive precursor along with the first fluorine-containing precursor. The additive precursor may be or may include a halogen other than fluorine. The etch selectivity between silicon nitride and silicon oxide may be greater than or about 20:1. The fluorine-containing precursor may include sulfur, phosphorus, arsenic, silicon, carbon, selenium, or tellurium. The method may be performed at a chamber operating pressure between about 10 mTorr and about 5 Torr. The method may be performed at a chamber temperature of less than or about 20° C. The method may include flowing argon, helium, or nitrogen along with the fluorine-containing precursor. The flow rate ratio of argon, helium, or nitrogen to the fluorine-containing precursor may be less than or about 2:1. The method may include flowing a hydrogen-containing precursor along with a fluorine-containing precursor. The method may include forming a passivation layer over the silicon oxide.

[0008] Some embodiments of the present technology may include methods of etching silicon-containing materials. The methods may include flowing a first halogen-containing precursor into a remote plasma region of a semiconductor processing chamber. The first halogen-containing precursor may include fluorine. The methods may include forming a plasma in the remote plasma region to produce a plasma effluent of the first halogen-containing precursor. The methods may include flowing the plasma effluent into a processing region of the semiconductor processing chamber. A substrate may be disposed within the processing region. The substrate may include a groove formed through a plurality of stacked layers, the stacked layers including alternating silicon nitride layers and silicon oxide layers. The methods may include flowing a second halogen-containing precursor directly into the processing region of the semiconductor processing chamber. The second halogen-containing precursor includes fluorine. The methods may include laterally etching the silicon nitride layer. The methods may include stopping the flow of the halogen-containing precursor after a first period of time. The methods may include purging the processing region with a purge precursor.

[0009] In some embodiments, the method may include flowing a sulfur-containing precursor into a remote plasma region of a semiconductor processing chamber. The second halogen-containing precursor includes chlorine, bromine, or iodine. The method may include repeating the method for at least 10 cycles. The first time period may be greater than or about 30 seconds. The method may include flowing argon or nitrogen along with the first halogen-containing precursor.

[0010] Some embodiments of the present technology may include methods of etching silicon-containing materials. The methods may include flowing a first fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber. The methods may include flowing a sulfur-containing precursor into a remote plasma region of a semiconductor processing chamber. The methods may include forming a plasma in the remote plasma region to produce plasma effluents of a first fluorine-containing precursor and a sulfur-containing precursor. The methods may include flowing the plasma effluent into a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The substrate may include grooves formed through a plurality of stacked layers, the stacked layers including alternating silicon nitride layers and silicon oxide layers. The methods may include flowing a second fluorine-containing precursor to a processing region of the semiconductor processing chamber. The second fluorine-containing precursor may bypass the remote plasma region. The methods may include isotropically etching the silicon nitride layer.

[0011] Such techniques can provide many benefits over conventional systems and techniques. For example, the process can selectively and isotropically etch silicon nitride within a semiconductor structure. In addition, the process can protect exposed oxide during the etching process. These and other embodiments and their many advantages and features are described in more detail in conjunction with the following description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The nature and advantages of the technology disclosed herein may be further understood by referring to the rest of the specification and the accompanying drawings.

[0013] Figure 1 Depicted is a top plan view of one embodiment of an example processing system in accordance with some embodiments of the present technology.

[0014] Figure 2A A schematic cross-sectional view of an example processing chamber is shown in accordance with some embodiments of the present technology.

[0015] Figure 2B Some embodiments of the present technology are shown. Figure 2A Detailed view of a portion of a processing chamber illustrated in FIG.

[0016] Figure 3 Depicted is a bottom plan view of an example sprinkler head in accordance with some embodiments of the present technology.

[0017] Figure 4 Depicted are example operations in a method according to some embodiments of the present technology.

[0018] Figures 5A to 5C A cross-sectional view of a substrate in process is shown according to some embodiments of the present technology.

[0019] Several drawings are included in a schematic manner. It should be understood that the drawings are for illustrative purposes only and should not be considered to be drawn to scale unless specifically stated to be drawn to scale. In addition, as schematic diagrams, the drawings are used to aid understanding and may not include all aspects or information compared to realistic representations and may include exaggerated material for illustrative purposes.

[0020] In the drawings, similar components and / or features may have the same reference numerals. Further, components of the same type may be distinguished by appending a letter after the reference numeral that distinguishes the similar components. If only the first reference numeral is used in the specification, the description applies to any similar component having the same first reference numeral, regardless of the second symbol. DETAILED DESCRIPTION

[0021] In the transition from 2D NAND to 3D NAND, many process operations are modified from vertical operations to horizontal operations. In addition, as the number of cells formed in the 3D NAND structure increases, the aspect ratio of memory holes and other structures will increase, sometimes significantly. During 3D NAND processing, the stack of placeholder layers and dielectric materials can form an inter-electrode dielectric layer or IPD layer. Various operations can be performed on these placeholder layers to place the structure before the material is completely removed and replaced with metal. Although metallization can be incorporated on one side of the cell structure, operations may have been performed on the other side of the structure before, such as forming a floating gate or a charge trap layer. Although these layers can be formed in the memory hole, crosstalk may occur between vertically separated memory cells. One way to reduce this communication may include etching the placeholder material before forming these layers to allow the dielectric material to further separate the individual cell material layers from adjacent cells.

[0022] Many conventional techniques utilize wet etching to access individual cell placeholder materials to etch sideways into the placeholder materials prior to forming layers such as charge trap layers. However, wet etching can be more aggressive than other etching techniques, and wet etching can etch placeholder materials more than is necessary or desired. For example, wet etching may over-etch certain features. Additionally, wet etching of small form factor structures may cause pattern collapse or deformation due to the surface tension of the etchant. The use of wet etchants may also require subsequent operations to remove residues formed within trenches or holes. Dry etching techniques may also be performed, however, many dry etchants utilized additionally etch silicon and silicon oxide, reducing the selectivity of the process.

[0023] The present technology overcomes these problems by performing a dry etching process that selectively etches silicon nitride laterally while limiting the etching of the oxide. By utilizing a specific precursor combination, the exposed surface of the oxide can be protected during the etching process. In this way, the protective material can allow an etching operation to be performed that may not remove or only minimally remove the underlying structural material.

[0024] Although the remainder of the disclosure will routinely reference specific etching processes using the disclosed techniques, it will be readily appreciated that the systems and methods are equally applicable to deposition and cleaning processes that may occur in the chamber. Thus, the techniques should not be viewed as limited to techniques used only with these etching processes or chambers. Furthermore, although an example chamber is described as providing a basis for the present techniques, it should be appreciated that the present techniques are applicable to virtually any semiconductor processing chamber that can allow for the described single chamber operation.

[0025] Figure 1 A top plan view of one embodiment of a processing system 100 showing deposition, etching, baking and hardening chambers according to embodiments. In the figure, a pair of front-opening unified chambers 102 supply substrates of various sizes, which are received by a robot arm 104 and placed into a low pressure holding area 106, and then placed into one of the substrate processing chambers 108a to 108f, which are arranged in a series block 109a to 109c. A second robot arm 110 can be used to transport substrate wafers from the holding area 106 to the substrate processing chambers 108a to 108f and back. Each substrate processing chamber 108a to 108f can be configured to perform a number of substrate processing operations, including the dry etching process described herein, as well as cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, degassing, orientation and other substrate processes.

[0026] The substrate processing chambers 108a-108f may include one or more system components for depositing, annealing, curing and / or etching dielectric films on substrate wafers. In one configuration, two pairs of processing chambers of the processing chambers, such as 108c and 108d and 108e and 108f, may be used to deposit dielectric materials on substrates, and a third pair of processing chambers of the processing chambers, such as 108a and 108b, may be used to etch the deposited dielectric. In another configuration, all three pairs of chambers, such as 108a-108f, may be configured to etch dielectric films on substrates. Any one or more of the processes described herein may be performed in one or more chambers separate from the manufacturing system as shown in the various embodiments. It will be appreciated that other configurations of chambers for deposition, etching, annealing and curing of dielectric films are contemplated.

[0027] Figure 2A A cross-sectional view of an example processing chamber system 200 is shown with separated plasma generation regions within the processing chamber and which may be configured to perform processes as further described below. During etching of films such as titanium nitride, tantalum nitride, tungsten, silicon, polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, etc., a process gas may be flowed into a first plasma region 215 through a gas inlet assembly 205. A remote plasma system 201 may optionally be included in the system and may process a first gas which then travels through the gas inlet assembly 205. The inlet assembly 205 may include two or more different gas supply channels, wherein a second channel may bypass the RPS 201, if included.

[0028] A cooling plate 203, a face plate 217, an ion suppressor 223, a showerhead 225, and a substrate support 265 having a substrate 255 disposed thereon are shown and may include each of the above depending on the embodiment. The pedestal 265 may have heat exchange channels through which a heat exchange fluid flows to control the temperature of the substrate, which may be operated to heat and / or cool the substrate or wafer during processing operations. Embedded resistive heater elements may also be used to resistively heat the wafer support plate of the pedestal 265 (which may include aluminum, ceramic, or a combination thereof) to achieve relatively high temperatures, such as from up to or about 100° C. to greater than or about 1100° C.

[0029] The faceplate 217 may be pyramidal, conical, or other similar structures, with a narrow top portion extending to a wide bottom portion. As shown, the faceplate 217 may additionally be flat and include a plurality of through-channels for distributing the process gas. For more uniform delivery to the first plasma region 215, depending on the use of the RPS 201, the plasma generating gas and / or plasma excitation species may be passed through the faceplate 217. Figure 2B Multiple holes in panel 217 are shown.

[0030] An example configuration may include opening the gas inlet assembly 205 into a gas supply region 258 separated from the first plasma region 215 by a faceplate 217, such that the gas / species flows into the first plasma region 215 through holes in the faceplate 217. Structural and operational features may be selected to prevent significant backflow of plasma from the first plasma region 215 back into the supply region 258, the gas inlet assembly 205, and the fluid supply system 210. The faceplate 217 (or the conductive top of the chamber) and the showerhead 225 are shown with an insulating ring 220 located between the features, which allows an AC potential to be applied to the faceplate 217 relative to the showerhead 225 and / or the ion suppressor 223. The insulating ring 220 may be located between the faceplate 217 and the showerhead 225 and / or the ion suppressor 223, so that a capacitively coupled plasma (CCP) can be formed in the first plasma region. A baffle (not shown) may additionally be located in the first plasma region 215, or otherwise coupled to the gas inlet assembly 205, to affect the flow of fluid through the gas inlet assembly 205 into the region. In some embodiments, additional plasma sources may be utilized, including an inductively coupled plasma source extending about the chamber or in fluid communication with the chamber, as well as additional plasma generation systems, such as a microwave plasma generation system.

[0031] The ion suppressor 223 may include a plate or other geometric structure defining a plurality of holes throughout the structure, the holes being configured to suppress the migration of ionically charged species away from the first plasma region 215 while allowing uncharged neutral or radical species to pass through the ion suppressor 223 into an activated gas delivery region located between the suppressor and the showerhead. In embodiments, the ion suppressor 223 may include a perforated plate having a plurality of hole configurations. These uncharged species may include highly reactive species that are transported through the holes along with a less reactive carrier gas. As noted above, the migration of ionic species through the holes may be reduced, and in some cases completely suppressed. Controlling the amount of ionic species passing through the ion suppressor 223 may advantageously increase control over the gas mixture in contact with the underlying wafer substrate, which in turn may increase control over the deposition and / or etching characteristics of the gas mixture. For example, adjusting the ion concentration of the gas mixture may significantly change the etch selectivity, such as SiNx:SiOx etch ratio, Si:SiOx etch ratio, etc. In alternative embodiments of performing deposition, it may also shift the balance of conformal-to-flowable style deposition of dielectric materials.

[0032] The plurality of holes in the ion suppressor 223 may be configured to control the flow of activated gas (i.e., ion species, radical species, and / or neutral species) through the ion suppressor 223. For example, the aspect ratio of the holes or the diameter to length of the holes and / or the geometry of the holes may be controlled to reduce the flow of ionized charged species in the activated gas through the ion suppressor 223. The holes in the ion suppressor 223 may include a conical portion facing the plasma excitation region 215 and a cylindrical portion facing the showerhead 225. The shape and size of the cylindrical portion may be determined to control the flow of ion species through the showerhead 225. An adjustable electrical bias may also be applied to the ion suppressor 223 as an additional means of controlling the flow of ion species through the suppressor.

[0033] The ion suppressor 223 can function to reduce or eliminate the amount of ionically charged species that travel from the plasma generation region to the substrate. Uncharged neutral and radical species may still pass through the openings in the ion suppressor and react with the substrate. It should be noted that in embodiments, the ionically charged species in the reaction region surrounding the substrate may not be completely eliminated. In some instances, it is desirable to allow the ion species to reach the substrate for etching and / or deposition processes. In these instances, the ion suppressor can help control the concentration of the ion species in the reaction region to a level that is conducive to the process.

[0034] The showerhead 225 in combination with the ion suppressor 223 can allow the plasma present in the first plasma region 215 to avoid directly exciting the gases in the substrate processing region 233, while still allowing the excited species to travel from the chamber plasma region 215 into the substrate processing region 233. In this way, the chamber can be configured to prevent the plasma from contacting the etched substrate 255. This can advantageously protect the various complex structures and films patterned on the substrate, which may be damaged, misaligned, or warped if directly contacted by the generated plasma. In addition, the rate of etching of oxide species may increase when the plasma is allowed to contact the substrate or close to the level of the substrate. Therefore, if the exposed area of ​​the material is an oxide, the material can be further protected by maintaining the plasma at a remote location from the substrate.

[0035] The processing system may further include a power supply 240 electrically coupled to the processing chamber to supply electrical power to the faceplate 217, the ion suppressor 223, the showerhead 225, and / or the pedestal 265 to generate plasma in the first plasma region 215 or the processing region 233. The power supply may be configured to deliver an adjustable amount of power depending on the process being performed. This configuration may allow an adjustable plasma to be used in the process being performed. Unlike a remote plasma unit that typically has an on or off function, an adjustable plasma may be configured to deliver a specific amount of power to the plasma region 215. This in turn may allow specific plasma characteristics to be developed so that precursors may be dissociated in a specific manner to enhance the etch profile produced by these precursors.

[0036] A plasma may be ignited in the chamber plasma region 215 above the showerhead 225 or in the substrate processing region 233 below the showerhead 225. A plasma may exist in the chamber plasma region 215 to generate radical precursors from, for example, an inflow of a fluorine-containing precursor or other precursor. An AC voltage, typically in the radio frequency (RF) range, may be applied between a conductive top portion of the processing chamber, such as the faceplate 217, and the showerhead 225 and / or the ion suppressor 223 to ignite a plasma in the chamber plasma region 215 during deposition. The RF power supply may generate a high RF frequency of 13.56 MHz, but may also generate other frequencies alone or in combination with the 13.56 MHz frequency.

[0037] Figure 2B A detailed view 253 is shown of features that affect the distribution of process gases through panel 217. Figure 2A and 2B As shown, the faceplate 217, the cooling plate 203, and the gas inlet assembly 205 intersect to define a gas supply region 258 into which a process gas may be delivered from the gas inlet 205. The gas may fill the gas supply region 258 and flow through the holes 259 in the faceplate 217 to the first plasma region 215. The holes 259 may be configured to direct flow in a substantially unidirectional manner such that the process gas may flow into the processing region 233, but may be partially or completely prevented from flowing back into the gas supply region 258 after passing through the faceplate 217.

[0038] The gas distribution assembly (e.g., showerhead 225) used in the processing chamber block 200 may be referred to as a dual channel showerhead (DCSH) and may be used in a plurality of processes. Figure 3 The dual channel showerhead may provide for an etching process that allows separation of the etchants outside of the processing region 233 to provide limited interaction with chamber components and each other before being delivered to the processing region.

[0039] The sprinkler head 225 may include an upper plate 214 and a lower plate 216. The plates may be coupled to each other to define a volume 218 between the plates. The plates may be coupled to provide a first fluid passage 219 through the upper and lower plates, and a second fluid passage 221 through the lower plate 216. The formed passages may be configured to provide fluid access from the volume 218 through the lower plate 216 only through the second fluid passage 221, and the first fluid passage 219 may be fluidly isolated from the volume 218 between the plates and the second fluid passage 221. The volume 218 may be fluidly accessed through the sides of the gas distribution assembly 225.

[0040] Figure 3 FIG. 3 is a bottom view of a showerhead 325 for use with a processing chamber according to an embodiment. The showerhead 325 may correspond to Figure 2A . To control and influence the flow of precursors through the showerhead 225, the through-holes 365 showing a view of the first fluid channel 219 can have a variety of shapes and configurations. The small holes 375 showing a view of the second fluid channel 221 can be substantially evenly distributed on the surface of the showerhead, even between the through-holes 365, and can help provide a more evenly mixed precursor as it leaves the showerhead than other configurations.

[0041] The chambers discussed above can be used to perform example methods, including etching methods. Figure 4 , which shows example operations in method 400 according to an embodiment of the present technology. Prior to the first operation of the method, the substrate may be processed in one or more ways before being placed in a processing area of ​​a chamber in which method 400 may be performed. For example, an IPD layer may be formed on the substrate, and then one or more memory holes or trenches may be formed through the stack of layers. The IPD layer may include any number of materials and may include alternating layers of placeholder material and dielectric material. In an embodiment, the dielectric material may be or include silicon oxide, and the placeholder material may be or may include silicon nitride. Although the remaining disclosure will discuss silicon nitride and silicon oxide, any other known material used in these two layers may be substituted for one or more of the layers. Some or all of these operations may be performed in a chamber or system as described above, or some or all of these operations may be performed in different chambers on the same system tool, which may include the chamber in which the operations of method 400 are performed.

[0042] Method 400 may include, at operation 405, flowing a fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber. An example chamber may be chamber 200 described above, which may include one or both of RPS unit 201 or first plasma region 215. Either or both of these regions may be the remote plasma region used in operation 405. At operation 410, a plasma may be generated within the remote plasma region, which may generate plasma effluents of the fluorine-containing precursor. At operation 415, the plasma effluents may flow to a processing region of the chamber. In some embodiments, method 400 may include, at operation 420, flowing one or more precursors directly to the processing region, bypassing the remote plasma region. In some embodiments, at operation 425, as appropriate, the plasma effluents may interact with the substrate in the processing region and may passivate or protect certain portions of the structure. For example, in some embodiments, the plasma effluents may passivate oxide materials. As noted, the substrate may include a silicon or silicon-containing substrate or wafer on which multiple material layers (e.g., alternating silicon oxide layers and silicon nitride layers) have been formed. A memory hole or trench extending to the substrate level can be formed through the stacked layers, which can provide an exposed portion of the substrate at the bottom of the hole or trench. In this way, within the memory hole structure, there can be exposed areas of silicon nitride, silicon oxide, and silicon or some silicon-containing material.

[0043] The formation of the holes or grooves may occur in a different chamber or at a previous operation step. If performed in the same chamber as method 400, the exposed portion of the surface of the substrate may be relatively clean or neat. However, if the process is performed in a different chamber or in a different environment, a native oxide may be formed over the exposed portion of the substrate through the holes or grooves. The native oxide may be different from the oxide formed in the alternating layers of the memory structure. For example, although the silicon oxide layer that can be used to divide the memory cells may be a relatively high quality oxide, the native oxide may be a relatively lower quality oxide and may be relatively porous compared to the silicon oxide layer.

[0044] The etching process for removing silicon nitride can have a relatively high selectivity to silicon oxide, such as a selectivity greater than or about 100:1 or higher. However, in some structures, the amount of silicon nitride to be removed can be from a few nanometers to a fraction of a micron or more. For example, in some embodiments, the amount of silicon nitride to be recessed can be from tens of nanometers to hundreds of nanometers. Such an amount of material to be etched can occur over a relatively long etching period. The selectivity of the nitride removal process to the oxide can be operated in part based on the resistance of the oxide to the etchant, which can include several fluorine-containing materials. Fluorine may also eventually penetrate into portions of the silicon oxide material, producing volatile materials that will also remove the silicon oxide material. However, this process typically includes an incubation period in which the fluorine slowly interacts with the oxide material. Depending on the quality of the oxide, the energy of the fluorine, and other processing conditions, the incubation can occur for up to 2 minutes or longer, such as up to 5 minutes, up to 10 minutes or longer. Thus, by forming a passivation of silicon oxide, the oxide material may be affected in a limited manner, while the process may laterally or isotropically etch silicon nitride at operation 430 .

[0045] The radical fluorine effluents may contact the semiconductor structure and penetrate the formed trenches. The exposed surface of the silicon oxide may not be affected by the fluorine plasma effluents, or may be minimally affected by the fluorine plasma effluents, while the silicon nitride may be laterally etched between the blocks of silicon oxide. Furthermore, as will be explained below, in some embodiments, by utilizing certain fluorine-containing precursors as well as additive precursors, a passivation layer may be formed over the exposed surface of the silicon oxide, and a polymeric protective layer may be formed over the material.

[0046] The extent of this damage or interaction may be related to the power of the plasma used to form the fluorine-containing plasma effluent and the distance that the formed effluent travels. For example, by utilizing a remote plasma, a relatively low plasma power (e.g., less than 5 kW, less than or about 3 kW, less than or about 1 kW, less than or about 500 W or less) may be used, which may limit the energy of the plasma effluent and also limit the complete dissociation of the precursor material. In addition, by forming a remote plasma (which may include ion filtering before delivery to the substrate as explained above), the extent to which the ion plasma effluent interacts with the silicon nitride structure may be limited. For example, the local plasma may retain sufficient energy at the wafer level to damage at least the upper layers of silicon oxide or silicon nitride contained in the stack through the bombardment process. Further, the plasma power may be pulsed, which may further reduce the effective plasma power. In addition, the ion effluent is generally directional, which may be conducive to anisotropic etching of surfaces perpendicular to the effluent delivery direction, but may be disadvantageous to lateral etching. The present technology utilizes neutral or radical species generated in the plasma to generate an isotropic etchant that can laterally etch silicon nitride. As the total flow rate is reduced and / or the pressure is increased, as described below, the plasma power can be further reduced while the plasma is continued, such as below or about 400 W, below or about 300 W, below or about 200 W, below or about 100 W, or less. This can further limit fluorine dissociation and additive precursor dissociation, which can improve the selective etching of nitride (which can occur more easily) while oxide etching can occur in the initial period or after saturation. In addition, the additive precursor can have reduced dissociation, which can promote the development of a passivation layer in some embodiments.

[0047] In some embodiments, the etching process can continue for a first time period. After the first time period, the flow of the fluorine-containing precursor can be stopped as the plasma is formed. A purge can then be performed at operation 435 as appropriate, which can remove residual etchant materials, etching byproducts, or other materials from the chamber. The purge can be performed using any number of chemically inert materials (such as nitrogen or a rare gas) that can be used to purge the processing area of ​​the chamber. The purge process can improve the etch selectivity by accelerating the removal of byproducts and less favorable plasma effluents, and reduce the residence time of these materials in the processing area. For example, this can promote lateral etching of silicon nitride while reducing exposure and impact to silicon oxide.

[0048] The first time period can be sufficient to produce etching while limiting the residence time that may begin to affect the oxide surface. For example, in some embodiments, the first time period can be greater than or about 5 seconds, and can be greater than or about 10 seconds, greater than or about 15 seconds, greater than or about 20 seconds, greater than or about 25 seconds, greater than or about 30 seconds, greater than or about 35 seconds, greater than or about 40 seconds, greater than or about 45 seconds, greater than or about 50 seconds, greater than or about 55 seconds, greater than or about 60 seconds, greater than or about 2 minutes, greater than or about 3 minutes, greater than or about 4 minutes, greater than or about 5 minutes, or longer. However, in order to limit additional effects, in some embodiments, the first time period can be less than or about 5 minutes, less than or about 4 minutes, less than or about 3 minutes, less than or about 2 minutes, or shorter.

[0049] As will be described below, the precursors used in the present technology may include fluorine-containing precursors as well as additional precursors. An example fluorine-containing precursor may be nitrogen trifluoride (NF3), which may be flowed into a remote plasma region that may be separate from but fluidly coupled to the processing region. Other fluorine sources may be used in conjunction with nitrogen trifluoride or as a substitute for nitrogen trifluoride. Generally, the fluorine-containing precursor may be flowed into the remote plasma region, and the fluorine-containing precursor may include at least one precursor selected from the group consisting of atomic fluorine, diatomic fluorine, nitrogen trifluoride, carbon tetrafluoride, hydrogen fluoride, xenon difluoride, and various other fluorine-containing precursors that may be used or useful for semiconductor processing.

[0050] In some embodiments, the fluorine-containing precursor may be characterized by an increased fluorine content in the molecule of the fluorine-containing precursor. For example, in some embodiments, the fluorine-containing precursor may be characterized by the molecular formula XF y . X can be any number of materials or periodic elements, and y can be a number greater than or about 1, greater than or about 2, greater than or about 3, greater than or about 4, greater than or about 5, greater than or about 6, or more. In some embodiments, fluorine can be replaced by additional halogen elements. The marking of the chemical formula may be only to indicate the ratio and may not limit the precursor. For example, the listed chemical formula may include X2F8, where y is 8. Other examples covered by the chemical formula will also be readily understood. Element X can be any of a variety of elements that can form compounds with fluorine or other halides.

[0051] For example, non-limiting examples may include any other non-metal that can bond to a halide (such as sulfur or phosphorus), as well as any other poor metal, transition metal or other element that can chemically bond to a halogen element. As non-limiting examples, fluorine-containing precursors may include phosphorus pentafluoride, sulfur hexafluoride and other fluorine-containing materials or halogen-containing materials. These materials may produce a large amount of plasma effluent materials that may increase etching. For example, using sulfur hexafluoride, a variety of elements including S, F, SF, SF2, SF3, SF4, SF5, F2, S2F8, and many other free radicals and neutral species may be generated and help with etching.

[0052] While any number of halogen-containing precursors (such as fluorine-containing precursors) may be used, certain materials (such as phosphorus and sulfur) may promote selectivity over other materials (such as nitrogen trifluoride), for example, because the silicon oxide material may provide additional impact. For example, sulfur compounds and phosphorus compounds may produce a type of passivation or protective material on the exposed surface of the silicon oxide. For example, sulfur and phosphorus are sufficiently large elements that a certain amount of polymerization may occur to produce a type of bridge polymer above the surface of the oxide. The sulfur may bond to the oxygen surface and be incorporated into the film while retaining one or more fluorine atoms, which may protect the surface from additional fluorination and reaction with the oxygen surface. This may allow etching of the nitride structure while maintaining or limiting any impact on the oxide layer, as no inference may be formed on the nitride.

[0053] In some embodiments, a sulfur-containing precursor may flow with the fluorine-containing precursor. An example sulfur-containing precursor may be hydrogen sulfide (H2S), which may flow into the remote plasma region along with the fluorine-containing precursor. Other sulfur sources may be used in combination with or as an alternative to hydrogen sulfide. In general, a sulfur-containing precursor may flow into the remote plasma region, and the sulfur-containing precursor may include at least one precursor selected from the group consisting of hydrogen sulfide, carbon disulfide, disulfur dichloride, disulfur tetrachloride, and various other sulfur-containing precursors used in or beneficial to semiconductor processing. As discussed above, sulfur may improve selectivity relative to other materials (such as fluorine-containing precursors) because of the formation of passivating or protective materials on the exposed surface of the silicon oxide material. Therefore, flowing a sulfur-containing precursor along with the fluorine-containing precursor can balance the etch selectivity by increasing the formation of passivating or protective materials.

[0054] In some embodiments, the additive precursor may flow with the fluorine-containing precursor and the sulfur-containing precursor (if present). The additive precursor may be or may include a halogen-containing precursor that includes a halogen other than fluorine. For example, the additive precursor may include a precursor that includes a Group VII element, or a halogen, along with any Group III, Group IV, Group V, or Group VI element (and in any combination). Example materials may be characterized by the formula Xa Y b , wherein X comprises any Group III, IV, V or VI element, Y comprises chlorine, bromine or iodine, a is 1, 2 or 3, and b is 3, 4, 5, 6, 7, 8 or 9. The additive precursor formulation may also encompass precursors characterized by the formula R1R2R3XY, wherein X may be any Group IV element, Y may be chlorine, bromine or iodine, and R1 to R3 may be any combination, H, methyl, ethyl or other hydrocarbons, additional halogens or additional Group IV elements bonded to any of the other mentioned chain-extending materials. For example, but not limited to the precursors covered by the above chemical formula, exemplary precursors may include any combination of silicon and chloride, such as carbon tetrachloride and / or disilicon hexachloride, and similarly, precursors may include carbon and chloride, germanium and chloride, silicon and fluorine, carbon and fluorine, germanium and fluorine, silicon and bromine, carbon and bromine, germanium and bromine, silicon and iodine, carbon and iodine, germanium and iodine, selenium and fluorine, bromine, chlorine or iodine, tellurium and fluorine, bromine, chlorine or iodine, phosphorus and fluorine, bromine, chlorine or iodine, and arsenic and fluorine, bromine, chlorine or iodine. In addition, the added precursor may be characterized by one or more methyl groups, such as trimethylsilane.

[0055] The additive precursor can be operated as a passivation precursor as described above. For example, although the fluorine-containing precursor can etch materials (including silicon nitride and silicon oxide) after sufficient exposure or without sufficient passivation, the additive precursor can perform the same passivation operation as described above without etching the structure. Because other halogen-containing precursors can perform similar functions to the above-mentioned fluorine precursors, the same operation can be performed, while the etching operation is further controlled by limiting the addition of additional fluorine. Although any precursor covered by the above chemical formula can be used as an additive precursor, in some embodiments, a precursor characterized by a silicon-silicon, carbon-carbon, germanium-germanium or similar atomic bonded structure can be used because low-power plasma may more easily destroy this bond on the auxiliary part (ancillary moieties) of the precursor. The additive precursor can also promote the healing of the etched surface. For example, the additive precursor may include silicon as described above. Once enhanced by plasma, if etched, the silicon-containing precursor can provide silicon back to silicon oxide. When the structure is removed from the processing environment, the added silicon may be oxidized, wherein the water in the atmosphere can react with the silicon to restore the oxidized surface. Thus, the procedure can limit, prevent, or regenerate silicon oxide, which can maintain the silicon oxide layer during the etching process. In some embodiments where the additive precursor includes fluorine, the additive precursor can replace the fluorine-containing precursor.

[0056] In some embodiments of the present technology, additional precursors may be delivered with the fluorine-containing precursor. For example, a hydrogen-containing precursor may be delivered, or one or more other precursors may be delivered, such as an argon-containing precursor, a nitrogen-containing precursor, a helium-containing precursor, and an oxygen-containing precursor, or other precursors. Hydrogen and argon can be easily ionized relative to helium, which can facilitate processing in some embodiments. The hydrogen-containing precursor may be or may include hydrogen, a hydrocarbon, or any hydrogen-containing precursor. Examples of oxygen-containing precursors may be or may include water vapor, hydrogen peroxide, oxygen, ozone, nitrous oxide, nitric oxide, or an energized oxygen-containing material, although as previously explained, in some embodiments, the oxygen-containing precursor may not be plasma enhanced to limit interaction with the silicon nitride material through the trench to be subsequently etched. The present technology may additionally etch silicon, and providing an amount of oxygen-containing precursor may facilitate etching.

[0057] Without being bound by any particular theory, providing materials such as or including hydrogen or argon, as well as other precursors, can facilitate the etching process by providing additional electrons to the process. While fluorine can be a pseudoscavenger of electrons in the plasma, the additional precursor can contribute additional electrons, which can increase the electron density within the plasma, improving the etching process and selectivity to nitrides. Therefore, in some embodiments, a flow rate ratio of the fluorine-containing precursor to the additional precursor can be maintained. For example, the flow rate ratio of the additive precursor and / or the additional precursor (such as hydrogen or argon) can be maintained at least about 1:2 relative to the fluorine-containing precursor, and can be maintained at greater than or about 1:1, greater than or about 1.5:1, greater than or about 2.0:1, greater than or about 2.5:1, greater than or about 3.0:1, greater than or about 3.5:1, greater than or about 4.0:1, or more. However, the flow rate ratio can be maintained to limit dilution, once sufficiently high that additional etching may be inhibited, and thus in some embodiments, the flow rate ratio of the additional precursor to the fluorine-containing precursor can be maintained at less than or about 10.0:1, less than or about 9.0:1, less than or about 8.0:1, less than or about 7.0:1, less than or about 6.0:1, less than or about 5.0:1, less than or about 4.0:1, less than or about 3.0:1, less than or about 2.0:1, less than or about 1.0:1, or less. For example, an additional precursor can be included to facilitate plasma formation, such as argon, which can provide electrons. However, when the added precursor is characterized by a lower ionization energy than argon, argon can be removed from the plasma precursor, which can improve selectivity.

[0058] In some embodiments, any one or more of the precursors discussed above may bypass the remote plasma region and flow directly to the processing region of the semiconductor processing chamber. By bypassing the remote plasma region, plasma effluents of the precursors that flow directly to the processing region may not be formed. However, it is contemplated that plasma effluents may be formed due to contact with plasma effluents generated in the remote plasma region and flowing to the processing region. For example, a second fluorine-containing precursor may bypass the remote plasma region and flow directly to the processing region. The second fluorine-containing precursor may be any of the fluorine-containing precursors mentioned above, and in embodiments, may be or may include: atomic fluorine, diatomic fluorine, or a precursor characterized by the chemical formula X a Y b A second fluorine-containing precursor wherein X comprises any Group III, Group IV, Group V or Group VI element, Y comprises chlorine, bromine or iodine, a is 1, 2 or 3, and b is 3, 4, 5, 6, 7, 8 or 9. For example, the second fluorine-containing precursor may be or may include: chlorine trifluoride, chlorine pentafluoride, bromine trifluoride, bromine pentafluoride, iodine trifluoride, iodine pentafluoride, iodine heptafluoride and various other fluorine-containing precursors that may be used or facilitate semiconductor processing. In addition, the carrier gas or inert gas may also bypass the remote plasma region and flow directly to the processing region of the semiconductor processing chamber.

[0059] Precursors provided directly to the process may flow into the process chamber separately from the plasma effluents while bypassing the remote plasma region. By flowing the precursors directly to the process chamber, the presence of excited plasma effluents and unexcited precursors may be adjusted within the process region, which may allow for adjustment of the etch rate and / or etch selectivity. For example, by flowing additional fluorine-containing precursors to the process region, additional fluorine radicals may be formed, which may increase the etch rate and / or decrease the etch selectivity. Conversely, by reducing or stopping the flow of additional fluorine-containing precursors to the process region, fewer fluorine radicals in the process region may decrease the etch rate and / or increase the etch selectivity.

[0060] Process conditions may also affect the operations performed in method 400. In embodiments, each operation of method 400 may be performed during a constant temperature, and in some embodiments, the temperature may be adjusted during different operations. The temperature may be maintained in any range, however, at higher temperatures, further dissociation of the fluorine-containing material may occur, which may produce more fluorine radicals. As the amount of fluorine radicals increases, the oxide may begin to etch more easily, and the selectivity may decrease. Therefore, in some embodiments, the temperature may be maintained at less than or about 700° C., and the temperature may be maintained at less than or about 650° C., less than or about 600° C., less than or about 550° C., less than or about 500° C., or less. In some embodiments, the substrate, pedestal, or chamber temperature during nitride or silicon etching can be maintained at a temperature of less than or about 400°C, and in some embodiments, the temperature can be maintained at less than or about 350°C, less than or about 300°C, less than or about 250°C, less than or about 200°C, less than or about 150°C, less than or about 100°C, less than or about 50°C, less than or about 25°C, less than or about 10°C, less than or about 0°C, less than or about -10°C, less than or about -20°C, less than or about -30°C, less than or about -40°C, less than or about -50°C, less than or about -60°C, or less.

[0061] As the process temperature is reduced, the selectivity of the precursor can be enhanced to reduce or limit free hydrogen. For example, while methyl groups can still beneficially passivate exposed oxide surfaces, as the temperature is reduced to below or about 20° C., free hydrogen may produce ammonia or fluorimide, which may etch oxide by producing ammonium fluorosilicate as a byproduct. Therefore, in some embodiments, the hydrogen concentration can be limited to less than 1:1 to any other element of the precursor, and based on the plasma power, can be limited to methyl groups, which can passivate exposed oxide surfaces during nitride etching.

[0062] In some embodiments, the process can be performed at various pressures, which can facilitate operation in any number of processing chambers. For example, the process can be performed in a chamber that can provide (e.g., with a turbomolecular pump) a pressure of less than or about 10 mTorr or less. In addition, the pressure in the chamber can be maintained at a higher pressure, which can increase the associated etch rate, and the pressure in the processing chamber can be maintained at greater than or about 1 Torr, and can be maintained at greater than or about 2 Torr, greater than or about 5 Torr, greater than or about 10 Torr, greater than or about 50 Torr, greater than or about 100 Torr, greater than or about 200 Torr, or more.

[0063] Precursor and total flow rates may also contribute to improved silicon nitride etching. For example, argon, helium, nitrogen, or other plasma-stabilizing precursors may be delivered or maintained at flow rates less than or about 100 sccm, and may be maintained at less than or about 90 sccm, less than or about 80 sccm, less than or about 70 sccm, less than or about 60 sccm, less than or about 50 sccm, less than or about 40 sccm, less than or about 30 sccm, less than or about 20 sccm, less than or about 10 sccm, or less. By reducing the flow of the plasma-stabilizing precursor, dissociation may be reduced, a lower plasma power may be used to generate the plasma, and etching may be controlled to increase nitride etching, which may occur more easily relative to oxide etching. The flow of the additive precursor, the first halogen-containing precursor, the second halogen-containing precursor, or the total precursor flow may be maintained at less than or about any of the recorded flow rates, which may further control dissociation and enhance the selectivity of nitride etching relative to oxide etching.

[0064] By performing a certain amount of etching followed by a certain amount of purging, a controlled lateral or isotropic etch of silicon nitride can be performed. To further facilitate etching, the present technique can be performed in several cycles to renew the silicon oxide, allow removal of etch byproducts, and facilitate delivery of etchant into the lateral recesses of the silicon nitride. In some embodiments, depending on factors such as the extent of silicon nitride etching to be performed or other effects of the process, the process (including optional purging) can be performed in greater than or about 2, greater than or about 3, greater than or about 4, greater than or about 5, greater than or about 10 cycles, greater than or about 20 cycles, greater than or about 50 cycles, greater than or about 100 cycles, greater than or about 200 cycles, or more.

[0065] The benefits of performing additional cycles may include: when hydrogen is combined with the etchant precursor, the hydrogen plasma effluent may beneficially interact with the silicon oxide layer of the stack to extract fluorine that may interact with the layer during each cycle. As discussed above, after the fluorine may begin to interact with the oxide structure and extend into the incubation period within the oxide structure, the silicon oxide may eventually react with the process for removing silicon nitride. However, although the hydrogen effluent may not react with the silicon oxide itself, or may only interact minimally, the effluent energy may be sufficient to extract the fluorine that has begun to interact with the silicon oxide, and the fluorine may be removed from the layer when the plasma effluent contacts the exposed surface of the silicon oxide layer. By performing a purge as described above, the removed fluorine and the reacted hydrogen can be exhausted from the chamber. This can renew the incubation period at least to some extent, and can increase the overall selectivity of the silicon nitride etching process relative to silicon oxide by removing residual etchant from the silicon oxide in each cycle. By performing the process described above, the etch selectivity of silicon nitride relative to silicon oxide can be maintained at greater than or about 10:1, and selectivities of greater than or about 15:1, greater than or about 20:1, greater than or about 30:1, greater than or about 50:1, greater than or about 70:1, greater than or about 100:1, or more can be produced.

[0066] See also Figures 5A to 5C , which shows a cross-sectional view of a structure 500 processed according to some embodiments of the present technology. Figure 5A As shown, substrate 505 may have multiple stacked layers covering the substrate, which may be silicon, silicon germanium, or other substrate materials. The layers may include IPD layers, which include dielectric material 510, which may be silicon oxide, alternating with placeholder material 520, which may be silicon nitride. Placeholder material 520 may be or may include a material that will be removed in subsequent operations to produce individual memory cells. Although only seven material layers are shown, the example structure may include any number of layers discussed above, and it should be understood that the drawings are merely schematic diagrams for illustrating aspects of the present technology. A trench 530, which may be a memory hole, may be defined through the stacked structure to the level of substrate 505. Trench 530 may be defined by sidewalls 532, which may be defined by alternating layers of dielectric material 510 and placeholder material 520.

[0067] exist Figure 5B The method according to the present technology (such as reference Figure 4A remote plasma of a fluorine-containing precursor (which may include additional precursors) may be formed to produce plasma effluents. The plasma effluents may be delivered to a substrate processing region where they may interact with the substrate and exposed materials. As described above, when etching silicon nitride or placeholder material 520, plasma effluents of certain precursors according to embodiments of the present technology may passivate silicon oxide or produce a protective layer 540 on the exposed area.

[0068] Figure 5C A further method or operation according to the present technology (such as reference Figure 4 For example, as the etching process continues, additional passivation or protective material 540 may extend over further exposed surfaces of dielectric material 510, which may continue to protect the material from vertical etching as the silicon nitride continues to be recessed during cycles of the process. By utilizing precursors and processing as discussed throughout the present technology, silicon nitride may be etched isotropically or laterally from between blocks of silicon oxide while limiting damage or removal of the silicon oxide.

[0069] In the foregoing description, for the purpose of explanation, many details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to a person skilled in the art that some embodiments may be practiced without some of these details or with additional details.

[0070] After several embodiments have been disclosed, those of ordinary skill in the art will recognize that various modifications, alternative configurations, and equivalents may be used without departing from the spirit of the embodiments. In addition, in order to avoid unnecessary confusion of the present technology, several well-known processes and elements are not described. Therefore, the above description should not be considered to limit the scope of the present technology. In addition, the method or process may be described as being performed sequentially or in steps, but it should be understood that the operations may be performed simultaneously or in an order different from the order listed.

[0071] Where a range of values ​​is provided, unless expressly specified herein, it is understood that each intermediate value between the upper and lower limits of that range is also specifically disclosed, with an accuracy to the smallest quantile of the unit of the lower limit. Any narrower range between any stated value or unstated intermediate value in the stated range and any other stated value or intermediate value in that stated range will be included. The upper and lower limits of such smaller ranges may be independently included in or excluded from the range, and each range in which any, no, or both limits are included in such smaller ranges is also included in the present technology, each of which is governed by any specifically excluded limits in the stated range. Where the stated range includes one or both of these limits, ranges excluding one or both of the limits included are also included.

[0072] As used herein and in the appended claims, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, reference to "a precursor" includes a plurality of such precursors and reference to "the layer" includes reference to one or more layers and equivalents thereof known to those skilled in the art, and so forth.

[0073] Furthermore, when the words “comprise,” “comprising,” “contain,” “include,” and “including” are used in the specification and the claims below, they are intended to specify the existence of stated features, integers, components, or operations, but these words do not exclude the existence or addition of one or more other features, integers, components, operations, actions, or groups.

Claims

1. A method for etching a silicon-containing material, the method comprising: flowing a first fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber; flowing a sulfur-containing precursor into the remote plasma region of the semiconductor processing chamber; forming a plasma in the remote plasma region to produce plasma effluents of the first fluorine-containing precursor and the sulfur-containing precursor; flowing the plasma effluent into a processing region of the semiconductor processing chamber, wherein a substrate is disposed within the processing region, and wherein the substrate includes trenches formed through a plurality of stacked layers, the stacked layers including alternating silicon nitride layers and silicon oxide layers; and The silicon nitride layer isotropically etched while substantially maintaining the silicon oxide.

2. The method of etching a silicon-containing material as claimed in claim 1, further comprising: A second fluorine-containing precursor is flowed to the processing region of the semiconductor processing chamber, wherein the second fluorine-containing precursor bypasses the remote plasma region.

3. The method for etching a silicon-containing material as claimed in claim 1, further comprising: After a first period of time, stopping the flow of the first fluorine-containing precursor and the sulfur-containing precursor; and The processing area is purged with a purging precursor. 4 . The method of etching a silicon-containing material as claimed in claim 1 , wherein the sulfur-containing precursor comprises hydrogen sulfide or carbon disulfide.

5. The method of etching a silicon-containing material as claimed in claim 1, further comprising: An additive precursor is flowed with the first fluorine-containing precursor, wherein the additive precursor comprises a halogen other than fluorine.

6. The method of claim 1, wherein the etch selectivity between silicon nitride and silicon oxide is greater than or about 20:

1.

7. The method of etching a silicon-containing material as claimed in claim 1, wherein the first fluorine-containing precursor comprises: sulfur, phosphorus, arsenic, silicon, carbon, selenium or tellurium.

8. The method of etching a silicon-containing material of claim 1, wherein the method is performed at a chamber operating pressure between about 10 mTorr and about 5 Torr.

9. The method of etching a silicon-containing material of claim 1, wherein the method is performed at a chamber temperature of less than or about 20°C.

10. The method of etching a silicon-containing material as claimed in claim 1, further comprising: Argon, helium, or nitrogen is flowed with the first fluorine-containing precursor and the sulfur-containing precursor.

11. The method of etching a silicon-containing material of claim 10, wherein a flow rate ratio of the argon, helium or nitrogen to the first fluorine-containing precursor is less than or about 2:

1.

12. The method of etching a silicon-containing material as claimed in claim 1, further comprising: A hydrogen-containing precursor is flowed with the first fluorine-containing precursor.

13. The method of claim 1 , further comprising: A passivation layer is formed on the silicon oxide.

14. A method for etching a silicon-containing material, the method comprising: flowing a first halogen-containing precursor into a remote plasma region of a semiconductor processing chamber, wherein the first halogen-containing precursor comprises fluorine; forming a plasma in the remote plasma region to produce a plasma effluent of the first halogen-containing precursor; flowing the plasma effluent into a processing region of the semiconductor processing chamber, wherein a substrate is disposed within the processing region, and wherein the substrate includes a trench formed through a plurality of stacked layers, the stacked layers including alternating silicon nitride layers and silicon oxide layers; flowing a second halogen-containing precursor directly to the processing region of the semiconductor processing chamber, wherein the second halogen-containing precursor comprises fluorine; laterally etching the silicon nitride layer; stopping the flow of the first halogen-containing precursor after a first period of time; and The processing area is purged with a purging precursor.

15. The method of etching a silicon-containing material as claimed in claim 14, further comprising: A sulfur-containing precursor is flowed into the remote plasma region of the semiconductor processing chamber.

16. The method of etching a silicon-containing material of claim 14, wherein the second halogen-containing precursor comprises chlorine, bromine, or iodine.

17. The method of etching a silicon-containing material as claimed in claim 14, further comprising: The method was repeated for at least 10 cycles.

18. The method of etching a silicon-containing material of claim 14, wherein the first period of time is greater than or about 30 seconds.

19. The method of etching a silicon-containing material as claimed in claim 14, further comprising: Argon or nitrogen is flowed with the first halogen-containing precursor.

20. A method of etching a silicon-containing material, the method comprising: flowing a first fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber; flowing a sulfur-containing precursor into the remote plasma region of the semiconductor processing chamber; forming a plasma in the remote plasma region to produce plasma effluents of the first fluorine-containing precursor and the sulfur-containing precursor; flowing the plasma effluent into a processing region of the semiconductor processing chamber, wherein a substrate is disposed within the processing region, and wherein the substrate defines a trench through a plurality of stacked layers, the stacked layers comprising alternating silicon nitride layers and silicon oxide layers; flowing a second fluorine-containing precursor to the processing region of the semiconductor processing chamber, wherein the second fluorine-containing precursor bypasses the remote plasma region; and The silicon nitride layer isotropically etched.

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