Implementation method of high-precision time-to-digital converter

Abstract

The invention discloses an implementation method of a high-precision time-to-digital converter, and relates to the technical field of time mode signal processing. The delay chain comprises a Start signal channel and a plurality of Stop signal channels, each delay chain corresponds to one channel, each delay chain is formed by cascading a circuit with a delay function as a delay unit, the chain structure is divided into an integral chain and a differential chain, the integral chain is that one channel corresponds to one independent delay chain, and the differential chain is that one channel corresponds to one independent delay chain. The difference chain regards two delay chains corresponding to two adjacent channels as a group, and the time difference of signals reaching the input ends of the two delay chains is maintained for 1 / 2 of the delay duration of a single-stage delay unit through a back-end constraint physical layout wiring rule, so that difference is formed. According to the invention, the maximum time resolution of TDC can reach about 12ps, and the test precision is lt; and the dynamic range is about 67 ms, so that high-precision time interval measurement capable of being dynamically calibrated is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of time mode signal processing, and in particular to a method for realizing a high-precision time-to-digital converter. Background Art

[0002] Time to digital converter (TDC) is a high-precision time measurement device. It is widely used in high-energy physics, fluorescence imaging, space exploration, astronomical observation, positron emission tomography, laser ranging, automatic driving, aerospace, radar positioning, three-dimensional imaging, fluid flow measurement, electronic instruments and other fields, and plays an extremely important role in the above fields.

[0003] The technical routes for time measurement include direct counting method, clock phase division method, interpolation delay chain method, etc. Different technical routes have a great impact on the final resolution capability. TDC is mainly implemented through two solutions: FPGA and Application Specific Integrated Circuit (ASIC). The FPGA platform has a short development cycle and can be programmed multiple times. Its resolvable time interval is mainly concentrated in the range of hundreds of picoseconds. However, the cost of implementing it under the ASIC solution is relatively high.

[0004] The resolution of current mainstream devices is between 100 picoseconds and 20 picoseconds, and it is difficult to reach the level of 10 picoseconds. The traditional high-resolution design uses enough delay units to form a delay chain, but the cost is to sacrifice area, increase power consumption and cost. Another way is to achieve it through clock phase division. In theory, the resolution will increase with the increase of phase division, but in reality, due to the existence of multiple clock domains, it will increase the difficulty of data transmission and processing, and it is usually difficult to achieve a higher resolution.

[0005] In addition, since the delay time of the delay unit changes due to temperature and voltage, the resolution and accuracy of the TDC will also change accordingly, resulting in poor INL and DNL indicators of two important accuracy parameters related to TDC; for this reason, we propose a method to implement a high-precision time-to-digital converter. Summary of the invention

[0006] The purpose of the present invention is to provide a method for realizing a high-precision time-to-digital converter, by designing an additional calibration unit to improve the linearity of the TDC and solve the problem that the time resolution in the traditional algorithm is greatly affected by the external environment.

[0007] The present invention is achieved through the following technical solutions:

[0008] The present invention is a method for implementing a high-precision time digital converter, comprising a Start signal channel, multiple Stop signal channels and a delay chain, each delay chain corresponding to a channel, the delay chain is formed by cascading a circuit with a delay function as a delay unit, and the chain structure is divided into two types: a full chain and a differential chain, and also includes a differential structure. The method for implementing the high-precision time digital converter comprises the following steps:

[0009] S1: For the whole chain mode, the decoder inputs the sampling result of each level of the trigger chain into the decoding unit, and the data flips between "0" and "1" to obtain the "fine count" result;

[0010] S2: For the differential chain mode, the same signal is input into two delay chains respectively, and then the sampling result is input into the decoding unit;

[0011] S3: In the above S2, the difference between the detailed counting results of the two delay chains is also 1 / 2 of the delay time of the single-stage delay unit, which means that the resolution is doubled, thereby achieving double precision in a physical way;

[0012] S4: For the differential structure, an algorithm is used to divide the sampling results of the trigger chain into two groups of odd and even levels, and decode them separately to obtain two groups of "fine counting" results;

[0013] S5: back-label the result to the whole chain, perform threshold expansion according to ±1, and obtain two groups of intervals with a length of 3. Take the intersection of the two intervals. If the intersection result is still an interval, take its average value.

[0014] S6: In the above S5, when the fine count is a decimal, it means that the jump is now accurately between two adjacent delay units, and the resolution is half of the delay time of a single-stage delay unit, thereby achieving double precision in an algorithmic manner;

[0015] S7: By combining algorithmic differentiation with physical differentiation, hierarchical decoding is performed based on the differential chain structure to achieve the highest precision measurement

[0016] Preferably, the whole chain, i.e., one channel corresponds to an independent delay chain, and the differential chain regards two delay chains corresponding to two adjacent channels as a group, and through the back-end constraint physical layout and wiring rules, the time difference between the signals reaching the input ends of the two delay chains is maintained at 1 / 2 the delay length of the single-stage delay unit to form a differential.

[0017] The implementation method of the high-precision time-to-digital converter also includes a calibration mode, and the implementation of the calibration mode includes the following steps:

[0018] Step 1: After dividing the system clock, input it into the delay chain in the calibration unit for propagation, and send the output of the last-stage delay unit and the input signal of the first-stage delay unit out of the chip;

[0019] Step 2: Use a phase detector to sample the signal, use the input signal as a reference signal, and determine the phase difference between the output signal and the input signal;

[0020] Step 3: Calculate the range that needs to be compensated based on the phase difference, convert it into a voltage signal through DAC, filter, amplify, and shape it, and feed the voltage back to the delay unit;

[0021] Step 4: The temperature is dynamically compensated by changing the supply voltage of the delay unit to complete the calibration.

[0022] Preferably, in step 1, the difference between the two signals is a total delay length of a delay chain, that is, one clock cycle.

[0023] In the present invention, from the perspective of TDC implementation, the design resolution based on FPGA is limited, while ASIC has higher integration and smaller size than FPGA. It can better optimize performance through customized layout and wiring, and is suitable for precision instruments. Therefore, the present invention is implemented based on the ASIC solution and is implemented using the interpolation delay chain method.

[0024] The present invention has the following beneficial effects:

[0025] The invention provides a method for realizing a high-precision time-to-digital converter, and proposes a high-resolution TDC design. S The process is implemented in the form of a chip. Based on the interpolation delay chain method, the present invention constructs a new interpolation delay chain unit, and introduces a whole chain splitting algorithm and a differential chain structure, with multiple precision modes and calibration functions;

[0026] Among them, the delay unit is temperature compensated through the calibration unit to improve stability and linearity, and the resolution is increased to ten picoseconds while saving area and cost.

[0027] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0029] Figure 1 Schematic diagram of the structure of TDC ASIC in the high-precision time-to-digital converter of the present invention;

[0030] Figure 2The basic structure diagram of the delay chain and trigger chain circuit in the high-precision time-to-digital converter of the present invention;

[0031] Figure 3 A schematic diagram of a calibration circuit in a high-precision time-to-digital converter of the present invention;

[0032] Figure 4 This is a flow chart of a method for implementing a high-precision time-to-digital converter of the present invention. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] Please refer to Figure 4 As shown, the present invention is a method for implementing a high-precision time-to-digital converter, comprising a Start signal channel, multiple Stop signal channels and delay chains, each delay chain corresponding to a channel, the delay chain is formed by cascading a circuit with a delay function as a delay unit, and the chain structure is divided into a full chain and a differential chain. The full chain, that is, one channel corresponds to an independent delay chain, and the differential chain regards two delay chains corresponding to two adjacent channels as a group, and through the back-end constraint physical layout and wiring rules, the time difference between the signal reaching the input end of the two delay chains is maintained at 1 / 2 of the delay time length of the single-stage delay unit to form a differential, high-precision time-to-digital converter implementation method, including:

[0035] For the whole chain mode, decoding requires inputting the sampling results of each level of the trigger chain into the decoding unit. The data flips between "0" and "1" to obtain the "fine counting" result.

[0036] For the differential chain mode, the same signal is input into two delay chains respectively, and then the sampling result is input into the decoding unit. At this time, the fine counting results of the two delay chains will differ by 1 / 2 of the delay time of the single-stage delay unit, which means that the resolution is doubled, and double precision is achieved in a physical way.

[0037] For the differential structure, it can also be realized by the algorithm. The sampling results of the trigger chain are divided into two groups of odd and even levels, and decoded separately to obtain two groups of "fine counting" results. The results are back-labeled to the whole chain, and the threshold is expanded by ±1. The two groups of intervals with a length of 3 are obtained. The intersection of the two intervals is taken. When the intersection result is still an interval, the average value is taken. When the fine count is a decimal, it means that the jump is now accurately between the two adjacent delay units. The resolution is half of the delay time of the single-stage delay unit, thereby realizing double precision in an algorithmic way.

[0038] By combining algorithmic differentiation with physical differentiation, hierarchical decoding is performed based on the differential chain structure to achieve the highest precision measurement.

[0039] The implementation of the calibration mode is as follows:

[0040] like Figure 3 As shown, after the system clock is divided, it is input into the delay chain in the calibration unit for propagation, and the output of the last-stage delay unit and the input signal of the first-stage delay unit are sent out of the chip. At this time, the two signals differ by the total delay length of a delay chain, that is, one clock cycle. The phase detector is used to sample the signal, and the input signal is used as the reference signal to determine the phase difference between the output signal and the input signal. The range that needs to be compensated is calculated based on the phase difference, and converted into a voltage signal through a DAC. After filtering, amplification, shaping and other processing are performed, the voltage is fed back to the delay unit, and the temperature is dynamically compensated by changing the power supply voltage of the delay unit.

[0041] like Figure 1 As shown, the present invention realizes the time interval measurement by customizing the ASIC chip, and adopts the interpolation delay chain method as the main technical route. The interpolation delay chain method represents the time interval ΔT to be measured in the form of "coarse count" + "fine count", so as to realize high-precision time measurement. The TDC ASIC design includes five main modules: counter, quantization unit, decoding unit, calibration unit and data processing. Among them, TDC chips such as Texas Instruments TDC720X series have the advantages of good time resolution and multi-channel measurement, support up to 5-10 groups of measurement channels, resolution of 55ps, two measurement modes, maximum measurement range of 8ms, and support working at an ambient temperature of -40℃-85℃.

[0042] In the present invention, the coarse count part is counted by the counter module, and starts counting under the system clock when the signal arrives. The fine count is the part that exceeds the distinguishable part of the system clock, and is quantized by the delay chain in the quantization unit. The delay chain is composed of a plurality of delay units in cascade, and the D flip-flop samples the output result of each delay unit to form a flip-flop chain; Figure 2 As shown, the decoding unit can find the jump level by decoding the sampling results of the trigger chain. The total delay time accumulated to this level is the "fine count" quantization result, that is, ΔT = kt, k represents the number of "1" in the sampling result, and t represents the time interval of each delay unit. The design consists of multiple delay chains, which are sampled corresponding to the trigger chain. It is divided into multiple modes, corresponding to different resolutions and accuracies. The chain structure and algorithm are adjusted by mode switching. The calibration unit is used to measure the current delay deviation and adjust the voltage of the delay unit to compensate for the delay change caused by temperature.

[0043] In the description of this specification, the description with reference to the terms "one embodiment", "example", "specific example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0044] The preferred embodiments of the present invention disclosed above are only used to help explain the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to only specific implementation methods. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for implementing a high-precision time-to-digital converter, characterized in that: It includes a Start signal channel, multiple Stop signal channels and a delay chain, each delay chain corresponds to a channel, the delay chain is formed by cascading a circuit with a delay function as a delay unit, and the chain structure is divided into a full chain and a differential chain. In addition, it also includes a differential structure. The implementation method of the high-precision time digital converter includes the following steps: S1: For the whole chain mode, the decoder inputs the sampling result of each level of the trigger chain into the decoding unit, and the data flips between "0" and "1" to obtain the "fine count" result; S2: For the differential chain mode, the same signal is input into two delay chains respectively, and then the sampling result is input into the decoding unit; S3: In the above S2, the difference between the detailed counting results of the two delay chains is also 1 / 2 of the delay time of the single-stage delay unit, which means that the resolution is doubled, thereby achieving double precision in a physical way; S4: For the differential structure, an algorithm is used to divide the sampling results of the trigger chain into two groups of odd and even levels, and decode them separately to obtain two groups of "fine counting" results; S5: back-label the result to the whole chain, perform threshold expansion according to ±1, and obtain two groups of intervals with a length of 3. Take the intersection of the two intervals. If the intersection result is still an interval, take its average value. S6: In the above S5, when the fine count is a decimal, it means that the jump is now accurately between two adjacent delay units, and the resolution is half of the delay time of a single-stage delay unit, thereby achieving double precision in an algorithmic manner; S7: By combining algorithmic differentiation with physical differentiation, hierarchical decoding is performed based on the differential chain structure to achieve the highest precision measurement.

2. The method for implementing a high-precision time-to-digital converter according to claim 1, characterized in that: The whole chain, that is, one channel corresponds to an independent delay chain, and the differential chain regards the two delay chains corresponding to two adjacent channels as a group. Through the back-end constraint physical layout and wiring rules, the time difference between the signals reaching the input ends of the two delay chains is maintained at 1 / 2 the delay length of the single-stage delay unit to form a differential.

3. The method for implementing a high-precision time-to-digital converter according to claim 1, characterized in that: Also included is a calibration mode, the implementation of which includes the following steps: Step 1: After dividing the system clock, input it into the delay chain in the calibration unit for propagation, and send the output of the last-stage delay unit and the input signal of the first-stage delay unit out of the chip; Step 2: Use a phase detector to sample the signal, use the input signal as a reference signal, and determine the phase difference between the output signal and the input signal; Step 3: Calculate the range that needs to be compensated based on the phase difference, convert it into a voltage signal through DAC, filter, amplify, and shape it, and feed the voltage back to the delay unit; Step 4: The temperature is dynamically compensated by changing the supply voltage of the delay unit to complete the calibration.

4. The method for implementing a high-precision time-to-digital converter according to claim 3, characterized in that: In the step 1, the difference between the two signals is the total delay length of a delay chain, that is, one clock cycle.

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