Integrated circuit device

Abstract

An integrated circuit device (10) is provided. The integrated circuit device (10) comprises a clock distribution network (30) comprising a clock grid (32) formed by a first set of parallel clock lines (34) and a second set of parallel clock lines (36), where the first set of clock lines (34) and the second set of clock lines (36) are arranged at a same level (BSM2) in a backside interconnect structure (20) of the integrated circuit device (10), and are interconnected by crossing each other.

Description

Technical Field

[0001] The present disclosure generally relates to integrated circuit devices including a clock distribution network. Background Art

[0002] Clock distribution networks are a critical part of existing digital integrated circuit devices, such as synchronous digital systems on a chip (SOCs). The networks cover a large chip area, which means that they consume a lot of power (e.g., about 30% of SOC power consumption is due to clock distribution). Clock distribution is also important for performance. Due to factors such as buffer delays and variability in parasitic capacitance, clock signals may accumulate skew as they propagate across the chip. Clock skew is the difference in arrival time of clock edges between different parts of the IC. Therefore, one challenge facing integrated circuit designers is to minimize or mitigate clock skew so that each active device is kept in the same pace, for example to avoid delays that could cause IC failure.

[0003] In high-performance circuit designs, clock grids can be used instead of clock trees to reduce clock skew. However, conventionally designed clock grids tend to consume more power than clock trees. In addition, conventional clock grids take up valuable space in the front BEOL interconnect structure, which is used to interconnect the active devices of the IC (e.g., configured to define logic gates, flip-flops, or registers) and route signals (e.g., logic input and output signals) between them. In addition, conventional clock grids may increase competition for routing resources in the front BEOL interconnect structure, which are also needed to route non-clock signals (e.g., logic input and output signals) between the active devices of the IC (e.g., configured to define logic gates, flip-flops, or registers). Therefore, there is room for improvement in clock distribution in ICs. Summary of the invention

[0004] It is an object of the present invention to provide an IC device which solves or at least mitigates at least some of the above-mentioned disadvantages of conventional clock grid implementations.

[0005] It is therefore an object of the present invention to provide an IC device comprising a clock distribution network in the form of a clock grid, enabling low clock skew and reduced power consumption.

[0006] Another object is to provide an IC device comprising a clock grid implemented such that contention for routing resources in the front BEOL can be reduced.

[0007] Yet another object is to provide an IC device comprising a clock grid implemented to enable rational and cost-effective manufacturing.

[0008] These and other objects are achieved by an IC device according to the independent claims. Embodiments of the invention are defined in the dependent claims.

[0009] Therefore, according to one aspect of the present invention, there is provided an integrated circuit device, comprising:

[0010] A clock distribution network includes a clock grid formed by a first set of parallel clock lines and a second set of parallel clock lines, wherein the first and second sets of clock lines are arranged at the same level in a backside interconnect structure of an integrated circuit device and are interconnected by crossing each other.

[0011] Therefore, the present invention is based on the following recognition: providing a clock grid in the backside interconnect structure can reduce the competition for routing resources in the frontside BEOL interconnect structure (for the sake of brevity, the term BEOL may be omitted hereinafter), so that more resources are available for routing non-clock signals in the frontside interconnect structure.

[0012] Furthermore, by moving the clock grid to the backside interconnect structure, the risk of the clock signal propagating in the clock grid introducing noise into the non-clock logic signals transmitted in the frontside interconnect structure is reduced.

[0013] Furthermore, by moving the clock grid to the backside interconnect structure, the clock grid can be positioned closer to the active device area of ​​the integrated circuit, so that a shorter signal path length can be achieved compared to a conventional clock grid provided in the frontside interconnect structure.

[0014] Furthermore, according to the IC device of the first aspect, the first and second groups of clock lines are arranged at the same level in the backside interconnect structure. Thus, the first and second clock lines are merged or folded into a single common metallization layer of the backside interconnect structure.

[0015] The single layer and cross arrangement of the first and second clock lines eliminates the need for vertical via connections between the first and second sets of clock lines, allowing for shorter signal path lengths. This can help reduce clock skew and make manufacturing more rational and cost-effective. In addition, the cross arrangement of the first and second sets of clock lines can reduce resistance at the intersection by providing an increased contact interface between the lines compared to conventional via connections.

[0016] Here, "same level" means that the first and second groups of clock lines are arranged at the same distance from a nominal reference plane or surface. Therefore, the first and second groups of clock lines are arranged at the same vertical level or height relative to, for example, the front or back side of a substrate of an IC device. This means that in practice, the first and second groups of clock lines extend in the same plane (i.e., a horizontal plane parallel to the substrate), so that the first and second groups of clock lines are naturally interconnected at the location where they intersect.

[0017] According to some embodiments, a first set of clock lines may extend in a first direction and a second set of clock lines may extend in a second direction transverse to the first direction, which is advantageous because interconnection of the clock grid with other portions of the IC device, such as active components, may be facilitated.

[0018] Here, "lateral" means that the first and second directions are orthogonal or substantially orthogonal, such that the first set of clock lines extend orthogonally or substantially orthogonally to the second set of clock lines.

[0019] According to some embodiments, the backside interconnect structure may further include a power distribution network, which is advantageous because contention for routing resources in the frontside interconnect structure may be further reduced.

[0020] According to some embodiments, the power distribution network may include a first group of power rails and a second group of power rails, wherein the clock grid, the first group of power rails and the second group of power rails are arranged at different corresponding levels in the backside interconnect structure. By providing power rails and clock grids at different corresponding levels in the backside interconnect structure, clock distribution and power distribution can be co-located in the backside interconnect architecture while reducing the capacitive coupling between the power rails and the clock lines. The power rails are typically formed as high aspect ratio metal lines. Therefore, if arranged side by side with the clock line, the capacitive coupling with the power rails may significantly increase the capacitance of the clock distribution network. However, by arranging the clock grid and the first and second groups of power rails at different levels, the horizontal interface between the clock line and the power rails can be avoided.

[0021] Herein, the "first set of power rails" refers to a set of power rails that are closer to the substrate of the IC device, which supports the backside interconnect structure. Therefore, the first set of power rails are closer to the substrate supporting the backside interconnect structure than the second set of power rails. Therefore, here, the "second set of power rails" refers to the set of power rails that are farther away from the substrate supporting the backside interconnect structure.

[0022] According to some embodiments, the power rails of the first set of power rails may alternately be VSS and VDD power rails and the power rails of the second set of power rails may alternately be VSS and VDD power rails, which is advantageous because both VSS and VDD power rails are accessible in the first and second directions.

[0023] According to some embodiments, the clock grid may be arranged at a level between the first and second sets of power rails, which is advantageous because the power rails may protect the clock lines from surrounding circuitry, thereby further counteracting interference of noise caused by clock signals propagating in the clock grid with non-clock logic signals transmitted in the front-side interconnect structure.

[0024] According to some embodiments, the clock grid, the first set of power rails and the second set of power rails may be arranged in a coherent metallization layer of the backside interconnect structure, which is advantageous because a compact solution using a limited number of metal layers may be achieved.

[0025] According to some embodiments, a first set of clock lines and a first set of power rails may extend along a first direction, and a second set of clock lines and a second set of power rails may extend along a second direction transverse to the first direction, which is advantageous because clock lines and power rails may be available along two lateral directions.

[0026] According to some embodiments, a first group of power rails may be arranged at a first power rail spacing, and a first group of clock lines may be arranged at a first clock line spacing defined by one or more integer multiples of the first power rail spacing, and wherein a second group of clock lines may be arranged at a second clock line spacing, and a second group of power rails may be arranged at a second power rail spacing defined by one or more integer multiples of the second clock line spacing. Thus, the electrical characteristics of the clock grid and the power distribution network may be consistent throughout the IC device, further maintaining small mutual capacitance coupling.

[0027] According to some embodiments, the first set of power rails can be offset relative to the first set of clock lines along the second direction, and / or the second set of power rails can be offset relative to the second set of clock lines along the first direction, which is advantageous because the intersection points in the clock grid can be located in the gaps between the power rails. This arrangement can facilitate the arrangement of vias, such as clock vias, in the gaps between the power rails.

[0028] According to some embodiments, the offset of the first group of power rails relative to the first group of clock lines may be substantially equal to half of the first power rail spacing, and the offset of the second group of power rails relative to the second group of clock lines may be substantially equal to half of the second clock line spacing. This is advantageous because the power rails of the first group of power rails may be substantially located at the center of the gaps in the clock grid, and the intersection of the clock grid may be substantially located at the center of the gaps between the power rails of the second group of power rails. This arrangement may facilitate the arrangement of vias in the gaps between the first or second power rails, such as clock vias from or to the clock grid. Similarly, this arrangement may facilitate the arrangement of vias in the gaps between the clock lines, such as power vias between the second and first power rails. In addition, the capacitive coupling between the first and second groups of clock lines and the first and second groups of power rails may be further reduced.

[0029] According to some embodiments, the backside interconnect structure may further include at least one power via connected to a power rail of the first group of power rails and a power rail of the second group of power rails and extending through the opening in the clock grid. Thus, active components may be powered without being blocked by the clock grid. In addition, power may be distributed between different levels of the power distribution network without being blocked by the clock grid.

[0030] According to some embodiments, the backside interconnect structure may further include at least one clock via connected to the clock distribution network and extending through an opening in the first set of power rails. Thus, the clock signal may be distributed to active components of the integrated circuit without being blocked by the first set of power rails.

[0031] According to some embodiments, the IC device may further include a substrate supporting an active device region and a front-side interconnect structure disposed over the active device region on a front-side thereof, wherein the back-side interconnect structure is disposed on a back-side of the substrate.

[0032] According to some embodiments, at least one clock via may extend through the substrate and connect to the clock driving circuitry of the active device region. Thus, the clock distribution network of the backside interconnect structure may receive and distribute the clock signal generated by the clock driving circuitry of the active device region on the front side of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] This and other aspects of the present invention will now be described in more detail, with reference to the appended drawings showing embodiments of the invention.

[0034] Figure 1 A cross-sectional view of an integrated circuit device is schematically shown, the integrated circuit device comprising an active device region and a front-side interconnect structure arranged on a front side of a substrate and a back-side interconnect structure arranged on a back side of the substrate.

[0035] Figure 2 Schematically shows Figure 1 An isometric three-dimensional view of a portion of a backside interconnect structure of an integrated circuit device. DETAILED DESCRIPTION

[0036] An example embodiment of an integrated circuit (IC) device including a clock distribution network including a clock grid will be described below with reference to the accompanying drawings. The accompanying drawings are schematic diagrams only, and the relative sizes of certain structures and layers may be exaggerated and not drawn to scale. Instead, the sizes may be adjusted to make the illustration clear and easy to understand. When present in the figure, the indicated axes X, Y and Z refer to the first horizontal or lateral, second horizontal or lateral and vertical directions, respectively. As used herein, the terms "horizontal" and "lateral" refer to the direction parallel to the substrate (main surface) of the integrated circuit device. The term "vertical" refers to the direction parallel to the normal direction of the substrate (main surface) supporting the active area of ​​the integrated circuit device in practice, that is, transverse to the substrate. In addition, the (positive) vertical direction refers to the direction pointing to what is generally regarded as the front side of the substrate. This means that the subsequent layers of the back interconnect structure are arranged one after another in the negative vertical direction, that is, the direction opposite to the vertical direction. In other words, the subsequent layers of the back interconnect structure are arranged one after another on the back side of the substrate, and therefore in the direction opposite to the direction shown by the axis Z.

[0037] Figure 1 An exemplary IC device 10 according to an embodiment is schematically shown. The IC device 10 shown is formed starting from a substrate 12. Thus, the IC device 10 includes the substrate 12. During the formation of the IC device 10, the substrate 12 may have been thinned. Thus, the shown portion of the substrate 12 may correspond to a thickness portion of the initial thickness of the substrate 12 after thinning.

[0038] As shown, substrate 12 may support active device region 14 on its front side 12a. Figure 1 As shown, the active device region 14 may be formed on the front side 12a of the substrate 12. The active device region 14 may include any type of active components, such as transistors, formed on the front side 12a of the substrate 12. The active components may be configured to provide various functions, such as defining logic gates, flip-flops, or registers. The active device region 14 may also be referred to as a front end of line (FEOL portion 14).

[0039] As shown, the front interconnect structure 16 can be arranged vertically above the active device area 14d of the IC device 10. As is known in the art, the front interconnect structure 16 can generally include multiple metallization layers, including conductive lines arranged in a dielectric layer structure of one or more interlayer dielectric materials and vias connecting conductive lines of the metallization layers of the front interconnect structure 6. Therefore, the front interconnect structure 16 can generally be configured to interconnect active components of the active device area 14.

[0040] As shown, the backside interconnect structure 20 can be arranged on the back side 12b of the substrate 12. The backside interconnect structure 20 can generally have a structure corresponding to the front side interconnect structure 16, and therefore includes a plurality of metallization layers, including a conductor arranged in a dielectric layer structure and a through hole of a conductor connecting the metallization layer of the backside interconnect structure 20. The through hole of the backside interconnect structure 20 can also generally extend through the substrate 12, for example, to provide power or clock signals to the active components of the active device area 14. In addition, the active device area 14 can include a clock drive circuit system. The clock drive circuit system can be configured to generate a clock signal. Such a clock signal can be provided to the backside interconnect structure 20 through a through hole extending through the substrate 12, and then provided to the active components of the active device area 14 through a through hole extending through the substrate 12. Examples of interlayer dielectric materials include silicon oxide or other low-k dielectrics commonly used for front and backside interconnect structures. Examples of conductive materials for conductive lines and through holes include aluminum, tungsten, ruthenium or gold, silver and combinations thereof.

[0041] Now also refer to Figure 2 , schematically showing Figure 1 1. In other words, Figure 2 An exemplary design of a backside interconnect structure 20 is shown. Figure 2 The dielectric layer structure with the metallization layer wires embedded therein is omitted to more clearly indicate the design of the metallization layer.

[0042] The depicted backside interconnect structure 20 includes a clock distribution network 30. The clock distribution network 30 includes a clock grid 32. Figure 2 As shown, the clock grid 32 is formed by a first group of parallel clock lines 34 and a second group of parallel clock lines 36. Therefore, each clock line 34 in the first group of parallel clock lines 34 can extend parallel to each other. Correspondingly, each clock line 36 in the second group of parallel clock lines 36 can extend parallel to each other.

[0043] The first set of clock lines 34 and the second set of clock lines 36 may be formed as conductive lines 34 , 36 (eg, any of the example metals described above) disposed in a dielectric layer.

[0044] like Figure 2 As shown, the first group of clock lines 34 and the second group of clock lines 36 of the backside interconnect structure 20 are arranged at the same level in the backside interconnect structure. In addition, the first group of clock lines 34 and the second group of clock lines 36 are interconnected by crossing each other. Therefore, the first group of clock lines 34 and the second group of clock lines 36 can form part of the same metallization layer BSM2 of the backside interconnect structure 20.

[0045] The first group of clock lines 34 and the second group of clock lines 36 can be formed simultaneously (e.g., during BEOL processing of IC device manufacturing). More specifically, the first group of clock lines 34 and the second group of clock lines 36 can be formed simultaneously in a damascene process, in which mutually intersecting grooves are formed in a dielectric layer and then filled with one or more metals. Such mutually intersecting grooves can be formed by photolithography and etching or any other suitable patterning technology. Alternatively, the first group of clock lines 34 and the second group of clock lines 36 can be formed simultaneously by direct metal etching, in which a metal layer is blanket deposited and then etched so that portions forming the first group of clock lines 34 and the second group of clock lines 36 are retained, while other portions of the metal layer are removed by being etched away. Although forming the first and second clock lines 34, 36 simultaneously may contribute to an efficient manufacturing process, an interleaved process is also possible. For example, in a damascene process, the first clock line 34 can be formed first, and the second clock line 36 can be formed subsequently, or vice versa.

[0046] like Figure 2 As shown, the first set of clock lines 34 may extend along the first lateral direction Y. Figure 2 As shown in , the first set of clock lines 34 can extend along axis Y. Figure 2 As shown, the second group of clock lines 36 may extend along a second lateral direction X. The second lateral direction X of the second group of clock lines 34 may be transverse to the first lateral direction Y of the first group of clock lines 33. In other words, the first group of clock lines 34 and the second group of clock lines 36 may extend substantially perpendicular to each other in a plane parallel to the back side 12 b of the substrate 12.

[0047] The back side 12b of the substrate 12 is Figure 2 denoted by shaded rectangles to illustrate the position of the substrate 12 relative to the components of the backside interconnect structure 20. In this regard, it is worth noting that Figure 2 The Z axis points downward, and Figure 1 The middle Z axis points upward.

[0048] As shown, the depicted backside interconnect structure 20 may also include a power distribution network 40. The power distribution network 40 may generally be configured to provide power to the active device region 14 of the IC device 10. The power distribution network 40 may be formed as a conductive line (e.g., any of the above-described example metals) disposed in a dielectric layer. The power distribution network 40 may be formed in a damascene process or direct metal etching, like the first set of clock lines 34 and the second set of clock lines 36.

[0049] As shown in the figure, Figure 2The power distribution network 40 may include a first set of power rails 44 and a second set of power rails 46. The first set of power rails 44, the second set of power rails 46 and the clock grid 30 are arranged at different corresponding levels in the backside interconnect structure 20. This means that the clock grid 30, the first set of power rails 44 and the second set of power rails 46 may form part of different corresponding metallization layers BSM2, BSM1, BSM3 of the backside interconnect structure 20.

[0050] More specifically, the first group of power rails 44 may be closer to the substrate 12 of the IC device 10 than the clock grid 30 and the second group of power rails 46. The clock grid 32 may be arranged at a level between the first group of power rails 44 and the second group of power rails 46. In other words, the second group of power rails 46 may be arranged at a position farther away from the substrate 12 than the clock grid 32 and the first group of power rails 44. Specifically, the first group of power rails 44, the clock grid 32, and the second group of power rails 46 may be arranged in consecutive metallization layers BSM1, BSM2, and BSM3 of the backside interconnect structure 20 as shown.

[0051] like Figure 2 As shown, the first set of power rails 44 may extend along a first lateral direction Y. Thus, as shown in FIG. Figure 2 As shown in , the first set of power rails 44 may extend along axis Y. Figure 2 As shown, the second set of power rails 46 may extend along the second lateral direction X. In other words, the first set of power rails 44 and the second set of power rails 46 of the illustrated backside interconnect structure 20 may extend substantially perpendicular to each other in a plane parallel to the backside 12 b of the substrate 12 .

[0052] Therefore, in Figure 2 In the backside interconnect structure 20, the first group of clock lines 34 and the first group of power rails 44 may extend along a first direction Y, and the second group of clock lines 36 and the second group of power rails 46 may extend along a second direction X transverse to the first direction Y. Figure 2 As shown, the first group of power rails 44 may alternately be VSS and VDD power rails 44S, 44D. Figure 2 As shown, each power rail of the second group of power rails 46 can be alternately VSS and VDD power rails 46S, 46D. Herein, the terms VSS and VDD power rails refer to power rails configured to provide a lower supply voltage (e.g., a reference voltage) and a higher supply voltage, respectively. The lower supply voltage can correspond to a ground voltage (GND), for example.

[0053] like Figure 2As shown, the first group of clock lines 34 can be arranged at a first clock line spacing PC1. In other words, among all the first group of clock lines 34, the center-to-center distance of consecutive clock lines 34 in the first group of clock lines 34 can be the same distance PC1. Correspondingly, the second group of clock lines 36 can be arranged at a second clock line spacing PC2. In other words, among all the second group of clock lines 36, the center-to-center distance of consecutive clock lines 36 in the second group of clock lines 36 can be the same distance PC2. The first clock line spacing PC1 can be equal to the second clock line spacing PC2. The first clock line spacing PC1 can be smaller than the second clock line spacing PC2. The first clock line spacing PC1 can be larger than the second clock line spacing PC2.

[0054] like Figure 2 As shown, the first group of power rails 44 can be arranged at a first power rail pitch PP1. In other words, among all the first group of power rails 44, the center-to-center distance of consecutive power rails 44 in the first group of power rails 44 can be the same distance PP1. Correspondingly, the second group of power rails can be arranged at a second power rail pitch PP2. In other words, among all the second group of power rails 46, the center-to-center distance of consecutive power rails 46 in the second group of power rails 46 can be the same distance PP2. The first power rail pitch PP1 can be equal to the second power rail pitch PP2. The first power rail pitch PP1 can be less than the second power rail pitch PP2. The first power rail pitch PP1 can be greater than the second power rail pitch PP2.

[0055] In addition, the first clock line spacing PC1 can be defined by one or more integer multiples of the first power rail spacing PP1. Therefore, when the first group of power rails 44 are arranged with the first power rail spacing PP1, the first group of clock lines 34 can be arranged at a first clock line spacing PC1 equal to the first power rail spacing PP1, or arranged at a first clock line spacing PC1 corresponding to an integer multiple of the first power rail close to PP1. In other words, the first clock line spacing PC1 can be 1, 2, 3, 4, ... N times the first power rail spacing PP1.

[0056] In addition, the second clock line spacing PC2 can be defined by one or more integer multiples of the second power rail spacing PP2. Therefore, when the second group of clock lines 36 are arranged at the second clock line spacing PC2, the second group of power rails 46 can be arranged at a second power rail spacing PP2 equal to the second clock line spacing PC2, or arranged at a second power rail spacing PP2 corresponding to an integer multiple of the second clock line spacing PC2. In other words, the second power rail spacing PP2 can be 1, 2, 3, 4, ... N times the second clock line spacing PC2.

[0057] like Figure 2As shown, the first group of power rails 44 can be offset relative to the first group of clock lines 34 along the second direction X. Accordingly, the second group of power rails 46 can be offset relative to the second group of clock lines 36 along the first direction Y. More specifically, the offset of the first group of power rails 44 relative to the first group of clock lines 34 can be substantially equal to half of the first power rail pitch PP1. Accordingly, the offset of the second group of power rails 46 relative to the second group of clock lines 36 can be substantially equal to half of the second clock line pitch PC2.

[0058] By offsetting the first group of power rails 44 in the second direction X relative to the first group of clock lines 34, clock vias 50 may be provided from the clock grid 32 to the back side 12b of the substrate 12. Thus, such clock vias 50 may provide the clock signal from the clock grid 32 to the active device region 14 of the IC device 10 by extending through the substrate 12. Alternatively, the clock vias 50 may be connected to the clock driving circuitry of the active device region 14 by the clock vias 50 extending through the substrate 12. In this way, the clock signal generated by the clock driving circuitry of the active device region 14 may be provided to the clock grid 32 of the back side interconnect structure 20. Thus, the clock signal generated by the clock driving circuitry of the active device region 14 may be provided to the clock grid 32 of the back side interconnect structure 20 by means of the first clock vias 50, and then provided to one or more active components provided to the active device region 10 through the second clock vias 50. In the embodiment of FIG. Figure 2 In the figure, a clock via 50 is generally indicated by a hatched line 50, and the clock via 50 extends from an interconnection point between a clock line 34 of the first set of parallel clock lines 34 and a clock line 36 of the second set of parallel clock lines 36 to the back side 12b of the substrate 12. Figure 2 As shown, the clock via 50 extends through the center of the opening formed between two adjacent power rails 44 of the first group of power rails 44 because Figure 2 The offset of the first group of power rails 44 relative to the first group of clock lines 34 is substantially equal to half of the first power rail pitch PP1.

[0059] Furthermore, by additionally offsetting the second group of power rails 46 in the first direction Y relative to the second group of clock lines 36, power vias 60 may be provided from the first group of power rails 44 to the second group of power rails 46. Figure 2 As shown, such power vias 60 can interconnect the VSS power rail 44S of the first group of power rails 44 with the VSS power rail 46S of the second group of power rails 46. Similarly, such power vias 60 can interconnect the VDD power rail 44D of the first group of power rails 44 with the VDD power rail 46D of the second group of power rails 46. Figure 2 In this way, power can be distributed between the first group of power rails 44 and the second group of power rails 46. Figure 2In FIG. 4 , a power via 60 is generally indicated by hatching 60, and the power via 60 extends from a power rail 44 of the first group of power rails 44 to a power rail 46 of the second group of power rails 46. Figure 2 As shown, due to Figure 2 The offset of the second group of power rails 46 relative to the second group of clock lines 36 is substantially equal to half of the second power rail pitch PP2, so the power via 60 substantially extends through the center of the opening formed between two adjacent clock lines 34 of the first group of clock lines 34 and two adjacent clock lines 36 of the second group of clock lines 36.

[0060] Those skilled in the art realize that the present invention is by no means limited to the above-described embodiments. On the contrary, many modifications and variations are possible within the scope of the appended claims. For example, in addition to Figure 2 In addition to the metallization layers BSM1, BSM2, and BSM3 shown in FIG. 1 , the backside interconnect structure 20 may further include other metallization layers. Figure 2 The metallization layers BSM1-BSM3 shown in FIG. 1 may represent a subset of the metallization layers of the backside interconnect structure 20. Figure 2 The line spacing of different metallization layers BSM1-BSM3 is uniform, but the line spacing may become larger when moving away from the back side of the substrate.

Claims

1. An integrated circuit device (10), comprising: A clock distribution network (30) includes a clock grid (32) formed by a first group of parallel clock lines (34) and a second group of parallel clock lines (36), wherein the first group of clock lines (34) and the second group of clock lines (36) are arranged at the same level (BSM2) in a backside interconnect structure (20) of the integrated circuit device (10) and are interconnected by crossing each other.

2. The integrated circuit device (10) according to claim 1, characterized in that The first set of clock lines (34) extends along a first direction (Y), and the second set of clock lines (36) extends along a second direction (X) transverse to the first direction (Y).

3. An integrated circuit device (10) according to any one of the preceding claims, characterized in that The backside interconnect structure (20) also includes a power distribution network (40).

4. The integrated circuit device (10) according to claim 3, characterized in that The power distribution network (40) includes a first set of power rails (44) and a second set of power rails (46), wherein the clock grid (30), the first set of power rails (44) and the second set of power rails (46) are arranged at different corresponding levels (BSM2, BSM1, BSM3) in the backside interconnect structure (20).

5. The integrated circuit device (10) according to claim 4, characterized in that The power rails in the first set of power rails (44) are alternating VSS and VDD power rails (44S, 44D), and wherein the power rails in the second set of power rails (46) are alternating VSS and VDD power rails (46S, 46D).

6. The integrated circuit device (10) according to any one of claims 4 to 5, characterized in that: The clock grid (32) is arranged at a level (BSM2) between the first set of power rails (44) and the second set of power rails (46).

7. The integrated circuit device (10) according to claim 6, characterized in that The clock grid (32), the first set of power rails (44), and the second set of power rails (46) are arranged in a consecutive metallization layer (BSM2, BSM1, BSM3) of the backside interconnect structure (20).

8. The integrated circuit device (10) according to any one of claims 4 to 7, characterized in that: The first set of clock lines (34) and the first set of power rails (44) extend along a first direction (Y), and the second set of clock lines (36) and the second set of power rails (46) extend along a second direction (X) transverse to the first direction (Y).

9. The integrated circuit device (10) according to claim 8, characterized in that The first group of power rails (44) are arranged at a first power rail pitch (PP1), and the first group of clock lines (34) are arranged at a first clock line pitch (PC1) defined by one or more integer multiples of the first power rail pitch (PP1), and wherein the second group of clock lines (36) are arranged at a second clock line pitch (PC2), and the second group of power rails (46) are arranged at a second power rail pitch (PP2) defined by one or more integer multiples of the second clock line pitch (PC2).

10. The integrated circuit device (10) according to any one of claims 8 to 9, characterized in that: The first set of power rails (44) is offset relative to the first set of clock lines (34) along the second direction (X), and / or wherein the second set of power rails (46) is offset relative to the second set of clock lines (36) along the first direction (Y).

11. An integrated circuit device (10) according to claim 10, when dependent on claim 9, characterized in that The first group of power rails (44) is offset relative to the first group of clock lines (34) by substantially half of the first power rail spacing (PP1), and wherein the second group of power rails (46) is offset relative to the second group of clock lines (36) by substantially half of the second clock line spacing (PC2).

12. The integrated circuit device (10) according to any one of claims 10-11, characterized in that: The backside interconnect structure (20) also includes at least one power via (60) connected to a power rail (44) of the first set of power rails (44) and a power rail (46) of the second set of power rails (46) and extending through an opening in the clock grid (32).

13. The integrated circuit device (10) according to any one of claims 10 to 12, characterized in that: The backside interconnect structure (20) also includes at least one clock via (50) connected to the clock distribution network (20) and extending through an opening in the first set of power rails (44).

14. The integrated circuit device (10) according to any one of the preceding claims, characterized in that The integrated circuit device (10) also includes a substrate (12) supporting an active device region (14) on its front side (12a) and a front side interconnect structure (16) arranged above the active device region (14), wherein the back side interconnect structure (20) is arranged on a back side (12b) of the substrate (12).

15. The integrated circuit device (10) according to claim 13 and 14, characterized in that The at least one clock via (50) extends through the substrate (12) and is connected to clock driver circuitry of the active device region (14).

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