Error processing method, related equipment and storage medium

Abstract

The invention provides an error processing method, related equipment and a storage medium, and is applied to the technical field of computers, the method is applied to a system on chip, the system on chip comprises a network on chip, and a processor, an error reporting unit, a bus monitoring module and at least one functional unit which are connected with the network on chip, the error reporting unit triggers a first interrupt signal according to error information provided by the abnormal function unit with the to-be-processed error, and the bus monitoring module responds to the first interrupt signal, obtains a target error identifier of the to-be-processed error and sends the to-be-processed error to the abnormal function unit based on a preset mapping relation between the error identifier and a preset instruction sequence. According to the method, the target instruction sequence corresponding to the target error identifier is determined, the bus monitoring module sends the target instruction sequence to the abnormal function unit, the to-be-processed error is processed through the target instruction sequence, the whole error processing process does not need participation of a processor, processor resources can be effectively released, and the running performance of the processor and the whole system-on-chip is improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to an error handling method, related equipment and storage medium. Background Art

[0002] The System on Chip (SoC) provides many error handling mechanisms, through which errors that occur during system operation can be discovered and handled in a timely manner, thereby ensuring the reliability of system operation.

[0003] Taking a SoC configured with a RAS (Reliability Availability Serviceability) mechanism as an example, the SoC includes a processor, a RAS unit, and at least one functional unit for implementing preset functions. When an error occurs in any functional unit in the SoC, the functional unit first sends the error information to the RAS unit. The RAS unit sends an interrupt signal to the processor in response to the error information. After receiving the interrupt signal, the processor obtains an instruction sequence pre-stored in the memory for processing the error, and sends the obtained instruction sequence to the functional unit where the error occurs, thereby resolving or eliminating the error in the functional unit.

[0004] The inventors have found that the existing error handling mechanism can effectively handle errors when the number of errors is small. However, once the number of errors in the system explodes, the processor will be stuck in a long processing flow, which will seriously occupy the processor's resources and affect the processor's processing of other tasks, thereby reducing the performance of the processor and the entire on-chip system. Summary of the invention

[0005] In view of this, the present application is committed to providing an error handling method, related equipment and storage medium, which handles errors through a bus monitoring module, releases processor resources, and ensures that the error handling process does not affect the operating performance of the processor and the entire on-chip system.

[0006] In a first aspect, the present application provides an error handling method, which is applied to a system on chip, wherein the system on chip includes a network on chip and a processor, an error reporting unit, a bus monitoring module and at least one functional unit respectively connected to the network on chip, and the method includes the following steps performed by the bus monitoring module:

[0007] In response to a first interrupt signal, obtaining a target error identifier of an error to be processed, wherein the first interrupt signal is triggered by the error reporting unit according to error information provided by an abnormal function unit where the error to be processed occurs;

[0008] Determine a target instruction sequence corresponding to the target error identifier based on a preset mapping relationship between the error identifier and the preset instruction sequence, wherein each set of the preset instruction sequences is used to process an error;

[0009] The target instruction sequence is sent to the abnormal function unit through the on-chip network to process the pending error.

[0010] In an optional implementation, the determining the target instruction sequence corresponding to the target error identifier based on a preset mapping relationship between the error identifier and the preset instruction sequence includes:

[0011] Determining whether the target error identifier is valid;

[0012] If the target error identifier is valid, a target instruction sequence corresponding to the target error identifier is determined based on a preset mapping relationship between the error identifier and the preset instruction sequence.

[0013] In an optional implementation manner, obtaining a target error identifier of an error to be processed includes:

[0014] Sending an identification query request to the error reporting unit;

[0015] Obtain a target error identifier corresponding to the error to be processed that is fed back by the error reporting unit in response to the identifier query request.

[0016] In an optional implementation, the process of creating the preset mapping relationship includes:

[0017] Acquire an error identifier, where the error identifier is created by the processor after injecting a preset error into a target functional unit, where the target functional unit includes any one of the at least one functional unit;

[0018] In response to an enable signal of the processor, recording a preset instruction sequence sent by the processor to the target functional unit, wherein the preset instruction sequence is used to process the preset error;

[0019] A corresponding relationship between the error identifier and the preset instruction sequence is established to obtain the preset mapping relationship.

[0020] In an optional implementation, recording a preset instruction sequence sent by the processor to the target functional unit includes:

[0021] Determining whether the error identifier is valid;

[0022] If the error flag is valid, recording a preset instruction sequence sent by the processor to the target functional unit;

[0023] If the error identifier is invalid, first notification information indicating that the error identifier is invalid is sent.

[0024] In an optional implementation, recording a preset instruction sequence sent by the processor to the target functional unit includes:

[0025] In response to an enable signal, acquiring a bus signal sent by the processor to the target functional unit through the on-chip network;

[0026] Analyzing the bus signal to obtain a preset instruction sequence;

[0027] In response to the disable signal, the receiving of the bus signal is stopped.

[0028] In an optional implementation, before acquiring the bus signal sent by the processor to the target functional unit through the on-chip network, the method further includes:

[0029] Second notification information indicating that a recording function is successfully enabled is sent to the processor, where the second notification information is used to trigger a bus signal sent by the processor to the target functional unit through the on-chip network.

[0030] In a second aspect, the present application provides an error handling method, which is applied to a system on chip, wherein the system on chip includes a network on chip, processors respectively connected to the network on chip, an error reporting unit, a bus monitoring module, and at least one functional unit, and the method includes the following steps performed by the processor:

[0031] Injecting a preset error into a target functional unit, wherein the target functional unit includes any one of the at least one functional unit;

[0032] In response to a second interrupt signal, creating an error flag, wherein the second interrupt signal is triggered by the error reporting unit according to error information fed back by the target functional unit in response to the preset error;

[0033] An enable signal is sent, and a preset instruction sequence is sent to the target functional unit, wherein the preset instruction sequence is used to process the preset error, and the enable signal is used to trigger the bus monitoring module to record the preset instruction sequence and establish a preset mapping relationship between the error identifier and the preset instruction sequence.

[0034] In an optional implementation manner, the error handling method provided in the second aspect of the present application further includes:

[0035] Acquire first notification information, where the first notification information is used to indicate that the error identifier is invalid;

[0036] In response to the first notification information, the error flag is updated.

[0037] In an optional implementation, sending a preset instruction sequence to the target functional unit includes:

[0038] Acquire second notification information, where the second notification information is sent by the bus monitoring module after the recording function is successfully turned on;

[0039] In response to the second notification information, a preset instruction sequence is sent to the target functional unit.

[0040] In an optional implementation manner, the error handling method provided in the second aspect of the present application further includes:

[0041] The error identifier is sent to the error reporting unit, so that the error reporting unit establishes a corresponding relationship between the preset error and the error identifier.

[0042] In a third aspect, the present application provides a bus monitoring module, which is configured to execute the error handling method as described in any one of the first aspects of the present application.

[0043] In a fourth aspect, the present application provides a processor configured to execute the error handling method as described in any one of the second aspect of the present application.

[0044] In a fifth aspect, the present application provides a system on chip, comprising: an on-chip network, an error reporting unit, at least one functional unit, the bus monitoring module as described in the third aspect of the present application, and the processor as described in the fourth aspect of the present application, wherein:

[0045] The error reporting unit, each of the functional units, the bus monitoring module and the processor are respectively connected to the on-chip network.

[0046] In a sixth aspect, the present application provides an electronic device, comprising: a system on a chip as described in the fifth aspect of the present application.

[0047] In a seventh aspect, the present application provides a computer-readable storage medium storing a computer program, which, when executed, implements the error handling method as described in the first aspect or any one of the second aspects of the present application.

[0048] Based on the above content, the error handling method provided by the present application is applied to an on-chip system, which includes an on-chip network, a processor connected to the on-chip network, an error reporting unit, a bus monitoring module and at least one functional unit. The error reporting unit triggers a first interrupt signal according to error information provided by an abnormal functional unit where an error to be processed occurs. The bus monitoring module responds to the first interrupt signal, obtains a target error identifier of the error to be processed, and determines a target instruction sequence corresponding to the target error identifier based on a preset mapping relationship between the error identifier and a preset instruction sequence. The bus monitoring module uses the on-chip network to send the target instruction sequence to the abnormal functional unit, thereby processing the error to be processed through the target instruction sequence. It can be seen that in the error handling method provided by the present application, the error handling of the abnormal functional unit is completed by the bus monitoring module, and the entire error handling process does not require the participation of the processor. Compared with the prior art, it can effectively release the processor's resources for processing errors, ensuring that the error handling process does not affect the operating performance of the processor and the entire on-chip system. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0050] Figure 1 It is a schematic diagram of the structure of a system on a chip provided by this application.

[0051] Figure 2 It is a flow chart of an error handling method provided by this application.

[0052] Figure 3 This is a structural block diagram of a bus monitoring module provided by this application.

[0053] Figure 4 It is a flowchart of another error handling method provided by the present application. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0055] As mentioned above, the error handling mechanism configured in the system on chip in the prior art can effectively handle errors when the number of errors is small, which has a positive impact on maintaining the stable operation of the system on chip. However, once the number of errors in the system explodes, the processor will fall into a long processing flow, seriously occupying the processor's resources, affecting the processor's processing of other tasks, thereby reducing the performance of the processor and the entire system on chip. Moreover, in the process of handling simple errors identified by error handling mechanisms such as RAS, the processor may further cause more serious fatal errors, and even cause the system on chip to crash, seriously reducing the reliability and stability of the system on chip.

[0056] To solve the above problems, the present application provides a system on chip, combining Figure 1 As shown, the system on chip provided by the present application includes: a processor 101, an error reporting unit 102, a bus monitoring module 103, an on-chip network 104 and at least one functional unit, wherein each functional unit is used to implement a preset function of the system on chip. Figure 1 In the illustrated embodiment, the peripheral controller 105 and the multimedia controller 106 are shown. Of course, in actual applications, functional units for implementing other preset functions may also be configured inside the system on chip, which are not listed one by one here.

[0057] The processor 101, the error reporting unit 102, the bus monitoring module 103 and each functional unit are respectively connected to the on-chip network 104, and information is exchanged between them through the on-chip network 104. Furthermore, the on-chip network 104 is also connected to the memory 200, and the processor 101 can access the memory 200 through the on-chip network 104.

[0058] For the error reporting unit 102, an interrupt signal can be triggered based on the error information fed back by any functional unit, and then the error handling mechanism is triggered by the interrupt signal. In the case where the system on chip is configured with a RAS mechanism, the error reporting unit 102 can be a hardware module that supports the RAS mechanism, that is, an interrupt signal is triggered according to the RAS error information fed back by the functional unit.

[0059] The bus monitoring module 103 is used to execute the error handling method provided by the present application, handle the error of any functional unit, and the entire error handling process does not require the participation of the processor. Compared with the prior art, it can effectively release the processor's resources for handling errors, ensuring that the error handling process does not affect the operating performance of the processor and the entire on-chip system. As for the optional implementation of the bus monitoring module 103, it will be expanded in the subsequent content and will not be described in detail here.

[0060] Based on the above, see Figure 2 The error handling method provided in this application may include the following steps.

[0061] S100: In response to a first interrupt signal, obtain a target error identifier of an error to be processed.

[0062] In the related art, each functional unit in the system on chip has the function of detecting its own operating status. Taking the RAS mechanism as an example, each functional unit in the system on chip is configured with error detection logic (which can be a hardware circuit or a software program). During the operation of the functional unit, the error detection logic in the functional unit detects whether an error occurs in the functional unit according to the operation status of the functional unit. Once the error detection logic of a functional unit identifies that an error occurs in the functional unit, it will report the error information to the error reporting unit. For the convenience of description, in this embodiment and subsequent embodiments, the functional unit in which an error occurs in each functional unit in the system on chip is defined as an abnormal functional unit.

[0063] After obtaining the error information reported by the abnormal functional unit, the error reporting unit triggers a first interrupt signal according to the obtained error information, and sends the first interrupt signal to the bus monitoring module through the on-chip network. The first interrupt signal can not only be used to carry the corresponding error information, but also to trigger the bus monitoring module to execute subsequent error handling processes.

[0064] Based on the above content, after obtaining the first interrupt signal, the bus monitoring module first obtains the target error identifier corresponding to the obtained first interrupt signal. In the present application, a unique error identifier is assigned to each error that may occur in the on-chip system, that is, there is a one-to-one correspondence between the error identifier and the error. In practical applications, the error identifier can be implemented in a variety of ways, for example, it can be an error number or an error name. Any information that can uniquely characterize the corresponding error can be used as the error identifier described in the present application, and it also belongs to the scope of protection of the present application without exceeding the core idea of ​​the present application.

[0065] In an optional embodiment, there may be multiple first interrupt signals reported by the error reporting unit, and each first interrupt signal corresponds to a different error. Therefore, after receiving any first interrupt signal, the bus monitoring module needs to accurately identify the error corresponding to the first interrupt signal. Each first interrupt signal corresponds to a unique interrupt signal identifier, for example, it can be the number of the interrupt signal. Furthermore, the bus monitoring module pre-stores the correspondence between the interrupt signal identifier and the error identifier. Based on this, the bus monitoring module can determine the error identifier corresponding to the interrupt signal identifier of the first interrupt signal according to the correspondence between the interrupt signal identifier and the error identifier, that is, the target error identifier.

[0066] In another optional implementation, the error identifiers of various types of errors are managed by an error reporting unit. As described above, the error reporting unit triggers the first interrupt signal according to the error information reported by the abnormal function unit, so the error reporting unit knows the corresponding relationship between the first interrupt signal and the error information. Based on this, the bus monitoring module responds to the first interrupt signal and sends an identification query request to the error reporting unit. As an optional implementation, the identification query request can carry the interrupt signal identifier of the first interrupt signal. The error reporting unit extracts the interrupt signal identifier in the identification query request, determines the error information corresponding to the obtained interrupt signal identifier, and then determines the target error identifier corresponding to the error information, and finally feeds back the target error identifier to the bus monitoring module.

[0067] In another optional embodiment, the first interrupt signal carries critical error information of the error that triggers the first interrupt signal. The bus monitoring module extracts the critical error information in the first interrupt signal and feeds back the critical error information to the error reporting unit through an identification query request. The error reporting unit responds to the identification query request and feeds back an error identification corresponding to the obtained critical error information, i.e., a target error identification, to the bus monitoring module.

[0068] S110. Determine a target instruction sequence corresponding to a target error identifier based on a preset mapping relationship between the error identifier and the preset instruction sequence.

[0069] The present application provides a preset mapping relationship, in which the corresponding relationship between error identifiers and preset instruction sequences is recorded, wherein each set of preset instruction sequences recorded in the preset mapping relationship can be used to handle an error. Of course, the errors that can be handled by each preset instruction sequence are different. In actual applications, any preset instruction sequence includes at least one instruction, and the functional unit can handle the corresponding error by executing the preset instruction sequence.

[0070] The preset mapping relationship can be stored in various forms, such as arrays, linked lists, tables, etc. In hardware implementation, it can also be stored in register groups. This application does not limit the specific storage method of the preset mapping relationship. As for the specific construction method of the preset mapping relationship, it will be detailed in the subsequent content and will not be described in detail here.

[0071] It can be understood that the preset mapping relationship is created in advance. Therefore, in actual applications, it is possible that a certain error identifier is not recorded in the preset mapping relationship. Based on this, in an optional implementation, after obtaining the target error identifier, the bus monitoring module can use a traversal method to determine whether the target error identifier is recorded in the preset mapping relationship. If the target error identifier is recorded in the preset mapping relationship, it can be determined that the target error identifier is valid, and the target instruction sequence corresponding to the target error identifier can be further determined based on the preset mapping relationship; on the contrary, if the target error identifier is not recorded in the preset mapping relationship, it can be determined that the target error identifier is invalid.

[0072] S120 . Send a target instruction sequence to the abnormal functional unit through the on-chip network to process the pending error.

[0073] On the basis of storing the aforementioned preset mapping relationship, the bus monitoring module also pre-stores the instruction sequence corresponding to each error identifier. Based on this, after determining the target instruction sequence through the aforementioned steps, the bus monitoring module sends the target instruction sequence to the abnormal function unit through the on-chip network based on the recurrence function. The abnormal function unit can handle the aforementioned pending errors by executing each instruction in the target instruction sequence.

[0074] In summary, in the error handling method provided by the present application, the error handling of the abnormal functional unit is completed by the bus monitoring module, and the entire error handling process does not require the participation of the processor. Compared with the prior art, it can effectively release the processor's resources for handling errors and ensure that the error handling process does not affect the operating performance of the processor and the entire system on chip. Furthermore, since the processor no longer actually handles each error, the probability of causing a fatal error due to handling a simple error can be significantly reduced, which is of great significance for improving the reliability and stability of the operation of the system on chip.

[0075] It is understandable that unexpected errors may occur during the operation of any functional unit. In this case, the preset instruction sequence stored in the bus monitoring module is very likely to be unable to handle all errors. For errors that cannot be handled based on the preset instruction sequence, the processor still needs to handle them according to relevant technologies, which will not be described in detail here. Correspondingly, after the bus monitoring module sends the target instruction sequence to the abnormal functional unit, the processor can further query the progress of the error handling, and then determine whether to further participate in the error handling process based on the processing results.

[0076] In an optional implementation, the bus monitoring module may refer to Figure 3 The embodiment shown is implemented. Figure 3As shown, the bus monitoring module provided in this embodiment includes: a pre-processing unit 10 , a general data processing unit 20 , a dedicated data processing unit 30 , a transmission unit 40 and a data recurrence unit 50 .

[0077] Specifically, the input end of the preprocessing unit 10 is connected to the on-chip network 104 to obtain the bus signal transmitted by the on-chip network 104. The first output end of the preprocessing unit 10 is connected to the general data processing unit 20, and the second output end is connected to the dedicated data processing unit 30. After obtaining the bus signal, the preprocessing unit 10 converts the bus signal into bus data. Furthermore, the preprocessing unit 10 also provides an enable signal when the obtained bus data meets the preset dedicated data screening condition.

[0078] The general data processing unit 20 receives the bus data provided by the preprocessing unit 10, and extracts the target general data in the bus data according to the preset general data screening conditions; the special data processing unit 30 responds to the enable signal provided by the preprocessing unit 10, and obtains the target special data according to the preset special data screening conditions.

[0079] In an optional embodiment, the preset general data filtering conditions can be set based on transaction characteristics, and the transaction characteristics used to set the preset general data filtering conditions can include at least one of the address of the bus request, the identification mark of the bus request, the data content in the bus information, and the response content of the bus request.

[0080] Compared with target general data, target specific data is more targeted and can be the data of a specified functional unit when the on-chip system is running. For example, when it is necessary to analyze the operating status or handle errors of the peripheral controller, the target specific data mainly refers to data related to the operating process of the peripheral controller. Of course, it can also be the preset instruction sequence mentioned in the previous content of this application.

[0081] It can be seen from the foregoing that the target-specific data may come from a specific target functional unit. Since the target functional unit also transmits data through the bus, the obtained bus data may also include the target-specific data. Based on this, in an optional implementation, the dedicated data processing unit 30 can extract the target-specific data from the bus data according to preset dedicated data screening conditions.

[0082] It should be noted that the aforementioned preset instruction sequence can be used as target-specific data storage or as target-general data storage. In practical applications, it can be selected based on actual needs, and this application does not make any specific limitations.

[0083] The dedicated data channel of the transmission unit 40 is connected to the dedicated data processing unit 30, and the general data channel is connected to the general data processing unit 20. The output end of the transmission unit 40 is connected to the on-chip network 104. The transmission unit 40 is used to store the target general data and the target dedicated data to the memory 200, that is, to store the preset instruction sequence to the memory 200.

[0084] It should be noted that in Figure 3 In the illustrated embodiment, the memory 200 is an external memory connected to the bus, and the transmission unit 40 stores the target general data and the target specific data in the external memory through the on-chip network 104. In another optional embodiment, an internal memory may be provided inside the bus monitoring module, in which case the transmission unit 40 may store the target general data and the target specific data directly in the internal memory without passing through the on-chip network 104.

[0085] The input end and the output end of the data regeneration unit 50 are respectively connected to the on-chip network 104. After determining the target instruction sequence according to the error handling method provided in the above embodiment, the data regeneration unit 50 accesses the memory 200 to obtain the target instruction sequence, and further sends the target instruction sequence to the abnormal function unit ( Figure 3 (not shown) recurs the target instruction sequence to handle pending errors in the abnormal functional unit.

[0086] It can be understood that, since the recurrence data comes from the target common data and / or the target specific data, the data recurrence process must occur after the transmission unit 50 stores the target common data and the target specific data in the memory. Therefore, in practical applications, it is necessary to reasonably configure the recurrence enable register in combination with the storage status of the target specific data and the target common data to ensure that the data recurrence unit 50 can successfully extract the recurrence data from the memory.

[0087] Furthermore, the present application provides another error handling method, which is also a method for creating the aforementioned preset mapping relationship, see Figure 4 The error handling method provided in this embodiment includes the following steps.

[0088] S200: The processor injects a preset error into a target functional unit.

[0089] In the related art, errors in the operation of each functional unit of the on-chip system are handled by the processor. As mentioned above, after the error reporting unit sends a first interrupt signal based on the error information fed back by the functional unit, the processor obtains a preset instruction sequence for handling the error in response to the first interrupt signal. That is to say, the processor knows the preset instruction sequence that needs to be called when handling different errors. Based on this, in order to create a preset mapping relationship between the error identifier and the preset instruction sequence, it is necessary to record one by one the preset execution sequence called by the processor when handling each error.

[0090] In order to reproduce the process of the processor calling the preset instruction sequence to handle the error, the present application uses an error injection method to trigger the processor to handle the error of the functional unit. Based on this, any one of the functional units in the system on chip is used as the target functional unit, and a preset error is injected into the target functional unit. After the error detection logic in the target functional unit recognizes the preset error, it will send error information to the error reporting unit, and further, the error reporting unit triggers a second interrupt signal according to the error information.

[0091] In an optional implementation, the system on chip supports the RAS mechanism, in which the error injection process can be implemented based on the EINJ interrupt mechanism. Specifically, the EINJ interrupt mechanism is a typical interrupt mechanism in the APEI (Advanced Platform Error Interfaces) interface. Its main function is to inject errors and trigger errors. In actual use, EINJ can inject various types of hardware errors. These injected errors are not simulated, but are actually generated through cooperation with the underlying firmware and hardware. The errors injected through the EINJ interrupt mechanism are no different from the errors that actually occur in the hardware. In this way, designers can use EINJ interrupts to test whether the platform's software and hardware environment is reliable, whether it has sufficient fault tolerance and completeness, etc. before the software and hardware are released.

[0092] It should be noted that the EINJ interrupt mechanism can be used to inject multiple RAS errors, but only one RAS error can be injected at a time. Therefore, in the process of creating a preset mapping relationship, the error injection process is repeated. After the EINJ interrupt mechanism is triggered, the EINJ interrupt mechanism will automatically traverse all RAS errors, thereby automatically repeating the error injection process. As for the specific implementation process of error injection based on the EINJ interrupt mechanism, please refer to the relevant technology and will not be described in detail here.

[0093] Similar to the above content, after the error is injected based on the EINJ interrupt mechanism, the error detection logic in the target functional unit will detect the injected error and report the corresponding error information to the error reporting unit (under the RAS mechanism, that is, the hardware module that supports RAS error reporting), and the error reporting unit will trigger the second interrupt signal.

[0094] S210: The processor creates an error flag in response to the second interrupt signal.

[0095] After receiving the second interrupt signal, the processor first creates an error identifier, which is defined as an error identifier in this application for ease of description. As mentioned above, there are many options for the specific form of the error identifier, such as an error number or an error name. In short, any information that can uniquely characterize the corresponding error can be used as the error identifier mentioned in this application, and it also falls within the scope of protection of this application without exceeding the core idea of ​​this application.

[0096] After creating the error identifier, the processor further sends the error identifier to the bus listening module. In an optional implementation, the processor may send the error identifier to the bus listening module by writing a register.

[0097] S220: The bus monitoring module obtains an error identifier.

[0098] Combination Figure 1 In the architecture of the system on chip shown, the bus monitoring module obtains the error identification provided by the processor through the on-chip network.

[0099] As mentioned above, if the processor sends an error flag by writing a register, the bus monitoring module can read the corresponding register to obtain the error flag.

[0100] In an optional implementation, after obtaining the error identifier, the bus monitoring module can determine whether the obtained error identifier is valid, that is, determine whether the error identifier already exists. If it already exists, it means that the error identifier is invalid. On the contrary, if the error identifier does not repeat any existing error identifier, it means that the error identifier is valid.

[0101] The purpose of verifying whether the error identifier is valid is, on the one hand, to avoid repeated editing of the error identifier and instruction sequence that have been created, and on the other hand, to avoid the correspondence between the previously recorded error identifier and the preset instruction sequence being overwritten due to the duplication of the error identifier.

[0102] Taking the RAS mechanism as an example, assuming that the bus monitoring module has recorded the correspondence between the error identifier error1 (the error identifier of RAS error 1) and the instruction sequences 1 to n, if the error identifier of RAS error 2 sent by the processor again is still error1 (actually it should be error2), if the bus monitoring module records the correspondence between error1 and the instruction sequence n+1 to m again, the original correspondence between error1 and the instruction sequence 1 to n will be overwritten.

[0103] In an optional embodiment, when it is determined that the error identifier is valid, the bus monitoring module sends a third notification message to the processor to notify the processor that the error identifier is valid. Correspondingly, when it is determined that the error identifier is invalid, the bus monitoring module sends a first notification message to the processor to notify the processor that the error identifier is invalid.

[0104] Further, as an optional implementation, the processor updates the error identifier in response to the first notification information, and again provides the updated error identifier to the bus monitoring module, which then again determines the validity of the error identifier, and repeats this process until a valid error identifier is obtained.

[0105] S230: The processor sends an enable signal and sends a preset instruction sequence to the target functional unit.

[0106] After providing the error identification to the bus monitoring module, the processor sends an enable signal to the bus monitoring module, triggering the bus monitoring module to record the preset instruction sequence transmitted by the on-chip network. Further, the preset instruction sequence capable of processing the injected preset error is sent to the target functional unit. As for the specific process of the processor sending the preset instruction sequence to the target functional unit, it can be realized by referring to the relevant technology and will not be repeated here.

[0107] In a possible implementation, if the bus monitoring module provides the aforementioned third notification information, the processor may perform this step after receiving the third notification information.

[0108] In another optional embodiment, the bus monitoring module is also configured with an enable register, and the processor transmits an enable signal by writing to the enable register. That is, when the processor writes a first value representing the activation of the data acquisition function to the enable register, the bus monitoring module enables the data acquisition and recording functions. Correspondingly, when the processor writes a second value representing the prohibition of the data acquisition function to the enable register, the bus monitoring module will not acquire data transmitted by the on-chip network.

[0109] Furthermore, when the bus monitoring module successfully obtains the aforementioned first value, that is, successfully enables the recording function, it can also send a second notification message to the processor indicating that the recording function is successfully enabled. After receiving the second notification message, the processor sends a preset instruction sequence to the target functional unit, thereby ensuring that the bus monitoring module records the content of the preset execution sequence in a timely manner to avoid information omissions.

[0110] S240. The bus monitoring module records a preset instruction sequence sent by the processor to the target functional unit in response to the enable signal.

[0111] In an optional implementation, if the bus monitoring module does not verify the validity of the error identifier in S220, the above verification process can also be performed in this step. Specifically, the bus monitoring module responds to the obtained enable signal and first determines whether the error identifier is valid. If the error identifier is valid, the preset instruction sequence sent by the processor to the target functional unit is recorded. On the contrary, if the error identifier is invalid, the recording function is disabled and the preset instruction sequence sent by the processor will not be recorded. As for the specific implementation method of determining whether the error identifier is valid, it can be implemented with reference to the relevant content in S220 and will not be repeated here.

[0112] Further, when it is determined that the error identifier is invalid, the bus monitoring module may also send the aforementioned first notification information to the processor to notify the processor that the error identifier is invalid. Similar to the aforementioned content, as an optional implementation, the processor updates the error identifier in response to the first notification information, and again provides the updated error identifier to the bus monitoring module, and the bus monitoring module again determines the validity of the error identifier, and repeats this process until a valid error identifier is obtained.

[0113] Referring to the foregoing content, the processor transmits a preset instruction sequence in the form of a bus signal through the on-chip network, and the bus monitoring module is connected to the on-chip network. Based on this, the bus monitoring module responds to the enable signal and first obtains the bus signal sent by the processor to the target functional unit through the on-chip network. After that, the bus monitoring module parses the bus signal according to the bus protocol corresponding to the corresponding bus in the on-chip network to obtain the corresponding bus data. Further, the bus monitoring module extracts the preset instruction sequence for the processor preset error from the bus data, and stores the obtained preset instruction sequence in a preset memory, such as Figure 3 Of course, in practical applications, the bus monitoring module can also select other storage devices to store the obtained preset instruction sequence, for example, the preset instruction sequence is stored in the internal memory integrated in the bus monitoring module.

[0114] Furthermore, in order to prevent the bus monitoring module from storing other bus data other than the preset instruction sequence and to ensure that the preset instruction sequence will not be affected by other irrelevant instructions or data when processing errors, the processor, after completing the sending of all instructions and related data in the preset instruction sequence, further sends a disable signal to the bus monitoring module, that is, a signal for turning off the recording function of the bus monitoring module. The bus monitoring module responds to the obtained disable signal and stops receiving bus signals in the on-chip network, that is, turns off the recording function.

[0115] In an optional implementation, the process of turning off the recording function of the bus monitoring module can also be achieved by writing a register. For details, please refer to the above-mentioned related content and will not be repeated here.

[0116] Further, as an optional implementation, the bus monitoring module may respond to the aforementioned disabling signal and may also feed back notification information to the processor to indicate whether the recording function is successfully or unsuccessfully turned off. For the processor, in the case where the recording function of the bus monitoring module fails to be turned off, it may try to send the disabling signal repeatedly for multiple times until the recording function of the bus monitoring module is successfully turned off. In the case where the processor enables or disables the recording function of the bus monitoring module by configuring the enable register, the bus monitoring module may query the specific value stored in the enable register to determine whether the recording function is successfully turned off. Following the previous example, the enable register enables the recording function when the first value is written, and turns off the recording function when the second value is written. Based on this, if the bus monitoring module determines that the second value is stored in the enable register by querying the enable register, it may feed back notification information indicating that the recording function is successfully turned off to the processor.

[0117] S250: The bus monitoring module establishes a corresponding relationship between the error identifier and the preset instruction sequence to obtain a preset mapping relationship.

[0118] After the above steps, the bus monitoring module has obtained the error identifier of the preset error and the preset instruction sequence for processing the preset error. Further, the bus monitoring module establishes a corresponding relationship between the error identifier and the preset instruction sequence, that is, obtains the above preset mapping relationship.

[0119] As mentioned above, the preset mapping relationship can be recorded in various forms. Taking the RAS mechanism as an example, the preset mapping relationship provided by this application can be shown in Table 1.

[0120] Table 1

[0121] RAS Error Flag Preset command sequence RAS1 Instruction sequence 1 RAS2 Instruction sequence 2 RAS3 Instruction sequence 3 …… ……

[0122] It should be noted that each instruction sequence shown in Table 1 includes at least one instruction, and each error identifier corresponds to a RAS error, for example, RAS1 corresponds to RAS error 1, RAS2 corresponds to RAS error 2, and so on, which are not listed one by one.

[0123] To summarize, the error handling method provided in the present application injects preset errors into each functional unit in the on-chip system by means of error injection, triggers the processor to process the preset error and establishes an error identifier corresponding to the preset error. At the same time, the bus monitoring module records the preset instruction sequence sent to the functional unit by the processor during the process of processing the preset error, thereby establishing a corresponding relationship between the error identifier and the preset instruction sequence, completing the creation of the preset mapping relationship between the error identifier and the preset instruction sequence, and providing basic data support for processing errors that occur during the actual application of the on-chip system.

[0124] Understandably, Figure 4 The preset mapping relationship creation method provided in the illustrated embodiment can also be used to update the preset mapping relationship in practical applications. Figure 2 In the process of error handling in the embodiment shown, it is determined that the error currently occurring in the functional unit has not been handled before, and the preset mapping relationship does not record the preset instruction sequence for handling the error. In this case, the error can be handled according to Figure 4 The processing process provided by the illustrated embodiment creates an error identifier for the error, records the preset instruction sequence provided by the processor to the functional unit during the error processing, and adds the correspondence between the error identifier and the preset instruction sequence to the preset mapping relationship, thereby updating the preset mapping relationship. Based on this method, the preset mapping relationship can be continuously enriched and improved in the actual application process of the system on chip, so that the error handling method provided by the present application can handle more types of errors based on the preset mapping relationship, better share the work of the processor, and help improve the overall working performance of the processor and the system on chip.

[0125] Further, in an optional implementation, when the processor creates an error identifier according to the aforementioned content and the bus monitoring module confirms that the error identifier is valid, the processor further sends the error identifier to the error reporting unit, and the error reporting unit then establishes a correspondence between the preset error and the error identifier. Based on this, when the bus monitoring module queries the error identifier based on the first interrupt signal, the error reporting unit can feedback the corresponding error identifier according to the aforementioned correspondence, that is, Figure 2 As for the specific implementation process of the bus monitoring module and the error reporting unit exchanging information to obtain the target error identifier, please refer to Figure 2 The relevant contents in the illustrated embodiment will not be repeated here.

[0126] It should be noted that the error handling methods provided in the above-mentioned embodiments can be executed during the power-on startup phase of the system on chip, or can be manually triggered by the user after the system on chip is started. Of course, it can also be automatically triggered based on a preset trigger mechanism after the system on chip is started. In actual applications, the triggering method of the error handling method provided in this application can be selected according to the actual error handling requirements, and this application does not make any specific limitations on this process.

[0127] The present application also provides a bus monitoring module, which is configured to execute the steps performed by the bus monitoring module in the error handling method provided in any of the above embodiments. In an optional implementation, the composition of the bus monitoring module can refer to Figure 3 As shown, no further repetition is given here.

[0128] The present application also provides a processor, which is configured to execute the steps performed by the processor in the error handling method provided in any of the above embodiments.

[0129] The present application also provides an electronic device, including the system on chip provided by any of the aforementioned embodiments, and further including a preset memory, such as a memory, which is connected to the on-chip network of the system on chip. The processor and bus monitoring module of the system on chip can access the preset memory through the on-chip network, write data to the preset memory, or read data stored in the preset memory.

[0130] In some embodiments, this embodiment further provides a computer-readable storage medium, such as a floppy disk, an optical disk, a hard disk, a flash memory, a USB flash disk, an SD (Secure Digital Memory Card) card, an MMC (Multimedia Card) card, etc., in which one or more instructions for implementing the above steps are stored, and when the one or more instructions are executed by one or more processors, the processors execute the error handling method described above. For the relevant specific implementation, please refer to the above description, which will not be repeated here.

[0131] In addition to the above-mentioned methods and devices, an embodiment of the present application may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the error handling method according to various embodiments of the present application described in the above content of this specification.

[0132] The computer program product may be written in any combination of one or more programming languages ​​to write program codes for performing the operations of the embodiments of the present application, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" language or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0133] Those skilled in the art will appreciate that the contents disclosed in this disclosure may be subject to various modifications and improvements. For example, the various devices or components described above may be implemented by hardware, or by software, firmware, or a combination of some or all of the three.

[0134] In addition, although the present disclosure makes various references to certain units in the system according to embodiments of the present disclosure, any number of different units can be used and run on the client and / or server. The units are only illustrative, and different aspects of the system and method can use different units.

[0135] Flowcharts are used in this disclosure to illustrate the steps of the method according to the embodiments of the present disclosure. It should be understood that the preceding or following steps are not necessarily performed precisely in order. On the contrary, various steps may be processed in reverse order or simultaneously. At the same time, other operations may also be added to these processes.

[0136] Those skilled in the art will appreciate that all or part of the steps in the above method can be completed by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, etc. Optionally, all or part of the steps in the above embodiment can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiment can be implemented in the form of hardware or in the form of a software functional module. The present disclosure is not limited to any particular form of combination of hardware and software.

[0137] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or highly formal sense, unless explicitly defined as such herein.

[0138] The above is an explanation of the present disclosure and should not be considered as a limitation thereof. Although several exemplary embodiments of the present disclosure are described, it will be readily understood by those skilled in the art that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims. It should be understood that the above is an explanation of the present disclosure and should not be considered to be limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. An error handling method, characterized in that: Applied to a system on chip, the system on chip includes a network on chip and a processor, an error reporting unit, a bus monitoring module and at least one functional unit respectively connected to the network on chip, and the method includes the following steps performed by the bus monitoring module: In response to a first interrupt signal, obtaining a target error identifier of an error to be processed, wherein the first interrupt signal is triggered by the error reporting unit according to error information provided by an abnormal function unit where the error to be processed occurs; Determine a target instruction sequence corresponding to the target error identifier based on a preset mapping relationship between the error identifier and the preset instruction sequence, wherein each set of the preset instruction sequences is used to process an error; The target instruction sequence is sent to the abnormal function unit through the on-chip network to process the pending error.

2. The error handling method according to claim 1, characterized in that: The determining, based on a preset mapping relationship between the error identifier and the preset instruction sequence, a target instruction sequence corresponding to the target error identifier includes: Determining whether the target error identifier is valid; If the target error identifier is valid, a target instruction sequence corresponding to the target error identifier is determined based on a preset mapping relationship between the error identifier and the preset instruction sequence.

3. The error handling method according to claim 1, characterized in that: The step of obtaining a target error identifier of an error to be processed includes: Sending an identification query request to the error reporting unit; Obtain a target error identifier corresponding to the error to be processed that is fed back by the error reporting unit in response to the identifier query request.

4. The error handling method according to any one of claims 1 to 3, characterized in that: The process of creating the preset mapping relationship includes: Acquire an error identifier, where the error identifier is created by the processor after injecting a preset error into a target functional unit, where the target functional unit includes any one of the at least one functional unit; In response to an enable signal of the processor, recording a preset instruction sequence sent by the processor to the target functional unit, wherein the preset instruction sequence is used to process the preset error; A corresponding relationship between the error identifier and the preset instruction sequence is established to obtain the preset mapping relationship.

5. The error handling method according to claim 4, characterized in that: Recording a preset instruction sequence sent by the processor to the target functional unit, comprising: Determining whether the error identifier is valid; If the error flag is valid, recording a preset instruction sequence sent by the processor to the target functional unit; If the error identifier is invalid, first notification information indicating that the error identifier is invalid is sent.

6. The error handling method according to claim 4, characterized in that: Recording a preset instruction sequence sent by the processor to the target functional unit, comprising: In response to an enable signal, acquiring a bus signal sent by the processor to the target functional unit through the on-chip network; Analyzing the bus signal to obtain a preset instruction sequence; In response to the disable signal, the receiving of the bus signal is stopped.

7. The error handling method according to claim 6, characterized in that: Before acquiring the bus signal sent by the processor to the target functional unit through the on-chip network, the method further includes: Second notification information indicating that a recording function is successfully enabled is sent to the processor, where the second notification information is used to trigger a bus signal sent by the processor to the target functional unit through the on-chip network.

8. An error handling method, characterized in that: Applied to a system on chip, the system on chip includes a network on chip, a processor respectively connected to the network on chip, an error reporting unit, a bus monitoring module and at least one functional unit, the method includes the following steps performed by the processor: Injecting a preset error into a target functional unit, wherein the target functional unit includes any one of the at least one functional unit; In response to a second interrupt signal, creating an error flag, wherein the second interrupt signal is triggered by the error reporting unit according to error information fed back by the target functional unit in response to the preset error; An enable signal is sent, and a preset instruction sequence is sent to the target functional unit, wherein the preset instruction sequence is used to process the preset error, and the enable signal is used to trigger the bus monitoring module to record the preset instruction sequence and establish a preset mapping relationship between the error identifier and the preset instruction sequence.

9. The error handling method according to claim 8, characterized in that: Also includes: Acquire first notification information, where the first notification information is used to indicate that the error identifier is invalid; In response to the first notification information, the error flag is updated.

10. The fault handling method according to claim 8, characterized in that: Sending a preset instruction sequence to the target functional unit includes: Acquire second notification information, where the second notification information is sent by the bus monitoring module after the recording function is successfully turned on; In response to the second notification information, a preset instruction sequence is sent to the target functional unit.

11. The fault handling method according to any one of claims 8 to 10, characterized in that: Also includes: The error identifier is sent to the error reporting unit, so that the error reporting unit establishes a corresponding relationship between the preset error and the error identifier.

12. A bus monitoring module, characterized in that: The bus monitoring module is configured to execute the error handling method according to any one of claims 1 to 7.

13. A processor, characterized in that: The processor is configured to execute the error handling method according to any one of claims 8 to 11.

14. A system on chip, characterized in that: include: An on-chip network, an error reporting unit, at least one functional unit, a bus snooping module as claimed in claim 12, and a processor as claimed in claim 13, wherein: The error reporting unit, each of the functional units, the bus monitoring module and the processor are respectively connected to the on-chip network.

15. An electronic device, characterized in that: include: The system on chip as claimed in claim 14.

16. A computer-readable storage medium, characterized in that: A computer program is stored, and when the computer program is executed, the error handling method described in any one of claims 1 to 7 or any one of claims 8 to 11 is implemented.

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