Accelerator power consumption optimization method, system and device based on hybrid adjustment strategy and storage medium

Abstract

The invention discloses an accelerator power consumption optimization method, system and device based on a hybrid adjustment strategy and a storage medium. The method comprises the steps that a bank manager collects use state information of all bank modules of an accelerator; the accelerator judges whether the bank state is updated or not through a state machine; when the bank state is updated, the bank manager sends state information to the microcontroller through a low-speed transmission protocol; the microcontroller receives bank state information, controls a power supply module and a clock module of the accelerator through a regulation and control strategy according to the state information, and adjusts the power consumption state of the accelerator to an optimal mode; the microcontroller obtains on-board state information and adjusts the rotating speed of the fan according to the state information, and the optimal configuration of the power consumption state of the whole board is achieved. By applying the accelerator power consumption real-time adjusting method provided by the invention, it can be ensured that the accelerator always operates in the optimal state, and the cost of a data center is saved.

Description

Technical Field

[0001] The present invention belongs to the technical field of computers, and in particular relates to an accelerator power consumption optimization method, system, device and storage medium based on a hybrid adjustment strategy. Background Art

[0002] FPGA is widely used in data centers due to its performance advantages in low latency, high parallelism, and low power consumption. As early as 2018, Microsoft announced its hardware developed specifically for artificial intelligence computing based on Intel A10 / S10 FPGA chip design, and unloaded the file ranking operation of more than 30,000 lines of C++ code in the Bing search engine to FPGA for hardware acceleration. Under the same system latency, the throughput is nearly doubled after using FPGA for hardware acceleration; for the same throughput requirements, the system latency is reduced by 29% after using FPGA. And the additional power consumption brought by each FPGA is less than 25W, which is less than 10% higher than the original system, and the overall cost increase does not exceed 30%. Amazon AWS launched the FPGA cloud service EC2 F1 in 2016. Each F1 instance computing pool can be configured with 8 FPGAs, which are used in data analysis, video processing, security, machine learning and other application scenarios, providing users with flexible acceleration solutions to meet the needs of different workloads. IBM and Xilinx jointly announced a strategic collaboration to use Xilinx FPGA to accelerate workload processing technology on IBM POWER systems. The two parties jointly developed open acceleration infrastructure, software and middleware to meet the needs of emerging applications such as machine learning, network function virtualization (NFV), genetic analysis, high-performance computing (HPC) and big data analysis. IBM System Department developers used Xilinx FPGA accelerators to create solution protocol stacks for POWER-based servers, storage systems and middleware systems. So far, the application of FPGA in data centers has covered several key areas. In the field of machine learning, it is used to accelerate model training and reasoning; in network function virtualization, it is used to achieve high-speed network packet processing and firewall functions; in data storage and retrieval, it is used to accelerate data encryption, decryption and index construction operations. FPGA has gradually become one of the important technical means for data centers to improve performance, reduce energy consumption and enhance flexibility.

[0003] However, with the development of FPGA chip technology, although FPGA chips have more and more logical resources and higher performance, their power consumption is also increasing. Taking Xilinx FPGA chips as an example, the power consumption of Spartan-7 series chips is more than ten W, the power consumption of Artix-7 series chips may be close to 30 W, the power consumption of Kintex-7 series chips is roughly tens of W, and the power consumption of UltraScale series chips ranges from tens of watts to hundreds of watts. The power consumption of the latest adaptive computing acceleration platform product series is hundreds of watts or even higher. At the same time, FPGA accelerators, as coprocessors in data centers, may be idle most of the time, wasting more energy. Therefore, while ensuring performance, optimizing the power consumption of FPGAs has become a hot topic in academia and industry. CTChow et al. proposed a dynamic voltage adjustment method based on logic delay measurement circuit to reduce the power consumption of FPGA operation. For a given task, the minimum operating power supply voltage is derived through experiments, and during operation, the voltage is adjusted to operate at this critical point. Under different operating tasks, the power supply can achieve 4% to 54% power saving. However, this solution has only been verified as a FPGA energy saving concept, and there is no implementation strategy to optimize energy consumption. At the same time, the scheme adopts the method of periodic polling to obtain the internal voltage, which is not real-time. Jose Luis Nunez-Yanez proposed an FPGA voltage regulation method based on adaptive voltage scaling technology. By adding an in-situ detector outside the FPGA chip and instantiating the corresponding monitoring management unit in the FPGA, the device can adjust its voltage and frequency in a closed-loop configuration based on workload, process and operating conditions. The test results show that compared with the rated voltage operation at the same frequency, the energy consumption is saved by more than 85%. However, the scheme adopts the method of extending the base plate when implementing the in-situ detector, and the design of the FPGA monitoring management unit occupies more logic resources. Xilinx has built-in XADC module in its FPGA chip, which can read the temperature and voltage information inside the FPGA through the DRP interface, but it needs to instantiate IP cores such as XADC and DSP48E2 when using it, resulting in a waste of computing resources. At the same time, the scheme can only obtain the temperature information of the FPGA chip itself, and cannot obtain the status information of the entire accelerator board.

[0004] In summary, although a lot of research work has been carried out in the direction of FPGA power consumption management and optimization, this work has two defects: first, power consumption information is collected based on the FPGA itself, resulting in a waste of FPGA computing resources; second, power consumption control is implemented based on the main influencing factors of power consumption such as voltage, and the adjustment granularity is coarse, which cannot achieve fine-grained power consumption adjustment while ensuring performance. In the field of data centers, there are still few studies on specific implementation plans for fine-grained power consumption adjustment and optimization using FPGA accelerators as carriers. In particular, for data center application scenarios, it is of great practical significance to design an accelerator power consumption optimization solution based on a hybrid adjustment strategy to reduce energy consumption. Therefore, the present invention designs an out-of-band power consumption adjustment method based on a microcontroller to achieve fine-grained adjustment of FPGA accelerator power consumption. Summary of the invention

[0005] The main purpose of the present invention is to overcome the shortcomings and deficiencies of the prior art and to provide an accelerator power consumption optimization method, system, device and storage medium based on a hybrid adjustment strategy. The present invention can make the FPGA accelerator power consumption always run in an optimal state to solve the current problems of high ineffective power consumption and large energy waste of FPGA accelerators in data centers.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] In a first aspect, the present invention provides an accelerator power consumption optimization method based on a hybrid adjustment strategy, comprising the following steps:

[0008] The bank manager at the accelerator end collects the usage status information of each bank module of the accelerator; the accelerator determines whether the bank status is updated through the state machine; when the bank status is updated, the bank manager sends the status information to the microcontroller through a low-speed transmission protocol;

[0009] The microcontroller receives the bank status information, controls the accelerator power module and clock module through the power optimization strategy according to the status information, and adjusts the accelerator power consumption state to the optimal mode; the microcontroller obtains the board status information and adjusts the fan speed according to the status information to achieve the optimal configuration of the power consumption state of the whole board;

[0010] The accelerator-side bank manager is constructed by FPGA, and the accelerator-side state control system is composed of a microcontroller, a clock control module, and a power control module.

[0011] As a preferred technical solution, the bank manager includes a low-speed protocol transmission module, a framer, a state machine manager and multiple state receivers; wherein the low-speed protocol transmission module is used for the FPGA end to send data to the microcontroller end; the framer is used for data packetization, including a data protocol frame header, a frame tail, a checksum, and data; the state machine manager is used for bank state conversion; the state receiver is used to collect the usage status of each bank module of the accelerator, and the bank module includes an optical port module, a DDR module, and an IO module.

[0012] As a preferred technical solution, the accelerator determines whether the bank status is updated through a state machine, specifically:

[0013] Get the return status information of each monitoring module;

[0014] When the state changes, the state machine manager performs the corresponding state transition and sends the state information to the frame assembly module; when the state does not change, no transition occurs and waits for the accelerator state information feedback;

[0015] The status information is framed and encapsulated according to the custom data frame format and sent to the microcontroller of the accelerator through the sending module.

[0016] As a preferred technical solution, the customized data frame format is specifically:

[0017] The data frame includes a data frame header, bank number, bank status, checksum, and data frame tail;

[0018] The data frame header occupies two bytes, the bank number occupies N*two bytes, the bank status occupies N*two bytes, the checksum is the CRC value of the valid data excluding the frame header and frame tail, which occupies two bytes, the data frame tail occupies two bytes, and N is the number of banks used.

[0019] As a preferred technical solution, after the microcontroller at the accelerator end obtains the status information reported by the accelerator through the low-speed bus, the method further includes:

[0020] The microcontroller at the accelerator end verifies the received information through a built-in algorithm to determine the correctness of the information; the built-in algorithm is a CRC verification implementation algorithm;

[0021] When the microcontroller at the accelerator end receives the correct information, the microcontroller will search for the preset strategy stored in the microcontroller based on the received information and the bank number in the information, and complete the accelerator state arrangement so that the accelerator power consumption reaches the optimal state;

[0022] The preset strategy is: setting the power consumption optimization strategy in advance according to the bank function, and storing the strategy in the readable memory of the accelerator, and when the power consumption optimization adjustment is needed, adjusting the voltage and clock state according to the optimization strategy.

[0023] As a preferred technical solution, the power consumption optimization strategy is:

[0024] The clock and voltage of each bank of the FPGA are processed in segments. The power supply of resources that are not frequently used and are in an idle state is turned off. The operating clock and voltage of frequently used and idle resources are reduced to keep them in standby or low-power mode. Frequently used and working resources are kept at full load to ensure operating efficiency.

[0025] As a preferred technical solution, the bank operation state is adjusted according to the power consumption optimization strategy, specifically:

[0026] When the bank operating clock needs to be adjusted, the clock configuration file in the readable memory must be found according to the clock key-value pair, and then the configuration file is updated to the clock controller; when the bank operating clock does not need to be adjusted, the voltage state of the bank is adjusted according to the power optimization strategy.

[0027] In a second aspect, the present invention provides an accelerator power consumption optimization system based on a hybrid adjustment strategy, comprising:

[0028] An accelerator, used for computing acceleration;

[0029] The processor is used to implement the steps of the accelerator power consumption optimization method based on the hybrid adjustment strategy when executing the computer program.

[0030] In a third aspect, the present invention provides an electronic device, characterized in that the electronic device comprises:

[0031] at least one processor; and,

[0032] a memory communicatively connected to the at least one processor; wherein,

[0033] The memory stores computer program instructions that can be executed by the at least one processor, and the computer program instructions are executed by the at least one processor to enable the at least one processor to perform the steps of the accelerator power consumption optimization method based on the hybrid adjustment strategy.

[0034] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the accelerator power consumption optimization method based on a hybrid adjustment strategy are implemented.

[0035] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0036] 1. The present invention adopts an out-of-band management mode. The accelerator status monitoring and control are performed through the accelerator onboard microcontroller. The FPGA side only needs a small amount of logic resources to monitor the bank usage status. On the basis of ensuring real-time performance, the waste of logic resources is avoided and more programmable resources can be provided to the user layer.

[0037] 2. The present invention realizes fine-grained accelerator power consumption control. First, a multi-level optimization strategy based on clock and voltage is set according to the function of the bank, and a combination of clock and voltage regulation is implemented for different application states, so as to complete power consumption optimization and control in a fine-grained manner while ensuring performance.

[0038] 3. The power consumption optimization method proposed in the present invention is completely implemented autonomously on the accelerator side, without the participation of the host. When deployed in a data center, it does not require environmental configuration and system compatibility, which increases the universality of use.

[0039] 4. The invention automatically adjusts the power consumption status in real time according to the operating status of the accelerator, reducing the energy consumption and operation and maintenance costs of the data center. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 This is a design diagram of the accelerator in this embodiment of the present invention.

[0042] Figure 2 This is a design topology diagram of the monitoring and management system in an embodiment of the present invention.

[0043] Figure 3 The block diagram of the bank manager design of the accelerator FPGA side in the embodiment of the present invention.

[0044] Figure 4 The flowchart of the accelerator power consumption optimization method based on the hybrid adjustment strategy in the embodiment of the present invention.

[0045] Figure 5 The block diagram of the accelerator power consumption optimization system based on the hybrid adjustment strategy according to an embodiment of the present invention.

[0046] Figure 6 4 is a structural diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0047] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0048] Reference to "embodiments" in this application means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments.

[0049] like Figure 1 As shown, it is the design diagram of the accelerator in the present invention. The external interface of the accelerator is PCIe and optical port, which are used for external high-speed data transmission; the PCIe interface provides 3V3 power for MCU to use, ensuring that the MCU can still realize board status monitoring when the external AUX power supply is missing; the core computing component of the accelerator is FPGA. In order to ensure that more resources are reserved for users, only a small amount of resources are used to design the FPGA status monitoring module (bank manager) in the present invention to avoid unnecessary waste of resources. The accelerator includes multiple DDR memories for data caching. The power module includes AUX 12V output and multi-cascade DC circuits to meet the power supply requirements of 12V, 5V, 3V3, 1V8, 0V9, and 0V6. The control module uses a microcontroller as the core component, and cooperates with sensors, fans, memory, and multipliers (clock chips) to meet the power consumption management and control requirements of the accelerator.

[0050] like Figure 2As shown in the figure, the design topology diagram of the monitoring and management system is given. Among them, the FPGA modules in the accelerator, such as optical port, DDR, IO, FPGA (RSVD), etc. are connected to the bank manager in the FPGA. The bank manager sends the FPGA bank status information to the microcontroller in the accelerator through a low-speed signal. The microcontroller is connected to the clock control module and the power control module. The clock control module includes a non-volatile memory and a frequency multiplier. The configuration file of the frequency multiplier is stored in the non-volatile memory according to the preset strategy; the frequency multiplier is connected to each functional module of the FPGA, and can provide a running clock for each functional module respectively, which is convenient for fine-grained control. The power control module can output multiple voltages, which provide voltages for each functional module of the FPGA respectively, which is convenient for fine-grained control of the power supply. In this way, the closed-loop control of the accelerator power consumption optimization monitoring and management system is realized.

[0051] like Figure 3 The figure shows the design block diagram of the bank manager architecture on the accelerator FPGA side. In order to save FPGA logic resources, the bank manager adopts a streamlined design and is only responsible for status information collection. The complex processing work is handed over to the out-of-band microcontroller for implementation. Among them, the bank manager consists of four parts: low-speed protocol transmission module, framer, state machine manager, and state receiver. The low-speed protocol transmission module reports the status information data to the microcontroller through SPI, I2C and other protocols. The framer is responsible for assembling the collected data according to the protocol and handing it over to the low-speed protocol transmission module for transmission. The state machine manager is responsible for the status record and status conversion of each bank functional module, and the state receiver is used to receive the status information of each functional module.

[0052] like Figure 4The figure shows the workflow of the accelerator power optimization system based on the hybrid control strategy. The process is divided into the accelerator FPGA side and the accelerator microcontroller side. The process on the FPGA side is as follows: the FPGA bank manager is in an idle state and waits for the bank status update signal; if there is a status update, it sends a command to the framer of the bank manager, and the framer packages the status information into a data frame according to the preset protocol, and the bank manager state machine completes the state transition; then the low-speed transmission protocol module sends the data packaged by the framer to the microcontroller side. The process on the microcontroller side is as follows: the microcontroller waits for the information reported by the bank manager in interrupt mode. If the information is received, the correctness of the information is judged; if the judgment is wrong, it returns to the upper process to continue the process of waiting for the reported information. If the information is correct, it determines whether the bank status has changed according to the bank status information contained in the information; if the bank status has not changed, it returns to continue to report the information and wait. If the bank status changes, the preset power optimization strategy is checked according to the bank number and bank status in the information. If the optimization strategy includes clock update, it is necessary to first read the clock configuration file saved in the readable memory according to the strategy, then update the file to the clock controller, and then adjust the power module; otherwise, adjust the power module according to the preset strategy to complete the power consumption optimization adjustment.

[0053] In a specific embodiment, the accelerator power consumption optimization method based on the hybrid adjustment strategy of the present invention specifically includes the following steps:

[0054] S1. Design a bank manager on the accelerator FPGA chip side, including a low-speed protocol transmission module, a framer, a state machine manager, and multiple state receivers. The low-speed protocol transmission module is used to send data from the FPGA side to the microcontroller side. The framer is used to package data, including the data protocol frame header, frame tail, checksum, data, etc. The state machine manager is used for bank state conversion. The state receiver is used to collect the usage status of each bank module of the accelerator, including the optical port module, DDR module, IO module, etc.

[0055] S2. The bank manager collects the operating status of the accelerator bank in real time. The accelerator determines whether the bank status is updated through the state machine. When the bank status is updated, the framer completes the data packaging and sends the data to the microcontroller module through the low-speed protocol transmission module of the bank manager.

[0056] Furthermore, the accelerator determines whether the bank status is updated through a state machine, specifically:

[0057] Get the return status information of each monitoring module;

[0058] When the state changes, the state machine manager performs the corresponding state transition and sends the state information to the frame assembly module; when the state does not change, no transition occurs and waits for the accelerator state information feedback;

[0059] The status information is framed and encapsulated according to the custom data frame format and sent to the microcontroller of the accelerator through the sending module.

[0060] Furthermore, the customized data frame format is specifically:

[0061] The data frame includes a data frame header, bank number, bank status, checksum, and data frame tail;

[0062] The data frame header occupies two bytes, the bank number occupies N*two bytes, the bank status occupies N*two bytes, the checksum is the CRC value of the valid data excluding the frame header and frame tail, which occupies two bytes, the data frame tail occupies two bytes, and N is the number of banks used.

[0063] Furthermore, after the microcontroller at the accelerator end obtains the status information reported by the accelerator through the low-speed bus, the method further includes:

[0064] The microcontroller at the accelerator end verifies the received information through a built-in algorithm to determine the correctness of the information; the built-in algorithm is a CRC verification implementation algorithm;

[0065] When the microcontroller at the accelerator end receives the correct information, the microcontroller will search for the preset strategy stored in the microcontroller based on the received information and the bank number in the information, and complete the accelerator state arrangement so that the accelerator power consumption reaches the optimal state;

[0066] The preset strategy is: setting the power consumption optimization strategy in advance according to the bank function, and storing the strategy in the readable memory of the accelerator, and when the power consumption optimization adjustment is needed, adjusting the voltage and clock state according to the optimization strategy.

[0067] S3, the microcontroller on the accelerator side responds to the data on the FPGA side in interrupt mode. First, the correctness of the data information is judged. If the data verification is correct, the execution continues; if the data verification is wrong, the data packet is directly discarded;

[0068] S4, the microcontroller determines whether the bank status has changed according to the information, and continues to execute if the bank status has changed; if the status has not changed, it returns to execute step S3;

[0069] S5. The microcontroller calls the power consumption optimization strategy preset in the microcontroller according to the bank number in the data packet and its corresponding bank status. The power consumption optimization strategy is as follows: the clock and voltage of each bank of the FPGA are processed in segments, and the power supply is turned off for the resources that are not frequently used and are in an idle state; the operating clock and voltage of the resources that are frequently used and are in an idle state are reduced to keep them in a standby state or a low power consumption mode; the resources that are frequently used and in operation are in a full load state to ensure the operating efficiency.

[0070] S6. According to the power consumption optimization strategy of the fifth step, the bank operation state is adjusted; when the bank operation clock needs to be adjusted, the clock configuration file in the readable memory needs to be found according to the clock key-value pair, and then the configuration file is updated to the clock controller; when the bank operation clock does not need to be adjusted, the voltage state of the bank is adjusted according to the power consumption optimization strategy.

[0071] S7. During the execution of steps S1-S6, the microcontroller executes the accelerator temperature and power consumption reading operations in parallel, and adjusts the accelerator fan speed in real time according to the power consumption and temperature information to keep the power consumption of the entire accelerator in an optimal state.

[0072] Based on the same idea as the accelerator power consumption optimization method based on the hybrid adjustment strategy in the above-mentioned embodiment, the present invention also provides an accelerator power consumption optimization system based on the hybrid adjustment strategy, which can be used to execute the above-mentioned accelerator power consumption optimization method based on the hybrid adjustment strategy. For ease of explanation, the structural schematic diagram of the embodiment of the accelerator power consumption optimization system based on the hybrid adjustment strategy only shows the parts related to the embodiment of the present invention. Those skilled in the art can understand that the illustrated structure does not constitute a limitation on the device, and may include more or fewer components than shown in the diagram, or combine certain components, or arrange the components differently.

[0073] See also Figure 5 , in another embodiment of the present application, an accelerator power consumption optimization system 100 based on a hybrid adjustment strategy is provided, the system comprising an accelerator 101 for performing computational acceleration;

[0074] The processor 102 is configured to implement the steps of the accelerator power consumption optimization method based on the hybrid adjustment strategy when executing the computer program.

[0075] It should be noted that the accelerator power consumption optimization system based on a hybrid regulation strategy of the present invention corresponds one-to-one to the accelerator power consumption optimization method based on a hybrid regulation strategy of the present invention. The technical features and beneficial effects described in the above-mentioned embodiment of the accelerator power consumption optimization method based on a hybrid regulation strategy are applicable to the embodiment of the accelerator power consumption optimization based on a hybrid regulation strategy. For specific contents, please refer to the description in the embodiment of the method of the present invention. It will not be repeated here. This is hereby declared.

[0076] In addition, in the implementation of the accelerator power consumption optimization system based on the hybrid adjustment strategy in the above-mentioned embodiment, the logical division of each program module is only an example. In actual applications, the above-mentioned functions can be assigned to different program modules as needed, for example, for the convenience of corresponding hardware configuration requirements or software implementation. That is, the internal structure of the accelerator power consumption optimization system based on the hybrid adjustment strategy is divided into different program modules to complete all or part of the functions described above.

[0077] See also Figure 6 In one embodiment, an electronic device for implementing an accelerator power consumption optimization method based on a hybrid adjustment strategy is provided. The electronic device 200 may include a first processor 201, a first memory 202 and a bus, and may also include a computer program stored in the first memory 202 and executable on the first processor 201, such as an accelerator power consumption optimization program 203 based on a hybrid adjustment strategy.

[0078] Among them, the first memory 202 includes at least one type of readable storage medium, and the readable storage medium includes flash memory, mobile hard disk, multimedia card, card-type memory (for example: SD or DX memory, etc.), magnetic memory, disk, optical disk, etc. In some embodiments, the first memory 202 can be an internal storage unit of the electronic device 200, such as a mobile hard disk of the electronic device 200. In other embodiments, the first memory 202 can also be an external storage device of the electronic device 200, such as a plug-in mobile hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (SecureDigital, SD) card, a flash card (Flash Card), etc. equipped on the electronic device 200. Further, the first memory 202 can also include both an internal storage unit of the electronic device 200 and an external storage device. The first memory 202 can not only be used to store application software and various types of data installed in the electronic device 200, such as the code of the accelerator power consumption optimization program 203 based on the hybrid adjustment strategy, but also can be used to temporarily store data that has been output or is to be output.

[0079] In some embodiments, the first processor 201 may be composed of an integrated circuit, for example, a single packaged integrated circuit, or a plurality of packaged integrated circuits with the same or different functions, including one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and combinations of various control chips, etc. The first processor 201 is the control core (Control Unit) of the electronic device, and uses various interfaces and lines to connect various components of the entire electronic device, and executes various functions and processes data of the electronic device 200 by running or executing programs or modules stored in the first memory 202, and calling data stored in the first memory 202.

[0080] Figure 6 Only an electronic device with components is shown, and those skilled in the art will understand that Figure 6 The structure shown does not constitute a limitation on the electronic device 200 , and may include fewer or more components than shown in the figure, or combine certain components, or arrange the components differently.

[0081] The accelerator power consumption optimization program 203 based on the hybrid adjustment strategy stored in the first memory 202 in the electronic device 200 is a combination of multiple instructions. When running in the first processor 201, it can achieve:

[0082] The bank manager at the accelerator end collects the usage status information of each bank module of the accelerator; the accelerator determines whether the bank status is updated through the state machine; when the bank status is updated, the bank manager sends the status information to the microcontroller through a low-speed transmission protocol;

[0083] The microcontroller receives the bank status information, controls the accelerator power module and clock module through the power optimization strategy according to the status information, and adjusts the accelerator power consumption state to the optimal mode; the microcontroller obtains the board status information and adjusts the fan speed according to the status information to achieve the optimal configuration of the power consumption state of the whole board;

[0084] The accelerator-side bank manager is constructed by FPGA, and the accelerator-side state control system is composed of a microcontroller, a clock control module, and a power control module.

[0085] Furthermore, if the module / unit integrated in the electronic device 200 is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a non-volatile computer-readable storage medium. The computer-readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a mobile hard disk, a magnetic disk, an optical disk, a computer memory, and a read-only memory (ROM).

[0086] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the program can be stored in a non-volatile computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0087] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0088] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications that do not deviate from the spirit and principles of the present invention should be equivalent replacement methods and are included in the protection scope of the present invention.

Claims

1. An accelerator power consumption optimization method based on a hybrid regulation strategy, characterized in that: The steps include: The bank manager at the accelerator end collects the usage status information of each bank module of the accelerator; the accelerator determines whether the bank status is updated through the state machine; when the bank status is updated, the bank manager sends the status information to the microcontroller through a low-speed transmission protocol; The microcontroller receives the bank status information, controls the accelerator power module and clock module through the power optimization strategy according to the status information, and adjusts the accelerator power consumption state to the optimal mode; the microcontroller obtains the board status information and adjusts the fan speed according to the status information to achieve the optimal configuration of the power consumption state of the whole board; The accelerator-side bank manager is constructed by FPGA, and the accelerator-side state control system is composed of a microcontroller, a clock control module, and a power control module.

2. The accelerator power consumption optimization method based on the hybrid regulation strategy according to claim 1 is characterized in that: The bank manager includes a low-speed protocol transmission module, a framer, a state machine manager and multiple state receivers; wherein the low-speed protocol transmission module is used for the FPGA end to send data to the microcontroller end; the framer is used for data packetization, including a data protocol frame header, a frame tail, a checksum, and data; the state machine manager is used for bank state conversion; the state receiver is used to collect the use status of each bank module of the accelerator, and the bank module includes an optical port module, a DDR module, and an IO module.

3. The accelerator power consumption optimization method based on the hybrid regulation strategy according to claim 2 is characterized in that: The accelerator determines whether the bank status is updated through a state machine, specifically: Get the return status information of each monitoring module; When the state changes, the state machine manager performs the corresponding state transition and sends the state information to the framing module; When the state has not changed, no conversion occurs, and the accelerator state information feedback is waited for; The status information is framed and encapsulated according to the custom data frame format and sent to the microcontroller of the accelerator through the sending module.

4. The accelerator power consumption optimization method based on the hybrid regulation strategy according to claim 3 is characterized in that: The customized data frame format is specifically: The data frame includes a data frame header, bank number, bank status, checksum, and data frame tail; The data frame header occupies two bytes, the bank number occupies N*two bytes, the bank status occupies N*two bytes, the checksum is the CRC value of the valid data excluding the frame header and frame tail, which occupies two bytes, the data frame tail occupies two bytes, and N is the number of banks used.

5. The accelerator power consumption optimization method based on the hybrid regulation strategy according to claim 4 is characterized in that: After the microcontroller at the accelerator end obtains the status information reported by the accelerator through the low-speed bus, the method further includes: The microcontroller at the accelerator end verifies the received information through a built-in algorithm to determine the correctness of the information; the built-in algorithm is a CRC verification implementation algorithm; When the microcontroller at the accelerator end receives the correct information, the microcontroller will search for the preset strategy stored in the microcontroller based on the received information and the bank number in the information, and complete the accelerator state arrangement so that the accelerator power consumption reaches the optimal state; The preset strategy is: setting the power consumption optimization strategy in advance according to the bank function, and storing the strategy in the readable memory of the accelerator, and when the power consumption optimization adjustment is needed, adjusting the voltage and clock state according to the optimization strategy.

6. The accelerator power consumption optimization method based on the hybrid regulation strategy according to claim 7 is characterized in that: The power consumption optimization strategy is: The clock and voltage of each bank of the FPGA are processed in segments. The power supply of resources that are not frequently used and are in an idle state is turned off. The operating clock and voltage of frequently used and idle resources are reduced to keep them in standby or low-power mode. Frequently used and working resources are kept at full load to ensure operating efficiency.

7. The accelerator power consumption optimization method based on the hybrid regulation strategy according to claim 7 is characterized in that: According to the power optimization strategy, the bank operation status is adjusted as follows: When the bank operating clock needs to be adjusted, the clock configuration file in the readable memory must be found according to the clock key-value pair, and then the configuration file is updated to the clock controller; when the bank operating clock does not need to be adjusted, the voltage state of the bank is adjusted according to the power optimization strategy.

8. An accelerator power consumption optimization system based on a hybrid regulation strategy, characterized in that: include: An accelerator, used for computing acceleration; A processor is used to implement the steps of the accelerator power consumption optimization method based on a hybrid adjustment strategy as described in any one of claims 1 to 7 when executing the computer program.

9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and, a memory communicatively connected to the at least one processor; wherein, The memory stores computer program instructions that can be executed by the at least one processor, and the computer program instructions are executed by the at least one processor so that the at least one processor can perform the steps of the accelerator power consumption optimization method based on a hybrid adjustment strategy as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the accelerator power consumption optimization method based on a hybrid adjustment strategy as described in any one of claims 1 to 7 are implemented.

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