FPGA top netlist integration method and system

Abstract

The invention discloses an FPGA top netlist integration method and system, and the method comprises the steps: carrying out the instantiation of a submodule, and obtaining one or more instances contained in the submodule, one or more ports contained in each instance, and the port name and the port type of each port; for each port, determining connection line information of the current port according to a preset port connection rule; wherein the preset port connection rule is artificially made or generated according to a historical connection scheme; performing classification according to a preset connection state category to obtain connection state information of the port; generating a connection report according to one or more instances contained in the submodule, one or more ports contained in each instance and port information of each port; the port information comprises a port name, a port type, connection line information and connection state information. According to the scheme, top-layer netlist integration can be automatically carried out, the connection report is generated, and the integration efficiency is remarkably improved.

Description

Technical Field

[0001] The embodiments of the present application relate to but are not limited to the field of chip design and manufacturing, and in particular to a FPGA top-level netlist integration method and system. Background Art

[0002] Modern FPGA (Field-Programmable Gate Array) designs are becoming increasingly complex, involving a large number of components, modules, signals, and connections. In order to ensure the correctness and efficiency of FPGA design, it is usually necessary to optimize each level of the design. Among them, top-level netlist integration is a key link, involving the connection and resource allocation between multiple sub-modules, mainly including: interface definition and configuration of multiple modules or IP cores, a large number of signal connections and timing constraints, and effective resource allocation and mapping to meet the resource limitations of FPGA (such as logic units, IO pins, clocks, etc.).

[0003] However, existing integration tools or processes usually have some problems when handling these tasks: low efficiency. Existing tools often face bottlenecks when dealing with complex or large designs, which makes the integration process time-consuming and prolonged, which not only affects the efficiency of the design, but also increases the cost of the design; difficult to expand. Many tools lack flexibility. When faced with different design scales or diversified design requirements, they often need to be adjusted or reconfigured from scratch, and their applicability still has room for improvement.

[0004] In view of the above problems, it is urgent to develop a new FPGA top-level netlist integration method and tool. This new method should be able to significantly improve the integration efficiency and have good scalability to effectively solve the problems of existing tools and provide better support for FPGA design. Summary of the invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] The embodiments of the present application provide a method and system for integrating a top-level FPGA netlist, which can significantly improve the integration efficiency and solve the technical problem of low efficiency in existing top-level FPGA netlist integration solutions.

[0007] An embodiment of the present application provides an FPGA top-level netlist integration method, including: Instantiate the submodule to obtain one or more instances contained in the submodule, one or more ports contained in each instance, and the port name and port type of each port; For each port, the connection line information of the current port is determined according to a preset port connection rule; wherein the preset port connection rule is manually formulated or generated according to a historical connection scheme; Classify according to preset connection status categories to obtain connection status information of the port; A connection report is generated according to one or more instances contained in the submodule, one or more ports contained in each instance and port information of each port; the port information includes port name, port type, connection line information and connection status information.

[0008] An embodiment of the present application also provides an FPGA top-level netlist integration system, including: a memory and a processor; The memory is used to store a program for performing FPGA top-level netlist integration; The processor is used to read the program for performing FPGA top-level netlist integration and execute the FPGA top-level netlist integration method as described in any embodiment of the present application.

[0009] Compared with the related art, the embodiment of the present application provides a FPGA top-level netlist integration method and system. After instantiating the submodule, the scheme can obtain one or more instances contained in the submodule, one or more ports contained in each instance, and the port name and port type of each port; then the connection line information of each port can be determined according to the preset port connection rules, and the connection of the port can be classified according to the preset connection status category to obtain the connection status information of the port; finally, a connection report is generated according to the one or more instances contained in the submodule, the one or more ports contained in each instance, and the port information of each port (port name, port type, connection line information, and connection status information). Through this scheme, the top-level netlist can be automatically integrated, the connection report can be generated, and the integration efficiency can be significantly improved.

[0010] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0012] Figure 1 A brief flow chart of the FPGA top-level netlist integration method according to an embodiment of the present application; Figure 2A schematic diagram of a graphical operation interface of the FPGA top-level netlist integration system according to an embodiment of the present application; Figure 3 This is a flow chart of the FPGA top-level netlist integration method according to an embodiment of the present application; Figure 4 A schematic diagram of the FPGA top-level netlist integration system according to an embodiment of the present application; Figure 5 This is a schematic diagram of the FPGA top-level netlist integration tool according to an embodiment of the present application. DETAILED DESCRIPTION

[0013] The present application describes multiple embodiments, but the description is exemplary rather than restrictive, and it is obvious to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present application. Although many possible feature combinations are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0014] The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in the present application may also be combined with any conventional features or elements to form a unique invention scheme. Any features or elements of any embodiment may also be combined with features or elements from other invention schemes to form another unique invention scheme. Therefore, it should be understood that any feature shown and / or discussed in the present application may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the attached claims and their equivalents, the embodiments are not subject to other restrictions. In addition, various modifications and changes may be made within the scope of protection of the attached claims.

[0015] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps of the specific order described. As will be understood by those of ordinary skill in the art, other sequences of steps are also possible. Therefore, the specific sequence of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to the steps of performing them in the order written, and those skilled in the art can easily understand that these sequences can be changed and still remain within the spirit and scope of the embodiments of the present application.

[0016] An embodiment of the present application provides a method for integrating a top-level netlist of an FPGA, such as Figure 1 As shown, the following steps may be included: Step S110: instantiate the submodule to obtain one or more instances contained in the submodule, one or more ports contained in each instance, and the port name and port type of each port; Step S120: for each port, determining the connection line information of the current port according to a preset port connection rule; wherein the preset port connection rule is manually formulated or generated according to a historical connection scheme; Step S130: Classify according to preset connection status categories to obtain connection status information of the port; Step S140: Generate a connection report according to one or more instances included in the submodule, one or more ports included in each instance and port information of each port; the port information includes port name, port type, connection line information and connection status information.

[0017] The FPGA top-level netlist integration method of this embodiment can obtain one or more instances contained in the submodule, one or more ports contained in each instance, and the port name and port type of each port after instantiating the submodule; then the connection line information of each port can be determined according to the preset port connection rule, and the connection of the port is classified according to the preset connection status category to obtain the connection status information of the port; finally, a connection report is generated according to the one or more instances contained in the submodule, the one or more ports contained in each instance, and the port information of each port (port name, port type, connection line information, and connection status information). This solution can automatically perform top-level netlist integration and generate connection reports, reduce manual participation, and significantly improve integration efficiency.

[0018] In an exemplary embodiment, after determining the connection line information of the current port according to the preset port connection rule for each port, the method may further include: After receiving the pre-connection instruction, the connected resources are determined according to the current connection status information of each port and the set constraint information, and batch pre-connection is performed; the resources may include: opposite end port and connection line information; Generate a pre-connection file according to the connection plan after the pre-connection is completed.

[0019] Exemplarily, the file format of the pre-connection file may be the same as the file format of the preset port connection rule.

[0020] The FPGA top-level netlist integration method of this embodiment, after receiving the pre-connection instruction, automatically searches for qualified resources according to the settings and performs batch pre-connection. From a global perspective, it searches for and implements connection schemes that meet the constraints, and finally implements a reasonable wiring scheme, so that engineers can make manual adjustments based on this scheme, saving the time of manually generating connection schemes, and significantly reducing the number of modification iterations, thereby improving integration efficiency.

[0021] In addition, the FPGA top-level netlist integration method of this embodiment also generates a pre-connection file in a preset format according to the connection scheme after the pre-connection is completed. The pre-connection file can be applied to later integrated design schemes of similar types to improve the integration efficiency of later similar schemes. Based on the scheme of this embodiment, when there are similar schemes for different design scales or diversified design requirements, improvements can be made directly on the basis of similar schemes without having to adjust or reconfigure from scratch. This also confirms that the preset port connection rules of this embodiment can be generated according to the historical connection scheme, and also shows that the top-level netlist integration method of this embodiment is a well-scalable solution.

[0022] In an exemplary embodiment, the preset port connection rule includes one or more; each of the preset port connection rules may include a port name part and a connection name part, the port name part is used to determine the port corresponding to the preset port connection rule, and the connection name part is used to determine the connection line information of the port corresponding to the preset port connection rule; Determining the connection line information of the current port according to the preset port connection rule may include: traversing each port, determining the preset port connection rule corresponding to the current port according to the port name of the current port and the instance where the port is located; and determining the connection line information of the current port according to the corresponding preset port connection rule.

[0023] In an example of this embodiment, the port name portion may include a port designation field and an instance designation field, the port designation field being used to confirm a port range to which a preset port connection rule applies, and the instance designation field being used to confirm an instance range to which a preset port connection rule applies; Determining the preset port connection rule corresponding to the current port according to the port name of the current port and the instance where the port is located may include: confirming the preset port connection rule corresponding to the current port according to the port name of the current port, the instance where the current port is located, the port range to which the preset port connection rule applies, and the instance range to which the preset port connection rule applies.

[0024] It should be noted that the port range specified by the port designation field can be a range or a port, and this application does not limit this; the instance range specified by the instance designation field can be a range or an instance, and this application does not limit this. In addition, the instance designation field can also be empty. When the instance designation field is empty, it means that the current preset port connection rule is applicable to all instances where the port specified by the port designation field is located.

[0025] In an example of this embodiment, the connection name part may include a variable field and a captured value field, and the captured value field may include one or more captured values; the variable field is used to represent the hardware configuration information corresponding to the instance generated by the current preset port connection rule, and the hardware configuration information may include location information, group number information, and clock domain information; the captured value field is used to confirm the opposite port to which the current port is connected, wherein each captured value corresponds to one opposite port; Determining the connection line information of the current port according to the corresponding preset port connection rule may include: determining the connection line information of the current port according to the hardware configuration information and a connection port corresponding to the current port.

[0026] In an example of this embodiment, a preset port connection rule can be set for each sub-module, or a preset port connection rule can be set for a type of sub-module. This application does not impose any restrictions on this, as long as it can ensure that the connection line information obtained according to the preset port connection rule (connection is performed according to the connection line information) meets the requirements.

[0027] The FPGA top-level netlist integration method of this embodiment determines the connection line information corresponding to the port by presetting the port connection rule, thereby reducing manual operations and improving integration efficiency. In addition, since a preset port connection rule can be applied to multiple ports, the connections of multiple ports with the same rule can be processed in batches, which can also improve processing efficiency.

[0028] In an example of this embodiment, the preset port connection rules can be implemented in the form of a port connection rule dictionary. Exemplarily, the port connection rule dictionary consists of a key-value pair of a port name and a connection name. When a port is not specified in the dictionary, the connection name corresponding to the port is set to "instance name + port name" by default. Therefore, in general, the dictionary specifies the connection of the input ports of each module. The following introduces the syntax of the connection rule dictionary, which is divided into two parts: port name and connection name: The port name part may include an instance-specified field and a port-specified field, and the two types of specifications are separated by a ".", i.e., "instance-specified.port-specified". The instance-specified field may specify both an instance and an instance range. If an instance is specified, the corresponding instance name can be directly written (such as "X1Y1"); if an instance range is specified, for example, "X[${x_min}:${x_max}]Y[2:${y_max}:4]", it specifies a set of instance names that meet the conditions, and the conditions are that the number after the instance name "X" is between the number represented by the variable "${x_min}" and the number represented by "${x_max}" (a left-closed and right-closed interval), and the number after "Y" meets the conditions of starting from 2, skipping 3 numbers each time, until the number represented by the variable "${y_max}". The above-mentioned variables may be pre-defined in the architecture information. However, instance specification is not required. When no instance or instance range is specified, the rule is considered to be valid for all instances of the module to which the specified port belongs. Port specification is required. Here, you only need to follow the usage of regular expressions to match the desired port name string.

[0029] The connection name part can be represented by a combination of characters and "variables", "{captured value}" and "<expression>" elements (the expression is not required). Among them, "variables" reflect some information corresponding to the current instance, such as location, group number, and clock domain information. They are parsed from the current instance name and architecture information, constraint information, packaging information and other files, and are identified by different variable names; "{captured value}" refers to the matching sub-expression captured by the regular expression when specifying the port in the above port name part. There can be multiple matching "{captured value}", which are used to replace several characters or strings in the port name, such as "{0}" represents the first captured value; if necessary, "<expression>" can also be included. The role of "<expression>" is to implement simple digital operations, avoid using specific numerical values, and ensure that the connection rules are widely applicable, such as "<y_max / / 2+{0}> " means divide the variable y_max by 2 and add the first captured number.

[0030] The port name part and the connection name part are separated by ",", that is, "port name part, connection name part", thus forming a complete preset port connection rule that meets the grammatical requirements.

[0031] As can be seen from this example, the port name part and the connection name part are not fixed values, but expressions. This allows the ports of each sub-module to be classified according to type and function. Ports of the same type can use the same connection rule dictionary, which simplifies the content to be written and makes the query and modification operations easier.

[0032] The FPGA top-level netlist integration method of this example, on the one hand, determines the port name and connection name through the connection rules specified in the dictionary, and batch processes the port connections with the same rules. This approach can reduce the time of repeatedly consulting the dictionary and improve processing efficiency. On the other hand, by using the matching sub-expressions (i.e., captured values) captured by the regular expression, the designer can flexibly adjust the connection relationship in the top-level netlist without modifying the underlying components or modules. This flexibility enables designers to respond to changing needs more quickly and improve design efficiency.

[0033] In an exemplary embodiment, the preset connection status categories may include "power supply", "multi-drive", "no drive", "no load", "suspended", and "bus". The classifying of the connection of the port according to the preset connection status category to obtain the connection status information of the port may include: Classify the ports according to the preset connection status categories and the connection line information of the ports to obtain classification results; The classification result is used as the connection status information of the current port.

[0034] It should be noted that this embodiment does not limit the types of preset connection status categories, and they can be added or deleted according to actual needs.

[0035] The FPGA top-level netlist integration method of this embodiment classifies the ports according to the preset connection status categories and the connection line information of the ports to obtain the connection status information of the ports. In this way, on the one hand, it is more convenient for users to intuitively understand the connection status of the ports, and it is easier to find problems in the integration process, thereby improving the integration efficiency; on the other hand, it also lays the foundation for the generation of subsequent connection reports.

[0036] In an exemplary embodiment, after the sub-module is instantiated, it can also include: performing a uniqueness check on the global instance name, when the uniqueness check fails, prompting the instance with the instance name conflict, and re-instantiating the sub-module where the instance is located after receiving the user's modification information on the instance.

[0037] The FPGA top-level netlist integration method of this embodiment performs a uniqueness check on the global instance name after instantiating each submodule and before confirming the connection status information of the port. This can detect problems with the instance name as early as possible and prompt the user to modify it in time, thereby improving integration efficiency by discovering and modifying it early.

[0038] In an exemplary embodiment, before instantiating the submodule, the method may further include: converting various types of information contained in the received FPGA system information into corresponding data structures and storing them in a preset storage file; the system information includes the following types of information: architecture information, constraint information, packaging information, and submodule information; The instantiation of the submodules may include: determining the instantiation location of each instance according to the design layout specified by the architecture information; determining the port name and port type of each port according to the submodule information; Before classifying the connections of the ports according to the preset connection status categories and obtaining the connection status information of the ports, the method may further include: checking the connection status of all the ports according to the constraint information and the encapsulation information.

[0039] Existing top-level netlist integration tools lack an immediate global inspection mechanism when generating top-level netlists, and connection errors are often not discovered until the simulation stage after the netlist is generated, which undoubtedly increases the repetitiveness of the work. The FPGA top-level netlist integration method of this embodiment can automatically identify connection errors (for example, multiple output ports connected together will result in "multiple drivers"; for example, multiple input ports connected together will result in "no driver") through connection status inspection during the netlist integration stage, discover and solve problems as early as possible, avoid illegal connections, contradictions, etc. in the final generated solution, and cause the FPGA to fail to work properly, thereby improving integration efficiency.

[0040] For example, when a problem is detected, a prompt may pop up to remind the user to modify the corresponding problem, and after the user completes, the user may click an update command to update the problematic area. In this way, modifications may be made quickly after a connection error is found.

[0041] In an exemplary embodiment, the method may further include: displaying each submodule, the instances contained in each submodule, the ports contained in each instance, and the port information; the port information includes: port name, port type, connection line information, and connection status information.

[0042] For example, the above information can be displayed in Figure 2 In the graphical operation interface shown.

[0043] In an example of this embodiment, the method may further include: accepting operation instructions for an instance (such as adding, deleting, modifying, etc.) input by a user; and accepting operation instructions for a sub-module input by a user.

[0044] The top-level netlist integration method of this embodiment presents the integration status (i.e., various information during the integration process) in real time through a graphical operation interface during the integration process. In this way, the user can view the integration progress and the status of each module in the graphical operation interface, and can also manually intervene and adjust the design.

[0045] In an exemplary embodiment, after generating the connection report, the method may further include: when an update instruction is received, updating according to the type of the update instruction.

[0046] In an example of this embodiment, when the connection update instruction is received, the changed port and the latest connection line information corresponding to the port are determined, and the connection line information corresponding to the port is updated to the latest connection line information.

[0047] The FPGA top-level netlist integration method of this example adopts an incremental integration strategy. When receiving an update connection instruction, it determines the changed port and the latest connection line information corresponding to the port, and only updates the changed connection, while retaining the original data for the unchanged part. This can reduce unnecessary data operations and graphics rendering, and speed up the update speed.

[0048] For example, the pre-connection file and connection report of the preset format generated in the above embodiment can be manually checked. When a problem is found, the pre-connection file or the preset port connection rule can be adjusted according to the cause of the problem, and then an update connection instruction is issued. When the system receives the update connection instruction, it will re-determine the connection line information of the port according to the preset port connection rule, classify the connection of the port according to the preset connection status category to obtain the connection status information of the port, generate a new connection report, etc. In this way, the connection between each submodule can be ensured to be correct, and the accuracy of the design can be guaranteed.

[0049] In an example of this embodiment, after generating the connection report, the method may further include: upon receiving an instruction to update the instance list, determining a changed instance, and re-instantiating a submodule where the changed instance is located.

[0050] The FPGA top-level netlist integration method of this example adopts an incremental integration strategy. When receiving an instruction to update the instance list, it determines the instances that have changed and only updates the changed instances, while retaining the original data of the unchanged instances. This can reduce unnecessary data operations and graphics rendering and speed up the update process.

[0051] In an example of this embodiment, after generating the connection report, it may also include: when receiving an update system instruction, determining the changed system information, and updating the changed system information; the system information includes the following types of information: architecture information, constraint information, encapsulation information, and sub-module information.

[0052] The FPGA top-level netlist integration method of this example adopts an incremental integration strategy. When receiving a system update instruction, it determines the instance that has changed and only updates the system information that has changed, thereby speeding up the update speed.

[0053] In an example of this embodiment, after generating the connection report, the method may further include: upon receiving a submodule update instruction, determining changed submodule information, and updating the changed submodule information.

[0054] The FPGA top-level netlist integration method of this example adopts an incremental integration strategy. When receiving the instruction to update the submodule, the submodule that has changed is determined, and only the submodule that has changed is updated, and the original data of the instance that has not changed is retained. This can reduce unnecessary data operations and graphics rendering, and speed up the update speed. Based on the top-level netlist integration method of this example, whenever a submodule design version is fixed, the integration process can be entered to update the top-level netlist without waiting for the design of all submodules to be completed. In this way, on the one hand, the possibility of connection errors between submodules being discovered in advance is greatly improved, so that the connection errors can be solved as soon as possible, thereby improving the integration efficiency; on the other hand, when facing complex large-scale designs, each iteration only updates the changed parts, without waiting for all submodules to be ready, and the time cost of top-level netlist integration is also shared, which can also improve the integration efficiency, and solve the technical problem of "the project progress is prone to bottlenecks due to mismatched design progress of multiple submodules".

[0055] It can be seen from this embodiment that the solution adopts an incremental integration strategy when updating connections, instances, system information and sub-module information, and only updates the changed parts. This improves the update efficiency and integration efficiency, and also avoids performance problems caused by many sub-modules, ports, resources, etc. when processing large designs.

[0056] In an exemplary embodiment, the method may further include: saving relevant data involved in generating the top-level netlist, such as architecture information, constraint information, packaging information, submodule information, the relationship between the submodule and the instance generated after instantiation, and the port name, port type, connection line information, and connection status information of each port.

[0057] The top-level netlist integration method of this embodiment saves the relevant data involved in the top-level netlist generation and supports data archiving, so that the data can be used. For example, for some designs with large similarity, only some key architecture parameters and submodule instance information need to be modified to quickly initialize the top-level netlist for the new design.

[0058] In an exemplary embodiment, the method may further include: saving the current integration state in real time. In this way, the top-level netlist integration method of this embodiment can support multi-person collaboration.

[0059] The following is a detailed description of the process of top-level netlist integration using the FPGA top-level netlist integration method of the present application using an embodiment. Figure 3 As shown, the following steps may be included: Step S301: Create a new netlist integration project, and initialize data objects related to the netlist integration project into a project file corresponding to the netlist integration project, wherein the related data objects include historical data information related to the project.

[0060] In step S301, after the data object is initialized to the storage file, subsequent storage, transmission and sharing can be facilitated.

[0061] Step S302: Convert various types of information contained in the received FPGA system information into corresponding data structures and store them in a preset storage file. The system information may include: architecture information, constraint information, packaging information, and submodule information; the preset storage file is located in the project file.

[0062] Step S303: Instantiate one or more submodules in the current netlist integration project. This step S330 may include: determining the instantiation position of each submodule according to the design layout specified by the architecture information; parsing batch preset instantiation expressions through the netlist integration system, and performing batch instantiation using the preset expressions in units of submodules.

[0063] Step S304: Check the uniqueness of the global instance name. If the uniqueness check fails (i.e. any instance name is not unique), return to step S303 to re-instantiate the submodule; if the uniqueness check succeeds (i.e. all instance names pass the uniqueness check), the submodule and instance information in the submodule are displayed in the navigation bar on the left side of the netlist integration system.

[0064] Exemplarily, each submodule includes one or more instances, each instance includes one or more ports, and each port includes a port name, a port type, connection line information, and connection status information.

[0065] Exemplarily, the display interface can refer to Figure 2 .like Figure 2 As shown in the figure, the left navigation bar displays multiple submodules, each of which includes multiple instances. When you click an instance, the ports in the instance and port-related information can be displayed.

[0066] It should be noted that after step S304, only the port name and port type of the port can be obtained according to the submodule information, while the connection line information and connection status information are empty and need to be determined in subsequent steps.

[0067] Step S305: for each port, determine the connection line information of the current port according to the imported preset port connection rule; wherein the pre-connection rule is a port connection rule pre-defined for the submodule, and the preset port connection rule is manually formulated or generated according to a historical connection scheme.

[0068] After step S305, the connection line information of the ports with clear signal connection requirements is confirmed. After the connection line information of these ports is determined, the connection line information of each port can be displayed on the Figure 2 In the graphical interface shown.

[0069] Step S306: Check the connection status of all ports, and after the check is completed, classify the connections of the ports according to preset connection status categories to obtain connection status information of the ports.

[0070] Exemplarily, this step may include: classifying the ports according to preset connection status categories and connection line information of the ports to obtain classification results, wherein the preset connection status categories may include "power supply", "multi-drive", "no drive", "no load", "hanging", and "bus"; and using the classification results as the connection status information of the current port.

[0071] After step S306, the connection status information of each port is obtained, and then the connection status information of each port can be displayed on Figure 2 In the graphical interface shown.

[0072] Step S307: Generate a connection report according to one or more instances contained in the submodule, one or more ports contained in each instance and port information of each port; the port information includes port name, port type, connection line information and connection status information.

[0073] Step S308: Determine whether there is a pre-connection requirement. If there is a pre-connection requirement, based on the current connection status, automatically search for qualified resources and perform batch pre-connections according to the set constraints, and generate a pre-connection file based on the final connection solution; wherein the format of the generated pre-connection file is the same as the format of the preset port connection rule.

[0074] The "pre-connection" in step S308 is to find and connect according to the condition of port type. For example, assuming that in the existing project design, there are three types of submodule ports: A, B, and C. The connection of type A ports needs to be determined by the "preset port connection rules", and the remaining type B and type C ports can be "pre-connected" by the tool.

[0075] It should be noted that in the same project design, when connecting again in the future, the connection will be made according to the "preset port connection rules" first; then if a "pre-connection file" exists, the connection will be made according to the "pre-connection file".

[0076] In step S308, after the pre-connection is completed, the resource connection that is more dependent on the physical location is realized, but the present application does not limit this, and the resource connection that is more dependent on the physical location can also be realized by setting the corresponding preset port connection rules.

[0077] Through the pre-connection function in step S308, a connection solution that meets the constraint conditions can be found and implemented according to the current connection status; then the engineer can make manual adjustments based on this solution, saving the time of manually generating connection solutions and improving the efficiency of top-level netlist integration.

[0078] Step S309: receiving the input manual inspection result: when the manual inspection result is passed, confirming that it is in line with expectations; when the manual inspection result is not passed, re-executing steps S305 to S307 to adjust the connection.

[0079] Exemplarily, the manual inspection result may be that after manually inspecting the pre-connection file generated in step S308 and the connection report generated in step S307, the input is passed if there is no problem, and is not passed if there is a problem.

[0080] Step S310: When receiving the instruction to update the instance list, jump back to step S303 to add, delete, or modify instances.

[0081] For example, you can select Figure 2 Right-click any instance shown in the navigation bar to delete or modify it; you can also select a module and right-click to add an instance to the module.

[0082] Step S311: upon receiving a system update instruction or a submodule update instruction, jump back to step S302.

[0083] Exemplarily, the user can right-click on a submodule to reload or delete the selected module. For example, when the user deletes a submodule, the process will jump back to step S302.

[0084] For example, Figure 2 As shown, when the user selects Figure 2 Right-click any sub-module in the navigation bar on the left side of the graphical operation interface and select Reload to generate an update sub-module instruction to reload the sub-module.

[0085] Step S312: Generate a top-level netlist according to the configuration information of the top-level netlist determined in the above steps, including: generating a complete top-level netlist when no submodule is selected; generating a top-level netlist of the selected module for the selected submodule when some submodules are selected; and generating a top-level netlist of the selected instance for the selected instance when some instances are selected.

[0086] Exemplarily, when a netlist of a part of a submodule or a part of an instance is selected for generation, the netlist integration system supports performing a connection check for the current netlist generation operation and generating a corresponding connection report (ie, a connection report for the part of the content).

[0087] In an example of this embodiment, before step S312, the following may be included: saving the project. Saving the project means saving all information required to generate the top-level netlist, including: architecture information, constraint information, encapsulation information, submodule information, the relationship between the submodule and the instance generated after instantiation, and the port name, port type, connection line information, and connection status information of each port.

[0088] In an example of this embodiment, Figure 2 As shown, this embodiment provides a user-friendly graphical operation interface, which is clear and concise, with clear data at a glance and simple operation. It can give users clearer and more intuitive feedback and avoid human-induced errors to a large extent.

[0089] In summary, the top-level netlist integration method of this embodiment has the following advantages: Improve integration efficiency: Automated integration reduces manual intervention, speeds up the formation of the top-level netlist, shortens the design cycle, and can also provide certain information support for simulation verification and software tools; Improve design quality: From the top-level perspective, optimize resource allocation, make full use of resources, give full play to performance, so that the final generated netlist can run more efficiently on the FPGA; Enhance flexibility and adaptability: It can flexibly adjust the architecture parameters according to different design requirements to adapt to FPGA designs of various sizes and complexities. Provide a friendly interface: The interface is clear and concise, the data is clear at a glance, and human-induced errors are avoided to a large extent.

[0090] An embodiment of the present application provides an FPGA top-level netlist integration system, such as Figure 4 As shown, it includes: a memory and a processor; The memory is used to store a program for performing FPGA top-level netlist integration; The processor is used to read the program for performing FPGA top-level netlist integration and execute the FPGA top-level netlist integration method as described in any embodiment of the present application.

[0091] An embodiment of the present application provides an FPGA top-level netlist integration tool (also referred to as an FPGA top-level netlist integration tool), such as Figure 5 As shown, it includes: engineering module, input module, control module, integration module, inspection module and output module; The engineering module is used to implement the saving and reproducing operations of the current integration state, so that the top-level netlist integration tool supports data archiving or multi-person collaboration; The input module is used to receive system information, and the system information may include architecture information, constraint information, packaging information, submodule information, etc.; The control module is used to load information and perform operations such as batch adding, deleting, renaming, and reloading of FPGA submodules and instances; illustratively, it can be used to receive update connection instructions, update instance list instructions, update system instructions, and update submodule instructions; The integration module is used to realize automatic top-level netlist integration. It can analyze and integrate the input information through algorithms to ensure that the connections between various sub-modules are correct and meet the design requirements. For some ports that meet the conditions, it can automatically find qualified resources according to the settings and pre-connect them in batches. From a global perspective, it provides a reasonable connection plan, which significantly reduces the number of modification iterations. The checking module is used to check the uniqueness of the global instance name; check the connection details and driver status of the port; and generate a connection report; The output module is used to output the integrated top-level netlist or custom netlist, connection report and other files.

[0092] In summary, this application implements a solution for efficient integration of FPGA top-level netlists, which can quickly generate top-level netlists while ensuring connection accuracy. In addition, this solution supports efficient integration of large-scale, highly complex designs, can be dynamically expanded to meet the needs of designs of different scales, and can ensure efficient resource utilization and integration stability when facing large-scale system designs. Through this new solution, more powerful and flexible support can be provided for FPGA design, thereby promoting innovation and development of electronic system design.

[0093] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As is known to those skilled in the art, the term "computer storage medium" includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0094] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0095] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A FPGA top-level netlist integration method, characterized in that: include: Instantiate the submodule to obtain one or more instances contained in the submodule, one or more ports contained in each instance, and the port name and port type of each port; For each port, the connection line information of the current port is determined according to a preset port connection rule; wherein the preset port connection rule is manually formulated or generated according to a historical connection scheme; Classify according to preset connection status categories to obtain connection status information of the port; A connection report is generated according to one or more instances contained in the submodule, one or more ports contained in each instance and port information of each port; the port information includes port name, port type, connection line information and connection status information.

2. The top-level netlist integration method according to claim 1, characterized in that: After determining the connection line information of the current port according to the preset port connection rule for each port, the method further includes: After receiving the pre-connection instruction, the connected resources are determined according to the current connection status information of each port and the set constraint information, and batch pre-connection is performed; the resources include: opposite end port and connection line information; Generate a pre-connection file according to the connection plan after the pre-connection is completed.

3. The top-level netlist integration method according to claim 1, characterized in that: The preset port connection rules include one or more; each of the preset port connection rules includes a port name part and a connection name part, the port name part is used to determine the port corresponding to the preset port connection rule, and the connection name part is used to determine the connection line information of the port corresponding to the preset port connection rule; Determining the connection line information of the current port according to the preset port connection rule includes: traversing each port, and determining the preset port connection rule corresponding to the current port according to the port name of the current port and the instance where the port is located; The connection line information of the current port is determined according to the corresponding preset port connection rule.

4. The top-level netlist integration method according to claim 3, characterized in that: The port name part includes a port designation field and an instance designation field, wherein the port designation field is used to confirm the port range to which the preset port connection rule is applicable, and the instance designation field is used to confirm the instance range to which the preset port connection rule is applicable; Determining the preset port connection rule corresponding to the current port according to the port name of the current port and the instance where the port is located includes: confirming the preset port connection rule corresponding to the current port according to the port name of the current port, the instance where the current port is located, the port range to which the preset port connection rule applies, and the instance range to which the preset port connection rule applies.

5. The top-level netlist integration method according to claim 3, characterized in that: The connection name part includes a variable field and a captured value field, wherein the captured value field includes one or more captured values; the variable field is used to represent the hardware configuration information corresponding to the instance generated by the current preset port connection rule, wherein the hardware configuration information includes location information, group number information and clock domain information; The captured value field is used to confirm the opposite port to which the current port is connected, wherein each captured value corresponds to one opposite port; The determining the connection line information of the current port according to the corresponding preset port connection rule includes: determining the connection line information of the current port according to the hardware configuration information and the connection port corresponding to the current port.

6. The top-level netlist integration method according to claim 1, characterized in that: The preset connection status categories include "power", "multi-drive", "no drive", "no load", "suspended", and "bus"; The classifying according to the preset connection status category to obtain the connection status information of the port includes: Classify according to the preset connection status category and the connection line information of the port to obtain a classification result; The classification result is used as the connection status information of the current port.

7. The top-level netlist integration method according to claim 1, characterized in that: After the submodule is instantiated, the following is further included: Perform a uniqueness check on the global instance name. When the uniqueness check fails, prompt the instance with the conflicting instance name and re-instantiate the submodule where the instance is located after receiving the user's modification information on the instance.

8. The top-level netlist integration method according to claim 1, characterized in that: Before instantiating the submodule, the method further includes: converting various types of information contained in the received FPGA system information into corresponding data structures and storing them in a preset storage file; the system information includes the following types of information: architecture information, constraint information, packaging information, and submodule information; The instantiation of the submodules includes: determining the instantiation position of each instance according to the design layout specified by the architecture information; determining the port name and port type of each port according to the submodule information; Before classifying the connection of the port according to the preset connection status category and obtaining the connection status information of the port, the method further includes: checking the connection status of all ports according to the constraint information and the encapsulation information.

9. The top-level netlist integration method according to claim 1, characterized in that: After generating the connection report, the method further includes: Upon receiving the connection update instruction, determining the changed port and the latest connection line information corresponding to the port, and updating the connection line information corresponding to the port to the latest connection line information; When receiving an instruction to update the instance list, determining the changed instance, and re-instantiating the submodule where the changed instance is located; Upon receiving the system update instruction, determining the changed system information, and updating the changed system information; the system information includes the following types of information: architecture information, constraint information, packaging information, and submodule information; When the submodule update instruction is received, the changed submodule information is determined, and the changed submodule information is updated.

10. An FPGA top-level netlist integration system, comprising: A memory and a processor, characterized in that: The memory is used to store a program for performing FPGA top-level netlist integration; The processor is used to read the program for performing FPGA top-level netlist integration and execute the FPGA top-level netlist integration method as described in any one of claims 1 to 9.

Images