Method for evaluating interconnection switch block layout success rate in FPGA layout and wiring process and layout optimization method based on evaluation result

Abstract

The invention relates to the field of integrated circuits, and discloses a method for evaluating the distribution success rate of an interconnection switch block (RSB) in a field programmable gate array (FPGA) distribution and wiring process. According to the method, driving end nodes and drain end nodes of the RSB are analyzed, the drain end nodes needing to be connected are counted in combination with a layout result, a connectable path is found, and the connectable success rate of the RSB is calculated. The invention also discloses a layout optimization method based on the evaluation result, and the method comprises the steps: calculating the layout success rate of each RSB, and carrying out the re-layout of an area where the RSBs lower than a threshold value are located, till the layout rate meets the requirements. According to the method, the resource usage amount and the distribution success rate of the RSB can be accurately and quantitatively evaluated, the distribution rate is evaluated by taking the RSB as a unit before wiring to guide layout adjustment, the internal wiring difficulty of the RSB is reduced, congestion is reduced, the wiring convergence speed is increased, and the FPGA design efficiency and reliability are improved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design automation, and in particular to an FPGA layout optimization method based on routing success rate. Background Art

[0002] FPGA (Field Programmable Gate Array) is widely used in the field of digital circuit design due to its flexible and programmable characteristics. The design process of FPGA mainly includes design reading, synthesis mapping, layout and routing, etc. Among them, layout and routing is one of the most critical steps in the entire design process, which directly affects the performance and feasibility of the design.

[0003] In the FPGA layout and routing process, the routing process needs to interconnect switch blocks (RSB, Routing SwitchBox) to achieve signal connections between logic units. RSB contains a large number of programmable switch nodes, which are responsible for connecting signals from the input end (Driver) to the output end (Sink). The traditional routing method is to eliminate congestion by multiple iterations of wire removal and rerouting after the layout is completed, using the wire net as the basic unit to achieve the final routing.

[0004] However, this traditional routing method has several significant problems: First, due to the lack of pre-evaluation of RSB routing capabilities, when the routing density is high, the routing difficulty within a single RSB may be very high, and multiple routing iterations are required to find a feasible solution, and sometimes even no feasible routing solution can be found. Second, frequent routing iterations not only increase design time, but also consume a lot of computing resources. Finally, when routing fails, designers often need to return to the layout stage and start over. This trial-and-error method seriously affects design efficiency.

[0005] For example, after a layout scheme is determined, some RSBs may need to handle too many signal connections. In this case, even if a lot of time is invested in routing iterations, it may not be possible to find a suitable routing scheme within the RSB. What's worse is that traditional methods cannot predict the occurrence of this situation before routing, and the problem can only be discovered after routing fails.

[0006] In addition, the existing technology has a fundamental problem: the separation of the two stages of layout and routing. The layout stage mainly considers the placement of logic cells without fully considering the feasibility of subsequent routing; the routing stage passively accepts the layout results and can only solve the problem through repeated attempts when routing is difficult. This separation leads to inefficiency in the design process, especially in large-scale or highly complex FPGA designs, where the problem is more prominent.

[0007] Therefore, the FPGA design process urgently needs a method that can evaluate the routing difficulty before routing and guide layout optimization accordingly. This method should be able to: accurately evaluate the routing capability of RSB; discover potential routing bottlenecks early; effectively guide layout optimization to improve the routing success rate; and reduce unnecessary routing iterations. Only by solving these problems can the efficiency and reliability of the FPGA design process be truly improved. Summary of the invention

[0008] The purpose of this application is to provide a method for evaluating the success rate of interconnect switch blocks in the FPGA layout and routing process and a layout optimization method based on the evaluation results to solve the problems raised in the above background technology.

[0009] The present application discloses a method for evaluating the success rate of interconnect switch blocks in an FPGA layout and routing process, comprising the following steps:

[0010] Analyze the interconnection switch blocks in the FPGA, record the set of drain end nodes to which each driver end node can be connected and the switch nodes that need to be passed from the driver end node to the drain end node, and count the total number of driver end nodes in the interconnection switch blocks;

[0011] Based on the layout result, counting the set of drain nodes that need to be connected in the interconnect switch block;

[0012] Selecting one drain node from the set of drain nodes that need to be connected as the node to be analyzed, finding a driver node that can be connected to the node to be analyzed, and checking whether the switch node from the driver node to the node to be analyzed is occupied;

[0013] If all the switch nodes that need to be passed from the driver node to the node to be analyzed are not occupied, the count of the routable path is increased by 1, and all the switch nodes passed by the path are marked as occupied; wherein, for each group of driver node and drain node combination, only one routable path is counted, and the situation where multiple paths occupy the same switch node is excluded;

[0014] Determine whether all driver-end nodes and the drain-end nodes that need to be connected have been traversed. If so, calculate the routable success rate of the interconnected switch block, which is equal to the minimum value of the routable path count and the total number of driver-end nodes divided by the total number of driver-end nodes and multiplied by 100; if not, return to execute the above-mentioned step of finding a routable path until the traversal is completed.

[0015] In a preferred example, the driving end node is used to receive an external signal into the interconnection switch block, and the drain end node is used to output the signal to an input port of a programmable function block or an input port of other logic units outside the interconnection switch block.

[0016] In a preferred embodiment, based on the layout result, the step of counting the set of drain nodes that need to be connected in the interconnect switch block includes:

[0017] Get the input pins of each programmable logic block under the current layout result;

[0018] The input pins are integrated to determine the drain node located inside each interconnected switch block and to be connected by the driving node.

[0019] In a preferred example, if all switch nodes that need to be passed from the driver end node to the node to be analyzed are not occupied, the count of the routable path is increased by 1, and all switch nodes passed by the path are marked as occupied; wherein, for each group of driver end nodes and drain end nodes, only one routable path is counted, and the case where multiple paths occupy the same switch node is excluded.

[0020] For multiple optional paths from the driver node to the node to be analyzed, if any two of the paths share the same switch node, only one of the paths is selected to be counted in the routable path count.

[0021] In a preferred example, after calculating the routable success rate of the interconnected switch blocks, the method further includes:

[0022] Comparing the routable success rate of the interconnected switch blocks with a preset threshold;

[0023] When the routable success rate is lower than the preset threshold, a warning message including the interconnection switch block position information and the routable success rate value is output, and the layout and signal connection of the interconnection switch block area are optimized in a targeted manner.

[0024] Return to the above step of finding a routable path until the routable success rate of the interconnect switch block is higher than a preset threshold or the upper limit of the number of layout iterations is reached.

[0025] The present application also discloses a layout optimization method based on the evaluation result, comprising the following steps:

[0026] After performing the initial layout, the method described above is used to calculate the success rate of each interconnected switch block in the FPGA;

[0027] Checking whether the routable success rates of all interconnected switch blocks in the FPGA are higher than a preset routable success rate threshold;

[0028] If there is an interconnection switch block whose success rate of routing is lower than the routing rate threshold, a layout adjustment area centered on the interconnection switch block is determined, and the logic units in the layout adjustment area are re-layouted under the premise of keeping the layout of other areas unchanged, until the success rate of routing of the interconnection switch block is increased to above the routing rate threshold or the current number of layout adjustments reaches a preset upper limit;

[0029] Determine whether there are still interconnection switch blocks in the FPGA whose routing success rate is lower than the routing success rate threshold and the total number of layout adjustments has not reached the preset upper limit. If so, return to execute the checking step; if not, determine the final layout result and enter the routing process;

[0030] A routing operation is performed using the final layout result.

[0031] In a preferred embodiment, after performing the initial layout, the step of calculating the routable success rate of each interconnected switch block in the FPGA using the method described above includes:

[0032] Obtain information about driver-end nodes and drain-end nodes that need to be connected in each interconnected switch block under the initial layout;

[0033] The method described above is called to calculate the routable success rate of each interconnected switch block under the current layout.

[0034] In a preferred example, in the step of checking whether the routable success rates of all interconnected switch blocks in the FPGA are higher than a preset routable success rate threshold, the routable success rate threshold is determined according to the specific model and design requirements of the FPGA.

[0035] In a preferred example, when the layout iterations reach a maximum number or the routing success rates of all interconnected switch blocks are higher than a routing success rate threshold, the final layout result is determined and the routing process is entered.

[0036] The present application provides a method for evaluating the success rate of interconnection switch blocks in the FPGA layout and routing process and a layout optimization method based on the evaluation method. By evaluating the success rate of interconnection switch blocks before routing and guiding layout optimization, the technical problems of difficult and time-consuming routing and even inability to complete routing in the prior art are effectively solved.

[0037] Specifically, this application analyzes the connection relationship between the driver-end node and the drain-end node inside the interconnection switch block, and combines the current layout results to quantitatively evaluate the routing success rate of the interconnection switch block by using the ratio of the routing path count to the total number of driver-end nodes. This evaluation method takes into account the internal structural characteristics and actual layout requirements of the interconnection switch block, and can accurately reflect the resource utilization and routing difficulty of the interconnection switch block under the current layout.

[0038] On this basis, this application proposes a layout optimization method based on the success rate of interconnection switch blocks. This method timely identifies areas with low success rates by real-time evaluation and monitoring of the success rate of each interconnection switch block, and makes targeted layout adjustments. This layout optimization strategy guided by the success rate of interconnection switch blocks can foresee and eliminate potential wiring bottlenecks before wiring, significantly reducing the difficulty of wiring.

[0039] The implementation of the method of the present application can bring the following technical effects: first, by early discovering and optimizing interconnect switch blocks with low routing success rates, congestion in the routing process is reduced and the routing success rate is significantly improved; second, by reducing the number of routing iterations and avoiding unnecessary routing attempts, the routing time is greatly reduced and the overall efficiency of the FPGA design process is improved; finally, the method of the present application improves the routing success rate by optimizing the layout, avoiding the inefficient method of repeated routing attempts in traditional methods, and reducing the consumption of computing resources.

[0040] In addition, the method of this application has strong adaptability and scalability. By adjusting the routing rate threshold and layout adjustment strategy, the method can adapt to the design requirements of FPGAs of different scales and complexities. At the same time, the method also provides a basis for the subsequent development of more complex layout optimization algorithms, which has important theoretical significance and practical value.

[0041] In general, the method provided by this application can effectively improve the quality and efficiency of the layout and routing process in the FPGA design process, and has significant technical effects and practical value. This innovative layout and routing method is of great significance to improving the performance and reliability of FPGA design tools.

[0042] A large number of technical features are recorded in the specification of this application, which are distributed in various technical solutions. If all possible combinations of technical features of this application (i.e., technical solutions) are to be listed, the specification will be too long. In order to avoid this problem, the various technical features disclosed in the above-mentioned invention content of this application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions are all deemed to have been recorded in this specification), unless the combination of such technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed, and features C and D are equivalent technical means that play the same role. Technically, only one can be used, and it is impossible to use them at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be deemed to have been recorded because it is technically infeasible, and the solution of A+B+C+E should be deemed to have been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A typical RSB internal wiring schematic is shown.

[0044] Figure 2 A flow chart of a method for evaluating the success rate of interconnect switch blocks in an FPGA layout and routing process according to a first embodiment of the present application is shown.

[0045] Figure 3 A flow chart of a layout optimization method based on the evaluation result according to the second embodiment of the present application is shown.

[0046] Figure 4 A schematic flow chart of a method for evaluating the success rate of interconnect switch blocks in an FPGA layout and routing process according to a first embodiment of the present application is shown.

[0047] Figure 5 A schematic flow chart of a layout optimization method based on the evaluation result according to the second embodiment of the present application is shown. DETAILED DESCRIPTION

[0048] In the following description, many technical details are provided to help readers better understand the present application. However, those skilled in the art can understand that the technical solution claimed in the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0049] Description of some concepts:

[0050] FPGA (Field Programmable Gate Array): Field programmable gate array, a programmable logic device that implements user-defined digital circuit functions by configuring internal programmable logic units and interconnection resources.

[0051] Placement: In the FPGA design process, the process of mapping the synthesized logic units to the physical resources inside the device and determining the specific location of each logic unit. The goal of placement is to minimize the length and congestion of interconnect lines while meeting timing constraints and resource limitations.

[0052] Routing: After completing the layout, the process of establishing the actual physical circuit based on the connection relationship between the logic units using the interconnection resources inside the FPGA (such as interconnection lines, cross switches, etc.). The task of routing is to complete the routing of all connections under limited routing resources and optimize the circuit's timing performance, power consumption and other indicators.

[0053] Interconnection switch block: A key module used to implement programmable interconnection within the FPGA, which usually contains a large number of configurable switch units to control the transmission and forwarding of signals between different lines. The topology and routing strategy of the interconnection switch block directly affect the routing efficiency and circuit performance of the FPGA.

[0054] Routability: reflects the probability that the interconnect switch block can successfully complete all internal connection routing under given layout conditions. The higher the Routability, the lower the routing difficulty of the interconnect switch block under the current layout, and the greater the possibility of routing completion. This application uses the ratio of the number of routable paths to the number of driver-end nodes to quantitatively evaluate the Routability.

[0055] Driver Pin: A node located on the input side of an interconnect switch block, responsible for introducing external signals into the switch block and serving as the starting point for internal connection lines. The number and distribution of driver pins affect the wiring capacity of the interconnect switch block.

[0056] Sink Pin: A node located on the output side of an interconnect switch block, responsible for leading the signal of the internal circuit to the input pin of other logic units. The number and location of the sink node determine the wiring requirements of the internal circuit of the interconnect switch block.

[0057] PFB (Programmable Function Block): Programmable function block, which is the basic module of the internal logic unit of FPGA. Various complex logic functions can be realized by programming and combining PFB. PFB usually includes programmable elements such as lookup table (LUT), flip-flop (FF), multiplier, etc.

[0058] EDA (Electronic Design Automation): Electronic design automation is a technology that uses computer software tools to automate all aspects of electronic circuit design (such as design entry, synthesis, simulation, layout and routing, etc.). EDA tools have greatly improved the efficiency and reliability of modern electronic system design.

[0059] The following is a brief description of some of the innovative features of this application:

[0060] Aiming at the technical problems of RSB routing difficulty and low efficiency in FPGA design, the inventor of this application has proposed an innovative solution after in-depth research. The core idea of ​​this solution is to introduce RSB routing rate evaluation mechanism into the FPGA layout and routing process, and use the evaluation results (evaluation of local interconnect resource usage) to guide layout optimization, thereby reducing RSB routing difficulty from the source.

[0061] The overall technical solution of this application can be divided into three main links: First, in the layout stage, the resource usage and routing rate of each RSB are evaluated in combination with the current layout results and the connection structure characteristics of the RSB. This evaluation process comprehensively considers the number of Sink ports that the RSB needs to connect to in the layout results, as well as the number of available paths from the Driver to the Sink inside the RSB, and can accurately reflect the routing difficulty of the RSB. Secondly, the routing rate of the RSB is used as a key indicator to measure the quality of the layout. By setting a reasonable routing rate threshold, the RSB with a low routing rate and a high routing difficulty is promptly identified. Finally, the position information of the RSB whose routing rate does not meet the standard is fed back to the layout tool to guide it to focus on optimizing the placement of units in these areas in subsequent layout iterations, thereby improving the overall routing rate. Through multiple rounds of layout iterative optimization, a layout scheme with good routing performance can be finally obtained, creating favorable conditions for subsequent routing.

[0062] This application has significant advantages in technical effects: by introducing the RSB routing rate pre-evaluation mechanism in the layout stage, potential routing difficulties can be discovered in advance, effectively reducing the uncertainty in the routing stage. At the same time, driving layout optimization with the RSB routing rate indicator can minimize connection conflicts and congestion within the RSB, fundamentally reducing the difficulty of routing. This optimization mechanism significantly improves the convergence speed and success rate of the routing process, effectively shortens the routing time, and speeds up the design progress. Especially for large-scale FPGA designs with dense RSB connections, the effect of this solution is more significant, which can greatly improve design efficiency and reduce design iteration costs.

[0063] From the perspective of technological innovation, this application provides a new approach to solving RSB wiring problems, enriching and developing FPGA layout and routing technology. This solution achieves collaborative optimization of the layout and routing process by establishing a linkage mechanism between the layout and routing stages. It not only solves the pain point of RSB wiring difficulty, but also achieves significant technical results in improving wiring quality and efficiency, shortening the design cycle, etc., and has important practical significance for promoting the advancement of FPGA design technology.

[0064] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0065] First of all Figure 1 Provide explanation. Figure 1 A typical RSB internal wiring diagram is shown. In RSB, the switch node used to receive external signals is called Driver, and the switch node used to output signals to external logic modules is called Sink (these external logic modules are usually the input ports of PFB or the input ports of other logic units). The signal transmission path from Driver to Sink usually needs to pass through multiple internal switch nodes. In a specific FPGA chip, the switch nodes available for RSB are fixed, and the connection between Driver and Sink can be achieved by selectively opening different switch nodes. It should be noted that each switch node can only be used once by one connection path.

[0066] After the design file is read in and converted into the internal logic unit of the FPGA chip through comprehensive mapping, it enters the layout process. At this stage, the dedicated EDA software needs to assign each logic unit to the appropriate physical location, such as placing it in the physical unit position inside the PFB. Through this layout process, it can be determined which Sink nodes are needed in each RSB to connect to the logic unit of the PFB.

[0067] When entering the routing process, the dedicated EDA software will build a signal transmission path through multiple programmable switches (this process usually needs to cross multiple RSBs). Especially when processing the RSB where the signal is finally input to the logic unit, the EDA software needs to try to establish a driver-to-sink connection inside the RSB. If there are a large number of sinks that need to be connected, and there are relatively few available driver-to-sink connection paths, the internal routing difficulty of the RSB will increase significantly, resulting in difficulty in routing convergence.

[0068] Based on the above considerations, this method proposes a solution to evaluate the RSB routing success rate in the layout and routing process. This solution evaluates the RSB routing success rate under a specific layout result by analyzing the Sink conditions that need to be connected inside the RSB in the layout result and combining the connection characteristics of the RSB itself. This evaluation result can be used to guide the layout iteration adjustment, thereby reducing the routing difficulty of the RSB and accelerating the convergence speed of the routing.

[0069] The first embodiment of the present application relates to a method for evaluating the success rate of interconnect switch blocks in the FPGA layout and routing process, and the process is as follows: Figure 2 and Figure 4 As shown, the method comprises the following steps:

[0070] S100: Analyze the interconnection switch blocks in the FPGA, record the set of drain nodes to which each driver node can be connected and the switch nodes that need to be passed from the driver node to the drain node, and count the total number of driver nodes in the interconnection switch blocks.

[0071] S200: Based on the layout result, counting the set of drain nodes that need to be connected in the interconnection switch block.

[0072] S300: selecting a drain node from the set of drain nodes to be connected as a node to be analyzed, searching for a driver node that can be connected to the node to be analyzed, and checking whether a switch node from the driver node to the node to be analyzed is occupied.

[0073] S400: If all switch nodes that need to be passed from the driver end node to the node to be analyzed are not occupied, the count of the routable path is increased by 1, and all switch nodes passed by the path are marked as occupied; wherein, for each group of driver end nodes and drain end nodes, only one routable path is counted, and the situation where multiple paths occupy the same switch node is excluded.

[0074] S500: Determine whether all driver-end nodes and the drain-end nodes that need to be connected have been traversed. If so, calculate the routable success rate of the interconnected switch block, which is equal to the minimum value of the routable path count and the total number of driver-end nodes divided by the total number of driver-end nodes and multiplied by 100; if not, return to execute the above-mentioned step of finding a routable path until the traversal is completed.

[0075] Optionally, for S100, the driving end node is used to receive an external signal into the interconnection switch block, and the drain end node is used to output the signal to an input port of a programmable function block or an input port of other logic units outside the interconnection switch block.

[0076] Optionally, for S200, the step of counting a set of drain nodes that need to be connected in the interconnection switch block includes:

[0077] Get the input pins of each programmable logic block under the current layout result;

[0078] The input pins are integrated to determine the drain node located inside each interconnected switch block and to be connected by the driving node.

[0079] Optionally, for S400, for multiple optional paths from the driver node to the node to be analyzed, if any two of these paths share the same switch node, only one of the paths is selected to be included in the count of routable paths.

[0080] Optionally, for S500, after calculating the routable success rate of the interconnected switch blocks, the method further includes:

[0081] Comparing the routable success rate of the interconnected switch blocks with a preset threshold;

[0082] When the routable success rate is lower than the preset threshold, a warning message including the interconnection switch block position information and the routable success rate value is output, and the layout and signal connection of the interconnection switch block area are optimized in a targeted manner.

[0083] Return to the above step of finding a routable path until the routable success rate of the interconnect switch block is higher than a preset threshold or the upper limit of the number of layout iterations is reached.

[0084] Specifically, the purpose of S100 is to comprehensively analyze the internal connection structure characteristics of the RSB to provide a basis for subsequent routing rate evaluation and optimization. By deeply analyzing the internal topology of the RSB, the following key information can be obtained: 1) Which drain nodes each driver node can be connected to. This determines the routing capability and flexibility of each driver. 2) The switch nodes that need to be passed from a specific driver to the target drain. The number and distribution of switch nodes will affect the difficulty of routing. 3) The total number of driver nodes inside the RSB. This total number is a key parameter when evaluating routing rate.

[0085] By collecting this information, RSB can be characterized and quantified from the perspective of local resource usage. This analysis method based on the internal structure of RSB can accurately evaluate the resource utilization and potential routing difficulty of RSB under the current layout. Compared with the traditional overall routing difficulty evaluation method, this localized analysis of the present application can more accurately predict routing bottlenecks and provide a reliable basis for subsequent targeted layout optimization.

[0086] In addition, this step also lays the foundation for the subsequent calculation of the RSB routing success rate. By counting the total number of driver terminals, a key indicator, combined with the number of routing paths counted in the subsequent steps, the RSB routing success rate can be quantitatively evaluated. This makes it possible to identify RSBs with low routing success rates before routing, which helps eliminate potential routing bottlenecks in the layout stage.

[0087] In summary, step S100 deeply evaluates the use of local interconnect resources by analyzing the internal connection characteristics of RSB, which is the key to accurately predict the difficulty of RSB routing. The information obtained in this step will be fully utilized in subsequent steps to guide the optimization of layout, improve the routing success rate, and reduce the routing time.

[0088] The purpose of S200 is to determine the number and distribution of drain nodes that actually need to be connected inside each RSB under the current layout. This information directly reflects the routing requirements and pressure of the RSB. Specifically, the statistical drain node set is mainly implemented through the following two sub-steps: 1) Obtain the input pin distribution of each programmable logic block (PLB) under the current layout. PLB is a logic unit inside the FPGA, and a PLB usually contains multiple PFBs (programmable function blocks). The input pins of the PLB need to be connected through the RSB. 2) Integrate the input pins of the PLB to determine the set of drain nodes that need to be connected inside each RSB. Usually an RSB is responsible for the interconnection resource support of the corresponding PLB.

[0089] Through these two sub-steps, we can get a set of drain nodes in each RSB that is closely related to the layout results. The size of this set directly determines the wiring pressure of the RSB. The more drain nodes there are, the greater the wiring requirements inside the RSB, and the wiring difficulty will increase accordingly.

[0090] The innovation of this step is that it links a key factor affecting the difficulty of wiring, namely the number of drain nodes, with the specific layout scheme. Traditional wiring difficulty assessment methods usually only focus on the overall interconnection resource utilization and ignore the impact of the layout scheme. The method of this application fully considers the actual connection requirements of each RSB under the current layout, making the difficulty assessment closer to the actual situation.

[0091] In addition, this step also provides another key parameter for the subsequent calculation of the routing success rate: the number of drain nodes that need to be connected. In step S400, the statistics of the routable paths are based on this set of drain nodes. Only by fully considering the information of the drain nodes can the routing success rate of RSB be accurately evaluated.

[0092] In general, step S200 accurately describes the routing requirements of each RSB by analyzing the layout results, making the evaluation of routing difficulty more accurate and reliable. This is of great significance for identifying routing bottlenecks, optimizing resource allocation, and improving routing success rate during the layout stage. At the same time, it also reflects a core idea of ​​the present application method, which is to closely combine the usage of local interconnect resources with the overall layout plan to achieve accurate prediction and optimization of routing difficulty.

[0093] S300 is one of the core links in evaluating the routing rate of RSB. It determines whether a specific drain node can be successfully connected under the current conditions by analyzing the wiring resource occupancy inside the RSB. This process can be divided into three main sub-steps: 1) Select a node from the drain set obtained in step S200 as the current analysis object. This node represents a specific routing requirement. 2) Find the driver node that can be routed to the drain node. This process is actually looking for potential routing paths. Based on the information collected in step S100, we know which drains each driver can be connected to. 3) Check whether there are any occupied switch nodes on the potential path from the driver to the drain. If a switch node is already occupied by other connections, the current path is unavailable. Only when all nodes on a path are free, the path is routable.

[0094] It should be pointed out that the purpose of this step is to determine whether a specific driver-to-drain connection is feasible under the current wiring conditions. It comprehensively considers the internal topology of the RSB and the current resource occupancy, and can dynamically reflect the possibility of routing.

[0095] This method of analyzing the routing of drain nodes one by one has higher accuracy and reliability than evaluating the routing difficulty of the entire RSB at one time. It takes into account the dynamic changes in routing requirements and resource usage, making the evaluation results closer to the actual routing process. By accumulating the analysis results of each drain node, the routing rate of the entire RSB can be obtained, thereby accurately predicting the routing difficulty.

[0096] In addition, this step also reflects a key idea of ​​this application, which is to evaluate the overall wiring difficulty by local resource occupancy. Compared with the traditional evaluation method based on overall line length, congestion and other indicators, this localized analysis method of this application is more intuitive and reliable, and can detect local wiring bottlenecks earlier, providing more targeted guidance for optimizing layout.

[0097] In general, step S300 is the key to RSB routing success rate assessment. It accurately determines the utilization efficiency of local interconnection resources by analyzing the routing status of specific drain nodes. This refined analysis makes the prediction of routing difficulty more accurate and provides strong support for eliminating potential bottlenecks in the layout stage. At the same time, this step also demonstrates the core idea of ​​this application, that is, to guide layout optimization through local routing analysis, and ultimately achieve the purpose of improving routing success rate and reducing routing difficulty.

[0098] The purpose of step S500 is to obtain the final routing success rate of RSB. This process can be divided into two main parts: 1) Determine whether the traversal analysis of all driver terminals and drain terminals has been completed. Only when each driver terminal and each drain terminal that needs to be connected has been analyzed in steps S300 and S400, can an accurate routing rate result be obtained. If the traversal has not been completed, it is necessary to return to step S300, select the next drain terminal node to be analyzed, and continue the analysis. 2) If the traversal has been completed, use the previous analysis results to calculate the routing success rate of RSB. The calculation formula for this success rate is: Routing success rate = min (number of routable paths, total number of driver terminal nodes) / total number of driver terminal nodes * 100% Among them, the number of routable paths comes from the statistical results of step S400, and the total number of driver terminal nodes comes from the statistical results of step S100. The reason why the minimum value of the number of routable paths and the total number of driver terminals is selected in the calculation is to ensure the rationality of the success rate. In actual wiring, the number of routable paths cannot exceed the number of driver terminals. Therefore, if the number of routable paths obtained by counting is greater than the total number of driver ends, in fact, at most the total number of driver ends can be connected.

[0099] It should be pointed out that step S500 is a necessary supplement and application of the previous analysis. It completes the final calculation of the routing rate and provides a direct basis for quantitatively evaluating the routing difficulty of RSB. By judging the completion of the traversal, the thoroughness of the analysis is ensured; by reasonably designing the routing rate calculation formula, the accuracy of the evaluation results is ensured.

[0100] S500 provides a quantitative indicator to evaluate the routing performance of RSB. Traditional routing methods often lack consideration of the efficiency of local resource utilization, making it difficult to accurately predict routing difficulty before routing. The routing success rate indicator of this application fully absorbs the analysis results of the previous steps, comprehensively considers the connection characteristics, resource occupancy and actual routing requirements within the RSB, and can accurately reflect the routing capability of the RSB under the current layout.

[0101] In addition, S500 also provides a clear direction for subsequent layout optimization. By calculating the success rate of each RSB, the weak links in the layout, that is, RSBs with low success rates, can be found. In subsequent optimization, the cell layout around these RSBs can be adjusted in a targeted manner to improve their success rates. Since the optimization focuses on the key low-pass rate areas, the success rate of the overall routing can be significantly improved at a small layout adjustment cost.

[0102] In general, S500 intuitively quantifies the routing performance of RSB by calculating the routing success rate, making the evaluation of routing difficulty more accurate and reliable. It not only provides an important basis for layout optimization, but also provides a reliable prediction for the final routing results. The completion of this step indicates that the core evaluation indicators of the method of this application have been established, laying a solid foundation for subsequent layout optimization and routing operations. It reflects an important value of this application, that is, in the early stage of layout and routing, fine-grained resource evaluation is used to drive optimization, thereby maximizing routing efficiency and reducing design costs.

[0103] After step S500, if the evaluation result of the RSB routing success rate is not ideal, the present application also provides an iterative optimization method: compare the RSB routing success rate with a preset threshold value, and if the threshold value is not reached, output a warning message including the RSB position and routing success rate value, and perform targeted optimization of the layout and connection of the area around the RSB; then return to step S300 and re-execute subsequent analysis until the RSB routing success rate meets the requirements or the upper limit of the number of layout iterations is reached.

[0104] This iterative optimization mechanism further enhances the adaptability and practicality of the present application. By setting a routing rate threshold, a clear optimization goal is established in the layout stage. The layout tool can refer to this goal and focus on adjusting the routing bottleneck area. At the same time, the optimization process is gradual and iterative. Each round of optimization is based on the evaluation results of the previous round, and can continuously approach a better solution. Even when the upper limit of the number of layout iterations is reached, the one with the highest routing rate can be selected from the historical solutions as the final solution. This optimization strategy not only improves the routing rate, but also takes into account the optimization efficiency, and has great engineering practical value.

[0105] In summary, the RSB routing rate evaluation method and the layout optimization method based on the evaluation results provided in this embodiment have well solved the problem of routing difficulty prediction and optimization from the perspective of fine-grained analysis and dynamic optimization. By introducing quantitative and calculable routing indicators in the layout stage and establishing a feedback optimization mechanism between layout and routing, the entire routing process is made more intelligent and efficient, and the routing results are more predictable and controllable. This is of great significance for improving FPGA design efficiency and reducing design costs.

[0106] Furthermore, Figure 3 and Figure 5 A layout optimization method based on the evaluation result according to a second embodiment of the present application is shown, comprising the following steps:

[0107] S10: After performing the initial layout, the method described in claim 1 is used to calculate the routable success rate of each interconnected switch block in the FPGA, wherein the position of each interconnected switch block is represented by row coordinates and column coordinates (c, r), and the corresponding routable success rate is recorded as R(c, r).

[0108] S20: Check whether the success rates of all interconnected switch blocks in the FPGA are higher than a preset success rate threshold.

[0109] S30: If there is an interconnect switch block whose success rate of routing is lower than the routing rate threshold, determine a layout adjustment area centered on the interconnect switch block, and re-layout the logic units in the layout adjustment area while keeping the layout of other areas unchanged, until the success rate of routing of the interconnect switch block is increased to above the routing rate threshold or the current number of layout adjustments reaches a preset upper limit.

[0110] S40: Determine whether there are still interconnection switch blocks in the FPGA whose routing success rate is lower than the routing success rate threshold and the total number of layout adjustments has not reached a preset upper limit. If so, return to execute the checking step; if not, determine the final layout result and enter the routing process.

[0111] S50: performing a routing operation using the final layout result.

[0112] Optionally, for S10, the step of calculating the routable success rate of each interconnected switch block after performing the initial layout includes:

[0113] Obtain information about driver-end nodes and drain-end nodes that need to be connected in each interconnected switch block under the initial layout;

[0114] The method of claim 1 is called to calculate the routable success rate of each interconnected switch block under the current layout.

[0115] Optionally, for S20, the routing rate threshold is determined according to a specific model and design requirements of the FPGA.

[0116] Optionally, for S40-S50, when the layout iterations reach a maximum number or the routing success rates of all interconnected switch blocks are higher than a routing success rate threshold, a final layout result is determined and the routing process is entered.

[0117] The above embodiments have the following technical innovations and effects:

[0118] The above embodiments propose several innovative solutions in optimizing the FPGA layout and routing process. The first innovation is to propose a new RSB routing evaluation method, which not only comprehensively considers the drain information inside the RSB in the layout results, but also deeply analyzes the RSB's own characteristics and potential routing paths, and obtains the RSB routing rate through quantitative calculation. The RSB routing rate is creatively used as an evaluation indicator for layout optimization, providing a quantifiable basis for layout optimization.

[0119] The second innovation is the establishment of an effective layout optimization feedback mechanism. The above embodiment can evaluate the difficulty of RSB routing before routing, and adjust the layout strategy in time according to the RSB routing rate, especially focusing on optimizing RSB areas with low routing rates. This method realizes the coordinated optimization of the layout and routing stages, breaking the traditional separation of layout and routing. At the same time, the above embodiment also proposes a layout optimization strategy based on local resource congestion. By evaluating the resource usage in the local area and finding the layout plan with the best resource utilization, the wiring load in the local area is effectively balanced.

[0120] In terms of technical effects, the above embodiments significantly improve the wiring success rate. By accurately evaluating the difficulty of RSB routing, designers can predict and avoid routing bottlenecks in advance, effectively reduce the difficulty of RSB internal routing, and reduce routing congestion. At the same time, the above embodiments greatly improve design efficiency, reduce the number of routing iterations, speed up routing convergence, significantly save computing resource consumption, and effectively reduce design time costs.

[0121] In addition, the above embodiment also significantly enhances the reliability of the design. By optimizing based on quantitative indicators, predictable routing results are provided, effectively avoiding the risk of routing failure and improving the first-time success rate of the design. In general, the above embodiment achieves forward-looking optimization of the layout and routing process by establishing an RSB routing pass rate evaluation mechanism, thereby comprehensively improving the efficiency, reliability and success rate of FPGA design.

[0122] In order to better understand the technical solution of the present application, a specific example is provided below for illustration. The details listed in the example are mainly for ease of understanding and are not intended to limit the scope of protection of the present application.

[0123] like Figure 2 As shown, this example includes the following steps:

[0124] First, analyze the RSB and record the Sink set that each available Driver can connect to and the switch nodes required for the connection. Count the total number of all available Drivers, represented by num_total_drivers. At the same time, count the Sink nodes that need to be connected in the RSB according to the layout results to form the Need_routed_sinks set.

[0125] Next, select a need_routed_sink from the need_routed_sinks collection, find a Driver that can be connected to the need_routed_sink, and check the switch nodes path_nodes required from the Driver to the need_routed_sink. When all path_nodes are not occupied, add 1 to the path count num_path and mark all path_nodes used by the path as occupied.

[0126] Then, check whether the traversal of all potential Drivers and Need_routed_sinks has been completed. If the traversal is completed, the final calculation of RSB routability is performed; if not, continue to execute the above process until the traversal of all Drivers and Need_routed_sinks is completed.

[0127] Finally, the brausability success rate R of RSB was calculated using the following formula:

[0128]

[0129] Among them, num_path represents the total number of valid paths that can be connected to all relevant sinks obtained through the above process. This value has two important characteristics: one is that it excludes the situation where multiple paths occupy the same switch node, and the other is that each group of potential driver and sink node combinations is counted only once. num_total_drivers represents the total number of all available drivers in the RSB. Generally speaking, the larger the num_path, the more paths the RSB has that can be used to connect to the target sink, and the lower the subsequent wiring difficulty. Therefore, we can use this value to quantitatively evaluate the success rate of RSB in subsequent wiring. Using this evaluation result to assist layout iteration can effectively improve the RSB's wiring rate and accelerate the convergence of wiring.

[0130] It should be pointed out that the RSB routing rate evaluation method proposed in the above example can effectively assist the layout iteration process, improve the efficiency and reliability of FPGA design, and reduce the routing difficulty and time cost. Figure 3 A specific implementation method of applying RSB routing yield evaluation results to the placement and routing process is demonstrated.

[0131] The specific steps are as follows:

[0132] After the initial layout is completed, the routability R(c, r) of each RSB in the FPGA is calculated, where c and r represent the row and column coordinates of the RSB, respectively, and R(c, r) represents the routability of the RSB located in the cth row and the rth column.

[0133] The routability of all RSBs is compared with a preset threshold, which can be flexibly adjusted according to the specific chip model and design requirements.

[0134] For RSB areas with a routability lower than the threshold, layout optimization is required: re-execute layout iterations; try to improve the routability of the corresponding RSB; until the routability of all RSBs reaches a high level, or the number of layout iterations reaches a preset upper limit.

[0135] After completing layout optimization, enter the routing process.

[0136] It should be noted that this is only an application example of the RSB routing rate evaluation result. In practical applications, the RSB routing rate index can be paid attention to at each stage of the layout and routing process, and used as an important reference for auxiliary optimization.

[0137] It should be noted that in the application documents of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements. In the application documents of this patent, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, which includes two situations: performing the action only according to the element, and performing the action according to the element and other elements. Expressions such as multiple, multiple, and multiple include 2, 2 times, 2 kinds, and more than 2, more than 2 times, and more than 2 kinds.

[0138] All documents mentioned in this application are considered to be included in the disclosure of this application as a whole, so that they can be used as the basis for modification when necessary. In addition, it should be understood that after reading the above disclosure of this application, those skilled in the art can make various changes or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A method for evaluating the success rate of interconnect switch blocks in an FPGA placement and routing process, characterized in that: The following steps are involved: Analyze the interconnection switch blocks in the FPGA, record the set of drain end nodes to which each driver end node can be connected and the switch nodes that need to be passed from the driver end node to the drain end node, and count the total number of driver end nodes in the interconnection switch blocks; Based on the layout result, counting the set of drain nodes that need to be connected in the interconnect switch block; Selecting one drain node from the set of drain nodes that need to be connected as the node to be analyzed, finding a driver node that can be connected to the node to be analyzed, and checking whether the switch node from the driver node to the node to be analyzed is occupied; If all the switch nodes that need to be passed from the driver node to the node to be analyzed are not occupied, the count of the routable path is increased by 1, and all the switch nodes passed by the path are marked as occupied; wherein, for each group of driver node and drain node combination, only one routable path is counted, and the situation where multiple paths occupy the same switch node is excluded; Determine whether all driver-end nodes and the drain-end nodes that need to be connected have been traversed. If so, calculate the routable success rate of the interconnected switch block, which is equal to the minimum value of the routable path count and the total number of driver-end nodes divided by the total number of driver-end nodes and multiplied by 100; if not, return to execute the above-mentioned step of finding a routable path until the traversal is completed.

2. The method according to claim 1, characterized in that The driving end node is used to receive an external signal into the interconnection switch block, and the drain end node is used to output a signal to an input port of a programmable function block or an input port of another logic unit outside the interconnection switch block.

3. The method according to claim 1, characterized in that Based on the layout result, the step of counting the set of drain nodes that need to be connected in the interconnect switch block includes: Get the input pins of each programmable logic block under the current layout result; The input pins are integrated to determine the drain node located inside each interconnected switch block and to be connected by the driving node.

4. The method according to claim 1, characterized in that If all the switch nodes that need to be passed from the driver end node to the node to be analyzed are not occupied, the count of the routable path is increased by 1, and all the switch nodes passed by the path are marked as occupied; wherein, for each group of driver end nodes and drain end nodes, only one routable path is counted, and the situation where multiple paths occupy the same switch node is excluded, For multiple optional paths from the driver node to the node to be analyzed, if any two of the paths share the same switch node, only one of the paths is selected to be counted in the routable path count.

5. The method according to claim 1, characterized in that After calculating the routable success rate of the interconnected switch blocks, the method further includes: Comparing the routable success rate of the interconnected switch blocks with a preset threshold; When the routable success rate is lower than the preset threshold, outputting a warning message including the interconnection switch block location information and the routable success rate value, and optimizing the layout and signal connection of the interconnection switch block area in a targeted manner; Return to the above step of finding a routable path until the routable success rate of the interconnect switch block is higher than a preset threshold or the upper limit of the number of layout iterations is reached.

6. A layout optimization method based on evaluation results, characterized in that: The following steps are involved: After performing the initial layout, the method according to claim 1 is used to calculate the routable success rate of each interconnected switch block in the FPGA; Checking whether the routable success rates of all interconnected switch blocks in the FPGA are higher than a preset routable success rate threshold; If there is an interconnection switch block whose success rate of routing is lower than the routing rate threshold, a layout adjustment area centered on the interconnection switch block is determined, and the logic units in the layout adjustment area are re-layouted under the premise of keeping the layout of other areas unchanged, until the success rate of routing of the interconnection switch block is increased to above the routing rate threshold or the current number of layout adjustments reaches a preset upper limit; Determine whether there are still interconnection switch blocks in the FPGA whose routing success rate is lower than the routing success rate threshold and the total number of layout adjustments has not reached the preset upper limit. If so, return to execute the checking step; if not, determine the final layout result and enter the routing process; A routing operation is performed using the final layout result.

7. The method according to claim 6, characterized in that After performing the initial layout, the step of calculating the routable success rate of each interconnected switch block in the FPGA using the method of claim 1 comprises: Obtain information about driver-end nodes and drain-end nodes that need to be connected in each interconnected switch block under the initial layout; The method of claim 1 is called to calculate the routable success rate of each interconnected switch block under the current layout.

8. The method according to claim 6, characterized in that In the step of checking whether the routable success rates of all interconnected switch blocks in the FPGA are higher than a preset routable success rate threshold, the routable success rate threshold is determined according to the specific model and design requirements of the FPGA.

9. The method according to claim 6, characterized in that When the layout iterations reach the maximum number or the routing success rates of all interconnected switch blocks are higher than the routing success rate threshold, the final layout result is determined and the routing process begins.

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