Modeling method for layout proximity effect parameters
By establishing a relationship model between device channel length parameters and threshold voltage parameters and mobility parameters, the modeling problem caused by device layout effect in 28nm and below processes is solved, and more accurate modeling of the IV characteristic curve of SOI devices is achieved.
Patent Information
- Application Number
- CN202411877555.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-19
- Publication Date
- 2025-05-16
AI Technical Summary
In processes of 28nm and below, HKMG process devices and FinFET devices have layout effects, resulting in the inability to fully and accurately model.
The threshold voltage is calculated by using the constant current method, and a relationship model is established between the device channel length parameters and the threshold voltage parameters, the device channel length parameters and the device mobility parameters, and fit it through the combination of physical characteristics and mathematical methods.
It realizes more accurate modeling of the IV characteristic curve of SOI device, improves the fitting accuracy of the model, and meets the needs of circuit design engineers.
Smart Images
Figure CN120012686A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuit design, and in particular to a modeling method for layout proximity effect parameters. Background Art
[0002] With the continuous advancement of semiconductor manufacturing technology, the manufacturing process of FDSOI process devices has developed to the nanometer level. The current minimum size has reached 22 nanometers, and the minimum size of the device is still shrinking. In the era of submicron devices, the size of the device is relatively large, and the electrical characteristics of the device are basically only affected by some of its own physical parameters, and have little to do with the devices and environment around it. However, with the advancement of semiconductor manufacturing technology, the size of the device has entered the nanometer stage. On the one hand, the reduction of the size of the device itself will produce some physical effects. On the other hand, in advanced processes, stress enhancement technology is introduced to improve the mobility of device carriers. These technologies will cause the environment around the device to affect the electrical characteristics of the device itself, and as the size of the device increases, the impact of the surrounding environment on the electrical characteristics of the device itself will become greater and greater. Therefore, when establishing a device model, it is necessary to consider the impact of layout effects on the electrical characteristics of the device, so that the fitting accuracy of the model is more accurate, which is very important for circuit design engineers. Summary of the invention
[0003] The technical problem to be solved by the present invention is to provide a more accurate modeling method for 28nm and below processes, in which HKMG process devices and FinFET devices cannot be completely and accurately modeled due to the presence of layout effects.
[0004] In order to solve the above problems, the present invention provides a modeling method for layout proximity effect parameters, including the following steps: calculating the threshold voltage respectively by a constant current method according to test data; establishing a relationship model between device channel length parameters and threshold voltage parameters; establishing a relationship model between device channel length parameters and device mobility parameters.
[0005] Optionally, the step of establishing a relationship model between device channel length parameters and threshold voltage parameters is further to fit the change of threshold voltage with the distance from the gate to the edge of the active area on both sides of the device (SA and SB), channel length L, and channel width W.
[0006] Optionally, the step of establishing a relationship model between device channel length parameters and device mobility parameters is further to fit the device mobility with the distance from the gate to the edge of the active area on both sides of the device (SA and SB), the channel length L, and the channel width W.
[0007] The present invention combines physical characteristics with mathematical methods to fit the IV characteristic curve of the SOI device, which is a more accurate modeling method. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Attached Figure 1 The figure below is a typical schematic diagram of LOD effect.
[0009] Attached Figure 2 Shown is a schematic diagram of the steps of the method described in one specific embodiment of the present invention.
[0010] Attached Figure 3 Shown is a schematic diagram of the main designed parameters in the LOD model described in a specific implementation manner of the present invention.
[0011] Attached Figure 4 Shown is the model fitting of the curve of the threshold voltage of the SOI device changing with the SA size according to a specific embodiment of the present invention.
[0012] Attached Figure 5 Shown is the model fitting of the current input-output characteristic curve of the SOI device with different SA sizes according to a specific embodiment of the present invention. DETAILED DESCRIPTION
[0013] The specific implementation of the layout proximity effect parameter modeling method provided by the present invention is described in detail below with reference to the accompanying drawings.
[0014] In the research of layout effect (LDE), the continuous reduction of device feature size and the introduction of large-scale stress engineering have brought new challenges to the research of layout proximity effect. Among the layout proximity effects, the length of deffusion (LOD) has a more obvious impact on device performance, which refers to the phenomenon that the device electrical parameters change with the length of the diffusion region and the active region. Figure 1 The figure below is a typical schematic diagram of the LOD effect. Research has found that the LOD effect mainly comes from the intentional stress imposed by stress engineering or the unintentional stress caused by certain processes. Through physical analysis, the impact of the layout's adjacent shadows on the device is closely related to the length of the channel. As the channel length increases, the impact of the layout's adjacent shadows blocking the device decreases.
[0015] The model proposed in this specific implementation is mainly a fitting method combining physical characteristics with mathematical methods for the IV characteristic curve of SOI devices. Figure 2 The figure is a schematic diagram of the steps of the method described in this specific embodiment, including: step S10, calculating the threshold voltage according to the test data; step S11, establishing a relationship model between the device channel length parameter and the threshold voltage parameter; step S12, establishing a relationship model between the device channel length parameter and the device mobility parameter.
[0016] Step S10, calculating the threshold voltages respectively using a constant current method according to the test data.
[0017] Step S11, establishing a relationship model between device channel length parameters and threshold voltage parameters.
[0018] Through physical analysis, it is found that the impact of the proximity effect on SOI devices is closely related to the channel length. As the channel size increases, the impact of the proximity effect on the device decreases.
[0019] As attached Figure 3 The figure shows a schematic diagram of the main design parameters in the LOD model. In the LOD, the main parameters involved are the distance from the gate to the edge of the active area on both sides of the device (SA and SB), the channel length L, and the channel width W.
[0020] Since the threshold voltage changes differently under different SA and SB conditions, the threshold voltage related parameters in the BSIMING model are modified to meet the requirements of use under different sizes. The parameter related to threshold voltage in the model manual is: phig1. The threshold voltage drift caused by the STI stress proximity effect (del_phig1_sa) is a function of SA, SB, L, and W. The following SPICE code can be used to implement the above process
[0021]
[0022]
[0023] In the above formula, kphig1_sa is the displacement parameter of phig1 under the layout effect, lkphig1_sa, wkphig1_sa, pkphig1_sa are the fitting parameters of size influencing factors, and the front-gate work function of the device is a function related to SA, SB, L, and W.
[0024] +del_phig1_sa='dphig1_sa*(inv_sa+inv_sb-inv_saref-inv_sbref)*_lodflag'
[0025] del_phig1_sa mainly describes the subthreshold voltage drift caused by layout effects, where _lodflag is 1.
[0026] like Figure 4 The model fitting of the curve showing the threshold voltage of the SOI device changes with SA size.
[0027] Step S12, establishing a relationship model between device channel length parameters and device mobility parameters.
[0028] Because the channel mobility of the device is different under different SA and SB conditions, the threshold voltage related parameters in the BSIMING model are modified to meet the requirements of use under different sizes. The parameters related to the device channel mobility in the model manual are mainly: u0. The mobility change rate (rhouo_eff_sa) caused by the STI stress proximity effect is a function of SA, SB, L, and W. The following SPICE code can be used to implement the above process:
[0029]
[0030] In the above formula, lku0_sa, wku0_sa, and pku0_sa are fitting parameters of the factors affecting size mobility. The mobility of the device is a function related to SA, SB, L, and W.
[0031] The final fitting verification results of the complete model are as follows Figure 5 The figure shows the model fitting of the current input-output characteristic curve of SOI devices with different SA sizes. The dots are measured data and the solid line is the model simulation result. The error is less than 10%, which meets the industry standard.
[0032] This process can be implemented using commercial software such as Agilent's MBP (model builder program), and the simulator can be HSPICE.
[0033] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.
Claims
1. A modeling method for layout proximity effect parameters, characterized in that: The steps include: The threshold voltages are calculated respectively using the constant current method according to the test data; Extract the relationship model between device channel length and threshold voltage fitting parameters; Extract the relationship model between device channel length and device mobility fitting parameters.
2. The method according to claim 1, characterized in that The step of establishing the relationship model between the device channel length parameters and the threshold voltage parameters is further to fit the threshold voltage with the distance from the gate to the edge of the active area on both sides of the device (SA and SB), the channel length L, and the channel width W.
3. The method according to claim 1, characterized in that The step of establishing the relationship model between the device channel length parameter and the device mobility parameter is further to fit the device mobility with the distance from the gate to the edge of the active area on both sides of the device (SA and SB), the channel length L, and the channel width W.