Layout and wiring method and device for integrated circuit layout and electronic equipment

Abstract

The embodiment of the invention discloses a layout and wiring method and device for integrated circuit layout, electronic equipment and a storage medium, relates to the technical field of chip design, and can effectively control voltage drop and guarantee stable power supply of a standard unit. The method comprises the following steps: determining position coordinates and working current of each standard unit in the integrated circuit layout in the integrated circuit layout from a layout and wiring configuration file of the integrated circuit layout; based on the position coordinates of the standard units in the integrated circuit layout in the integrated circuit layout, placing the standard units in the corresponding positions in the integrated circuit layout, and based on the working currents of the standard units in the integrated circuit layout, determining the number of power lines in a power wiring layer in the integrated circuit layout; and based on the number of power lines in a power wiring layer in the integrated circuit layout and a preset distance between adjacent power lines, arranging the power lines in the power wiring layer, and connecting the arranged power lines with each standard unit. The method can be used for layout and wiring of integrated circuit layout.

Description

Technical Field

[0001] The present invention relates to the field of chip design technology, and in particular to a layout and wiring method, device, electronic equipment and storage medium for integrated circuit layout. Background Art

[0002] Integrated circuit automatic layout and routing is a key step in the physical design of integrated circuits. It involves the reasonable placement and connection of billions of transistors and other circuit elements on the chip. In the process of integrated circuit layout and routing, it generally goes through the stages of data import, layout planning, unit setting, and routing. In the data import stage, the gate-level netlist generated by the front-end chip design and the standard unit physical library provided by the wafer factory are imported. In the layout planning stage, designing power planning to ensure that each module can obtain a stable power supply is an important part of layout and routing. In the unit setting stage, the automatic layout tool is used to set the standard unit (such as logic gates, triggers) in the appropriate position on the chip. In the routing stage, under the constraints of meeting the process rules and the number of wiring layers, line width, line spacing and the electrical performance of each line network reliable insulation, the standard units are connected with interconnects according to the connection relationship of the circuit.

[0003] At present, the common power planning process in the integrated circuit layout and routing process is: according to the adopted standard cell architecture and the product's PPA (performance, power and area, which are used to describe the key parameters in semiconductor design), a set of required power planning for each layer is preset. On this basis, the automatic layout and routing tool then sets and routes specific standard cells. However, this method may cause problems such as insufficient power supply in some places, resulting in excessive voltage drop or electromigration violations. Summary of the invention

[0004] In view of this, the embodiments of the present invention provide a layout and routing method, device, electronic device and storage medium for integrated circuit layout, which can effectively control voltage drop and ensure stable power supply of standard units.

[0005] In a first aspect, an embodiment of the present invention provides a layout and routing method for an integrated circuit layout, comprising: determining, from a layout and routing configuration file of the integrated circuit layout, the position coordinates and operating current of each standard unit in the integrated circuit layout; placing each standard unit in a corresponding position in the integrated circuit layout based on the position coordinates of each standard unit in the integrated circuit layout, and determining the number of power lines in a power wiring layer in the integrated circuit layout based on the operating current of each standard unit in the integrated circuit layout; arranging the power lines in the power wiring layer based on the number of power lines in the power wiring layer in the integrated circuit layout and a preset spacing between adjacent power lines, and connecting the arranged power lines to each standard unit.

[0006] In one embodiment, determining the operating current of each standard unit in the integrated circuit layout from the layout and routing configuration file of the integrated circuit layout includes: determining the number of power connection holes of a standard unit in the layout and routing configuration file based on the power connection hole marks in the layout and routing configuration file; wherein each power connection hole corresponds to a specified operating current; and adding the operating currents represented by each power connection hole of the standard unit to obtain the operating current of the standard unit.

[0007] In one embodiment, determining the operating current of each standard unit in the integrated circuit layout from a layout and routing configuration file of the integrated circuit layout includes: determining the operating current of each standard unit in the integrated circuit layout from the operating current value of each standard unit recorded in the layout and routing configuration file.

[0008] In one embodiment, determining the number of power lines in the power wiring layer in the integrated circuit layout based on the operating current of each standard unit in the integrated circuit layout includes: summing the operating current of each standard unit in the integrated circuit layout to obtain the total operating current of the integrated circuit layout; dividing the set expected voltage loss by the total operating current of the integrated circuit layout to obtain the estimated resistance of the integrated circuit layout; and determining the number of power lines in the power wiring layer in the integrated circuit layout based on the ratio of the resistance of a single power line in the integrated circuit layout to the estimated resistance of the integrated circuit layout.

[0009] In one embodiment, after arranging the power lines in the power wiring layer and connecting the arranged power lines to each standard unit, the method further includes: calculating the actual voltage loss of the integrated circuit layout; determining the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines based on the actual voltage loss of the integrated circuit layout; adjusting the power lines and standard units arranged in the integrated circuit layout based on the difference between the actual voltage loss of the integrated circuit layout and the set expected voltage loss, and the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines; and reconnecting the arranged power lines to each standard unit based on the adjustment of the power lines and standard units arranged in the integrated circuit layout.

[0010] In one embodiment, the calculating the actual voltage loss of the integrated circuit layout includes: summing the operating currents of the standard cells in the integrated circuit layout to obtain the total operating current of the integrated circuit layout; calculating the length of the metal wires wired in the integrated circuit layout to determine the resistance of the integrated circuit layout; and multiplying the total operating current of the integrated circuit layout by the resistance of the integrated circuit layout to obtain the actual voltage loss of the integrated circuit layout.

[0011] In one embodiment, based on the difference between the voltage loss and the expected voltage loss, and the ratio of the total operating current of the integrated circuit layout to the spacing between adjacent power lines, the power lines and standard cells arranged in the integrated circuit layout are adjusted, including: if the actual voltage loss of the integrated circuit layout is greater than the set expected voltage loss, then based on the ratio of the total operating current of the integrated circuit layout to the spacing between adjacent power lines, the spacing between adjacent power lines is reduced so that the ratio is equal to an estimated empirical value, thereby reducing the length of metal connections in the power wiring layer in the integrated circuit layout.

[0012] In one embodiment, the power lines and standard cells arranged in the integrated circuit layout are adjusted based on the difference between the voltage loss and the expected voltage loss, and the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines, including: if the actual voltage loss of the integrated circuit layout is greater than the set expected voltage loss, then based on the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines, the interval between the adjacent power lines is kept unchanged, and each standard cell is placed in an interval in the integrated circuit layout at a predetermined distance from the center line of each power line, thereby reducing the length of metal connections in the power wiring layer in the integrated circuit layout.

[0013] In one embodiment, based on the difference between the voltage loss and the expected voltage loss, and the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines, the power lines and standard cells arranged in the integrated circuit layout are adjusted, including: if the actual voltage loss of the integrated circuit layout is greater than the set expected voltage loss, then based on the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines, the width of the metal lines of the integrated circuit layout wiring is increased so that the ratio is equal to the estimated empirical value, thereby reducing the resistance of the integrated circuit layout.

[0014] In one embodiment, after arranging power lines in the power wiring layer and connecting the arranged power lines to each standard cell, the method further includes: performing voltage attenuation analysis based on the resistance of the integrated circuit layout and the operating current of each standard cell.

[0015] In a second aspect, an embodiment of the present invention further provides a layout and wiring device for an integrated circuit layout, comprising: a preparation unit, used to determine the position coordinates and operating current of each standard unit in the integrated circuit layout from a layout and wiring configuration file of the integrated circuit layout; a placement and planning unit, used to place each standard unit in the corresponding position in the integrated circuit layout based on the position coordinates of each standard unit in the integrated circuit layout, and determine the number of power lines in the power wiring layer in the integrated circuit layout based on the operating current of each standard unit in the integrated circuit layout; a wiring unit, used to arrange power lines in the power wiring layer based on the number of power lines in the power wiring layer in the integrated circuit layout and a preset spacing between adjacent power lines, and connect the arranged power lines to each standard unit.

[0016] In one embodiment, the preparation unit is specifically used to: determine the number of power connection holes of a standard unit in the layout and routing configuration file based on the power connection hole mark in the layout and routing configuration file; wherein each power connection hole corresponds to a specified operating current; and add the operating currents represented by each power connection hole of the standard unit to obtain the operating current of the standard unit.

[0017] In one embodiment, the preparation unit is further specifically used to determine the operating current of each standard cell in the integrated circuit layout from the operating current value of each standard cell recorded in the layout and routing configuration file.

[0018] In one embodiment, the placement and planning unit is specifically used to: sum the operating currents of the standard units in the integrated circuit layout to obtain the total operating current of the integrated circuit layout; divide the set expected voltage loss by the total operating current of the integrated circuit layout to obtain the estimated resistance of the integrated circuit layout; determine the number of power lines in the power wiring layer in the integrated circuit layout based on the ratio of the resistance of a single power line in the integrated circuit layout to the estimated resistance of the integrated circuit layout.

[0019] In one embodiment, the device also includes: a loss calculation unit for calculating the actual voltage loss of the integrated circuit layout; a ratio calculation unit for determining the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines based on the actual voltage loss of the integrated circuit layout; an adjustment unit for adjusting the power lines and standard cells arranged in the integrated circuit layout based on the difference between the actual voltage loss of the integrated circuit layout and the set expected voltage loss, and the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines; and a rewiring unit for reconnecting the arranged power lines to each standard cell based on the adjustment of the power lines and standard cells arranged in the integrated circuit layout.

[0020] In one embodiment, the loss calculation unit is specifically used to: sum the operating currents of the standard units in the integrated circuit layout to obtain the total operating current of the integrated circuit layout; calculate the length of the metal wires of the integrated circuit layout to determine the resistance of the integrated circuit layout; multiply the total operating current of the integrated circuit layout by the resistance of the integrated circuit layout to obtain the actual voltage loss of the integrated circuit layout.

[0021] In one embodiment, the adjustment unit is specifically used to: if the actual voltage loss of the integrated circuit layout is greater than the set expected voltage loss, based on the ratio of the total operating current of the integrated circuit layout to the spacing between adjacent power lines, reduce the spacing between adjacent power lines so that the ratio is equal to the estimated empirical value, thereby reducing the length of metal connections in the power wiring layer in the integrated circuit layout.

[0022] In one embodiment, the adjustment unit is further specifically used for: if the actual voltage loss of the integrated circuit layout is greater than the set expected voltage loss, based on the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines, keeping the interval between the adjacent power lines unchanged, placing each standard unit in the integrated circuit layout within a range with a predetermined distance from the center line of each power line, thereby reducing the length of the metal connection in the power wiring layer in the integrated circuit layout.

[0023] In one embodiment, the adjustment unit is further specifically used to: if the actual voltage loss of the integrated circuit layout is greater than the set expected voltage loss, then based on the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines, increase the width of the metal wires of the integrated circuit layout wiring so that the ratio is equal to the estimated empirical value, thereby reducing the resistance of the integrated circuit layout.

[0024] In one embodiment, the device further includes: an attenuation analysis unit, configured to perform voltage attenuation analysis based on the resistance of the integrated circuit layout and the operating current of each standard cell.

[0025] In a third aspect, an embodiment of the present invention further provides an electronic device, comprising: a memory and a processor, wherein the memory is used to store computer-readable instructions; the processor is used to read the computer-readable instructions and implement the layout and routing method provided by any embodiment of the present invention.

[0026] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-readable instructions, and when the computer-readable instructions are executed by a processor, the layout and routing method provided by any embodiment of the present invention is implemented.

[0027] The layout and wiring method, device, electronic device and storage medium of the integrated circuit layout provided by the embodiment of the present invention can determine the number of power lines in the power wiring layer of the integrated circuit layout based on the working current of each standard unit in the integrated circuit layout, arrange the power lines based on the number of power lines and the preset spacing between adjacent power lines, and connect the arranged power lines to the placed standard units. Since the working current of the standard unit can be determined from the layout and wiring configuration file of the integrated circuit layout during the layout and wiring process, the number of power lines used in the layout and wiring can be determined, and the preset spacing between adjacent power lines can be added for wiring, so that the length of the metal wires of the integrated circuit layout wiring can be controlled, thereby controlling the resistance of the integrated circuit layout. Therefore, when the working current and resistance are determined, the voltage drop can be effectively controlled to ensure the stable power supply of the standard unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0029] Figure 1Schematic diagram for prior art power supply planning and standard cell placement; Figure 2 A flow chart of a layout and routing method for an integrated circuit layout provided by an embodiment of the present invention; Figure 3 A flow chart for determining the number of power lines in a power layer of an integrated circuit layout in an embodiment of the present invention; Figure 4 A flow chart of dynamically adjusting layout and routing provided in an embodiment of the present invention; Figure 5 A detailed flow chart of a layout and routing method for an integrated circuit layout provided in an embodiment of the present invention; Figure 6 A schematic structural diagram of a layout and routing device for integrated circuit layout provided by an embodiment of the present invention; Figure 7 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0031] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] In a first aspect, an embodiment of the present invention provides a layout and routing method for an integrated circuit layout, which can effectively control voltage drop and ensure stable power supply of standard cells.

[0033] like Figure 2 As shown, an embodiment of the present invention provides a layout and routing method for an integrated circuit layout, comprising: S11, determining the position coordinates and operating current of each standard cell in the integrated circuit layout from a layout and routing configuration file of the integrated circuit layout.

[0034] In this step, the position coordinates and operating current of each standard cell in the integrated circuit layout can be obtained from the layout and routing configuration file of the integrated circuit layout. The integrated circuit layout and routing configuration file can be one or more configuration files for each standard cell. The configuration file records the corresponding coordinate position of the standard cell in the layout and routing, as well as the current supply that needs to be guaranteed when the standard cell is working.

[0035] Specifically, the position coordinates of the standard cell may refer to the layout and wiring level where the standard cell is to be placed and the specific coordinate position of the level. The working current of the standard cell refers to the current supply required to ensure the normal operation of the standard cell, and the current supply may be determined by simulation and other data. The working current may be a specific current value, or the working current value of the standard cell may be represented by a mark corresponding to a specific current value and the number of the marks.

[0036] For example, the working current of a certain standard unit may be a specific value such as 3A; or it may be the three standard current values.

[0037] It should be noted that the layout and routing configuration file of the integrated circuit layout can be one configuration file or multiple configuration files. The coordinate position and the operating current can be recorded in the same configuration file or in different configuration files, which is not limited in the embodiments of the present invention.

[0038] In yet another embodiment of the present invention, the operating current value recorded in the layout and routing configuration file is the current supply required for the standard cell to operate.

[0039] S12, placing each standard cell in the integrated circuit layout at a corresponding position based on the position coordinates of each standard cell in the integrated circuit layout, and determining the number of power lines in the power wiring layer in the integrated circuit layout based on the operating current of each standard cell in the integrated circuit layout.

[0040] In an embodiment of the present invention, standard cell placement and power planning are performed in the layout and routing of the integrated circuit layout. The power planning includes determining the number of power lines in the power routing layer. It should be noted that the order of the two steps of standard cell placement and power planning can be different. That is, in a certain embodiment, standard cell placement can be performed first, and then power planning can be performed. In another embodiment, power planning can be performed first, and then cell placement can be performed.

[0041] S13, arranging power lines in the power wiring layer based on the number of power lines in the power wiring layer in the integrated circuit layout and a preset distance between adjacent power lines, and connecting the arranged power lines to each standard unit.

[0042] In an embodiment of the present invention, wiring is performed based on the number of power lines determined in step S12 and the preset spacing between adjacent power lines. In this step, the wiring includes arranging the power lines in the power wiring layer and connecting the arranged power lines to each standard unit. For example, in an integrated circuit layout, the number of power lines is 200, and the preset spacing between adjacent power lines is 20um.

[0043] The layout and wiring method of the integrated circuit layout provided by the embodiment of the present invention can determine the number of power lines in the power wiring layer of the integrated circuit layout based on the working current of each standard unit in the integrated circuit layout, arrange the power lines based on the number of power lines and the preset spacing between adjacent power lines, and connect the arranged power lines to the placed standard units. Since the working current of the standard unit can be determined from the layout and wiring configuration file of the integrated circuit layout during the layout and wiring process, the number of power lines used in the layout and wiring can be determined, and the preset spacing between adjacent power lines can be added for wiring, so that the length of the metal wires of the integrated circuit layout wiring can be controlled, thereby controlling the resistance of the integrated circuit layout. Therefore, when the working current and resistance are determined, the voltage drop can be effectively controlled to ensure the stable power supply of the standard unit.

[0044] Specifically, in one embodiment of the present invention, in step S11, the number of power connection holes of a standard unit in the layout and routing configuration file can be determined based on the power connection hole marks in the layout and routing configuration file; wherein each power connection hole corresponds to a specified operating current; and the operating currents represented by each power connection hole of the standard unit are added to obtain the operating current of the standard unit.

[0045] In an embodiment of the present invention, the power connection hole mark in the layout and routing configuration file can be a power connection hole of uniform specifications. One power connection hole corresponds to a specific operating current value. The number of power connection holes indicates the current requirement of the standard unit when it is working normally. For example, each standard unit in the layout and routing uses the same power connection hole mark. In the standard unit 1 configuration file, the number of such power connection holes is 10. If one standard hole corresponds to a current of 1mA, it means that the operating current requirement of standard unit 1 is 10mA.

[0046] In another embodiment of the present invention, the power connection hole marks in the layout and routing configuration file can be power connection holes of different specifications. Specifically, a power connection hole of one specification corresponds to a specific operating current value. For example, in the standard cell 2 configuration file, there are two specifications of power connection holes recorded, and these two specifications of power connection holes are distinguished by the size and / or shape of the holes. The first specification is counted in number of 4, and the second specification is counted in number of 2. If the first specification represents a current of 5mA and the second specification represents a current of 1mA, it means that the operating current requirement of the standard cell 2 is 5×4+1×2=22mA.

[0047] In one embodiment of the present invention, the power connection holes recorded in the layout and routing configuration file also include power port types of VDD ports or VSS ports. The VDD port represents a power network connected to the chip; the VSS port represents a ground network connected to the chip.

[0048] It should be noted that in the present invention, the power connection hole is directly marked in the configuration file, and the power connection hole is used to represent the working current of the standard unit, and the layout and routing are performed by quantifying the working current. Moreover, the layout and routing in the integrated circuit endurance of the present invention can first place the standard unit and then perform power planning; or first perform power planning and then perform standard unit placement.

[0049] After determining the operating current of each standard unit, power planning can be carried out to determine the number of power lines in the power wiring layer. Figure 3 As shown, in one embodiment, determining the number of power lines in a power layer in an integrated circuit layout includes: S21, summing the operating currents of the standard cells in the integrated circuit layout to obtain a total operating current of the integrated circuit layout; S22, dividing the set expected voltage loss by the total operating current of the integrated circuit layout to obtain an estimated resistance of the integrated circuit layout; In this step, the expected voltage loss is divided by the total operating current of the integrated circuit layout to obtain the estimated resistance of the integrated circuit layout. In specific implementation, the expected voltage loss can be estimated based on simulation, such as controlling the voltage loss within a certain range, such as 5%.

[0050] For example, in an embodiment of the present invention, the power supply is 0.75V, and according to a 10% voltage loss, the expected voltage loss is set to 75mV. Thus, if the voltage loss is controlled within this value, the standard cell can still meet the voltage supply required for operation.

[0051] S23. Determine the number of power lines in a power wiring layer in the integrated circuit layout based on a ratio of a resistance of a single power line in the integrated circuit layout to an estimated resistance of the integrated circuit layout.

[0052] In a specific implementation, according to the resistance of the power line in the power wiring layer used for the integrated circuit layout, the resistance estimation can be performed according to the data actually used. For example, the resistance of a single power line in the power wiring layer used in the integrated circuit layout is 1 ohm, and the estimated resistance of the integrated circuit layout is 0.005 ohm. In this way, it can be determined that the number of power lines in the power wiring layer used in the integrated circuit layout is 200.

[0053] In one embodiment, the interval between adjacent power lines may include the interval between signal lines, that is, the power lines and the signal lines are arranged at equal intervals. The wiring is arranged within the limited range of the integrated circuit layout, so that the spacing between the power lines can be adjusted to balance the contradiction between the wiring of the power lines and the signal lines.

[0054] After determining the number of power lines in the integrated circuit layout, wiring can be performed by connecting adjacent power lines to each standard cell.

[0055] After completing the layout and routing of the integrated circuit layout, the present invention can also dynamically adjust the layout and routing according to quantitative analysis to further optimize the utilization of routing resources.

[0056] Specifically, if Figure 4 As shown, in an embodiment of the present invention, dynamically adjusting the layout and routing includes the following steps: S31, calculating the actual voltage loss of the integrated circuit layout; S32, determining a ratio of a total operating current of the integrated circuit layout to a spacing between adjacent power lines based on an actual voltage loss of the integrated circuit layout; S33, adjusting the power lines and standard cells arranged in the integrated circuit layout based on the difference between the actual voltage loss of the integrated circuit layout and the set expected voltage loss, and the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines; S34, based on the adjustment of the power lines and standard cells arranged in the integrated circuit layout, reconnect the arranged power lines to the standard cells.

[0057] It should be noted that the layout and routing of the circuit layout of the present invention is dynamically adjusted after the layout and routing, and the utilization of wiring resources is further optimized. It is not just a one-time adjustment of the layout and routing, but can be a continuous optimization process. In this dynamic adjustment process, on the basis of controlling the voltage drop and ensuring the stable power supply of the standard unit, on the one hand, the utilization of wiring resources is further optimized, and on the other hand, within the limited range of the integrated circuit layout, the spacing of the power lines is adjusted to balance the contradiction between the wiring of the power lines and the signal lines.

[0058] In one embodiment, in step S31, calculating the actual voltage loss of the integrated circuit layout includes: summing the operating currents of the standard units in the integrated circuit layout to obtain the total operating current of the integrated circuit layout; calculating the length of the metal wires wired in the integrated circuit layout to determine the resistance of the integrated circuit layout; multiplying the total operating current of the integrated circuit layout by the resistance of the integrated circuit layout to obtain the actual voltage loss of the integrated circuit layout.

[0059] In one embodiment, in step S33, based on the difference between the voltage loss and the expected voltage loss, and the ratio of the total operating current of the integrated circuit layout to the spacing between adjacent power lines, the power lines and standard cells arranged in the integrated circuit layout are adjusted, including: if the actual voltage loss of the integrated circuit layout is greater than the set expected voltage loss, then based on the ratio of the total operating current of the integrated circuit layout to the spacing between adjacent power lines, the spacing between adjacent power lines is reduced so that the ratio is equal to the estimated empirical value, thereby reducing the length of metal connections in the power wiring layer in the integrated circuit layout.

[0060] Specifically, there is a certain relationship between the total operating current of the integrated circuit layout and the interval between adjacent power lines. In the layout and wiring of the integrated circuit layout, because the operating current of each standard unit is determined according to the configuration file, it is a relatively stable value. Therefore, the total operating current of the integrated circuit layout is also quite stable. In the wiring, the interval between adjacent power lines largely determines the length of the metal connection in the power wiring layer, and determines the voltage loss of the integrated circuit layout. In the specific implementation, the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines can be determined according to the empirical value. If the actual voltage loss of the integrated circuit layout is greater than the set expected voltage loss, then based on the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines, the interval between the adjacent power lines is reduced so that the ratio is equal to the estimated empirical value, thereby achieving the purpose of controlling voltage loss.

[0061] In another embodiment, in step S33, based on the difference between the voltage loss and the expected voltage loss, and the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines, the power lines and standard cells arranged in the integrated circuit layout are adjusted, including: if the actual voltage loss of the integrated circuit layout is greater than the set expected voltage loss, then based on the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines, the interval between the adjacent power lines is kept unchanged, and each standard cell is placed in the integrated circuit layout within a predetermined distance from the center line of each power line, thereby reducing the length of the metal connection in the power wiring layer in the integrated circuit layout. In this step, adjusting the position of the standard cell can be to disperse the standard cell in the interval with a predetermined distance from the center line (the center line in the length direction) of each power line, such as 4um. In this way, by concentrating the standard cells near each power line, the length of the metal connection in the power wiring layer in the integrated circuit layout can be reduced.

[0062] In another embodiment, in step S33, based on the difference between the voltage loss and the expected voltage loss, and the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines, the power lines and standard cells arranged in the integrated circuit layout are adjusted, including: if the actual voltage loss of the integrated circuit layout is greater than the set expected voltage loss, then based on the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines, the width of the metal lines of the integrated circuit layout wiring is increased so that the ratio is equal to the estimated empirical value, thereby reducing the resistance of the integrated circuit layout.

[0063] The large current in the power network will cause the electromigration effect, resulting in the poor performance of the metal lines of the power network, and ultimately affecting the reliability of the chip. Specifically, if the actual voltage loss of the integrated circuit layout is greater than the expected voltage loss, then according to the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines, the width of the metal lines of the integrated circuit layout wiring is increased so that the ratio is equal to the estimated empirical value, thereby reducing the resistance of the integrated circuit layout. In the present invention, the width of the metal lines of the integrated circuit layout wiring is increased to reduce the resistance of the integrated circuit layout, which can avoid the electromigration effect.

[0064] In one embodiment, after arranging the power lines in the power wiring layer and connecting the arranged power lines to each standard cell, the method further includes: performing voltage decay analysis based on the resistance of the integrated circuit layout and the operating current of each standard cell. Specifically, after the layout and wiring of the integrated circuit layout is completed and the data is basically determined, the power consumption and voltage decay analysis of the entire design is more accurate, and the voltage decay analysis is used to evaluate whether the chip meets the design requirements.

[0065] The layout and wiring method of the integrated circuit layout provided by the embodiment of the present invention can determine the number of power lines in the power wiring layer of the integrated circuit layout based on the working current of each standard unit in the integrated circuit layout, arrange the power lines based on the number of power lines and the preset spacing between adjacent power lines, and connect the arranged power lines to the placed standard units. Since the working current of the standard unit can be determined from the layout and wiring configuration file of the integrated circuit layout during the layout and wiring process, the number of power lines used in the layout and wiring can be determined, and the preset spacing between adjacent power lines can be added for wiring, so that the length of the metal wires of the integrated circuit layout wiring can be controlled, thereby controlling the resistance of the integrated circuit layout. Therefore, when the working current and resistance are determined, the voltage drop can be effectively controlled to ensure the stable power supply of the standard unit.

[0066] The layout and routing method of an integrated circuit provided by an embodiment of the present invention is described in detail below through a specific embodiment.

[0067] like Figure 5 As shown, the layout and routing method of the integrated circuit layout provided by the embodiment of the present invention may include: S401, determining the position coordinates of each standard cell in the integrated circuit layout from a layout and routing configuration file of the integrated circuit layout; S402, determining the position coordinates and operating current of each standard cell in the integrated circuit layout from a layout and routing configuration file of the integrated circuit layout; The power connection hole mark in the layout and routing configuration file is a power connection hole of uniform specification; one power connection hole corresponds to a specific working current value; and the number of power connection holes indicates the current requirement of the standard unit when it works normally.

[0068] S403, summing the operating currents of the standard cells in the integrated circuit layout to obtain a total operating current of the integrated circuit layout; S404, dividing the set expected voltage loss by the total operating current of the integrated circuit layout to obtain an estimated resistance of the integrated circuit layout; S405, determining the number of power lines in a power wiring layer in the integrated circuit layout based on a ratio of a resistance of a single power line in the integrated circuit layout to an estimated resistance of the integrated circuit layout; S406, placing each standard cell in a corresponding position in the integrated circuit layout based on the position coordinates of each standard cell in the integrated circuit layout; S407, arranging power lines in the power wiring layer based on the number of power lines in the power wiring layer in the integrated circuit layout and a preset distance between adjacent power lines, and connecting the arranged power lines to each standard cell; S408, calculating the length of the metal wires of the integrated circuit layout wiring, and determining the resistance of the integrated circuit layout; S409, multiplying the total operating current of the integrated circuit layout by the resistance of the integrated circuit layout to obtain an actual voltage loss of the integrated circuit layout; S410, determining a ratio of a total operating current of the integrated circuit layout to a spacing between adjacent power lines based on an actual voltage loss of the integrated circuit layout; S411, adjusting the power lines and standard cells arranged in the integrated circuit layout based on the difference between the actual voltage loss of the integrated circuit layout and the set expected voltage loss, and the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines; Among them, if the actual voltage loss of the integrated circuit layout is greater than the set expected voltage loss, the interval between the adjacent power lines is reduced based on the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines so that the ratio is equal to the estimated empirical value, thereby reducing the length of the metal connection in the power wiring layer in the integrated circuit layout.

[0069] S412, based on the adjustment of the power lines and standard cells arranged in the integrated circuit layout, reconnecting the arranged power lines to the standard cells; S413: Perform voltage decay analysis based on the resistance of the integrated circuit layout and the operating current of each standard cell.

[0070] In a second aspect, an embodiment of the present invention provides a layout and routing device for an integrated circuit layout, which can effectively control voltage drop and ensure stable power supply of standard cells.

[0071] like Figure 6 As shown, the layout and wiring device of the integrated circuit layout according to the embodiment of the present invention comprises: A preparation unit 51 is used to determine the position coordinates and operating current of each standard cell in the integrated circuit layout from a layout and routing configuration file of the integrated circuit layout; a placement and planning unit 52, configured to place each standard cell in a corresponding position in the integrated circuit layout based on the position coordinates of each standard cell in the integrated circuit layout, and determine the number of power lines in the power wiring layer in the integrated circuit layout based on the operating current of each standard cell in the integrated circuit layout; The wiring unit 53 is used to arrange the power lines in the power wiring layer based on the number of power lines in the power wiring layer in the integrated circuit layout and the preset distance between adjacent power lines, and connect the arranged power lines to each standard unit.

[0072] The layout and wiring device of the integrated circuit layout provided by the embodiment of the present invention can determine the number of power lines in the power wiring layer of the integrated circuit layout based on the working current of each standard unit in the integrated circuit layout, arrange the power lines based on the number of power lines and the preset spacing between adjacent power lines, and connect the arranged power lines to the placed standard units. Since the working current of the standard unit can be determined from the layout and wiring configuration file of the integrated circuit layout during the layout and wiring process, the number of power lines used in the layout and wiring can be determined, and the preset spacing between adjacent power lines can be added for wiring, so that the length of the metal wires of the integrated circuit layout wiring can be controlled, thereby controlling the resistance of the integrated circuit layout. Therefore, when the working current and resistance are determined, the voltage drop can be effectively controlled to ensure the stable power supply of the standard unit.

[0073] In one embodiment, the preparation unit 51 is specifically used to: determine the number of power connection holes of a standard unit in the layout and routing configuration file based on the power connection hole marks in the layout and routing configuration file; wherein each power connection hole corresponds to a specified operating current; and add the operating currents represented by each power connection hole of the standard unit to obtain the operating current of the standard unit.

[0074] In one implementation, the preparation unit 51 is further specifically used to determine the operating current of each standard cell in the integrated circuit layout from the operating current value of each standard cell recorded in the layout and routing configuration file.

[0075] In one embodiment, the placement and planning unit 52 is specifically used to: sum the operating currents of the standard units in the integrated circuit layout to obtain the total operating current of the integrated circuit layout; divide the set expected voltage loss by the total operating current of the integrated circuit layout to obtain the estimated resistance of the integrated circuit layout; and determine the number of power lines in the power wiring layer in the integrated circuit layout based on the ratio of the resistance of a single power line in the integrated circuit layout to the estimated resistance of the integrated circuit layout.

[0076] In one embodiment, the device also includes: a loss calculation unit for calculating the actual voltage loss of the integrated circuit layout; a ratio calculation unit for determining the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines based on the actual voltage loss of the integrated circuit layout; an adjustment unit for adjusting the power lines and standard cells arranged in the integrated circuit layout based on the difference between the actual voltage loss of the integrated circuit layout and the set expected voltage loss, and the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines; and a rewiring unit for reconnecting the arranged power lines to each standard cell based on the adjustment of the power lines and standard cells arranged in the integrated circuit layout.

[0077] In one embodiment, the loss calculation unit is specifically used to: sum the operating currents of the standard units in the integrated circuit layout to obtain the total operating current of the integrated circuit layout; calculate the length of the metal wires of the integrated circuit layout to determine the resistance of the integrated circuit layout; multiply the total operating current of the integrated circuit layout by the resistance of the integrated circuit layout to obtain the actual voltage loss of the integrated circuit layout.

[0078] In one embodiment, the adjustment unit is specifically used to: if the actual voltage loss of the integrated circuit layout is greater than the set expected voltage loss, based on the ratio of the total operating current of the integrated circuit layout to the spacing between adjacent power lines, reduce the spacing between adjacent power lines so that the ratio is equal to the estimated empirical value, thereby reducing the length of metal connections in the power wiring layer in the integrated circuit layout.

[0079] In one embodiment, the adjustment unit is further specifically used for: if the actual voltage loss of the integrated circuit layout is greater than the set expected voltage loss, based on the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines, keeping the interval between the adjacent power lines unchanged, placing each standard unit in the integrated circuit layout within a range with a predetermined distance from the center line of each power line, thereby reducing the length of the metal connection in the power wiring layer in the integrated circuit layout.

[0080] In one embodiment, the adjustment unit is further specifically used to: if the actual voltage loss of the integrated circuit layout is greater than the set expected voltage loss, then based on the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines, increase the width of the metal wires of the integrated circuit layout wiring so that the ratio is equal to the estimated empirical value, thereby reducing the resistance of the integrated circuit layout.

[0081] In one embodiment, the device further includes: an attenuation analysis unit, configured to perform voltage attenuation analysis based on the resistance of the integrated circuit layout and the operating current of each standard cell.

[0082] In a third aspect, an embodiment of the present invention further provides an electronic device that can effectively control voltage drop and ensure stable power supply of standard units.

[0083] like Figure 7 As shown, the electronic device provided by the embodiment of the present invention may include: a shell 61, a processor 62, a memory 63, a circuit board 64 and a power supply circuit 65, wherein the circuit board 64 is arranged inside the space enclosed by the shell 61, and the processor 62 and the memory 63 are arranged on the circuit board 64; the power supply circuit 65 is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory 63 is used to store executable program codes; the processor 62 runs the program corresponding to the executable program code by reading the executable program code stored in the memory 63, so as to execute the layout and wiring method of the integrated circuit layout provided by any of the aforementioned embodiments.

[0084] The specific execution process of the above steps by the processor 62 and the steps further executed by the processor 62 by running the executable program code can be found in the description of the previous embodiment, which will not be repeated here.

[0085] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement any one of the integrated circuit layout layout methods provided in the aforementioned embodiments, thereby also being able to achieve the corresponding technical effects, which have been described in detail above and will not be repeated here.

[0086] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0087] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0088] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0089] For the convenience of description, the above device is described by dividing the functions into various units / modules. Of course, when implementing the present invention, the functions of each unit / module can be implemented in the same or more than two software and / or hardware.

[0090] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0091] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

[0092] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A layout and routing method for an integrated circuit layout, characterized in that: include: Determining, from a layout and routing configuration file of the integrated circuit layout, position coordinates and operating current of each standard cell in the integrated circuit layout; Based on the position coordinates of each standard cell in the integrated circuit layout, placing each standard cell in a corresponding position in the integrated circuit layout, and determining the number of power lines in a power wiring layer in the integrated circuit layout based on the operating current of each standard cell in the integrated circuit layout; Based on the number of power lines in the power wiring layer in the integrated circuit layout and the preset distance between adjacent power lines, the power lines are arranged in the power wiring layer, and the arranged power lines are connected to each standard unit.

2. The method according to claim 1, characterized in that Determining the operating current of each standard cell in the integrated circuit layout from the layout and routing configuration file of the integrated circuit layout includes: Determine the number of power connection holes of a standard unit in the layout and routing configuration file based on the power connection hole marks in the layout and routing configuration file; wherein each power connection hole corresponds to a specified operating current; The operating currents represented by the power connection holes of the standard unit are added together to obtain the operating current of the standard unit.

3. The method according to claim 1, characterized in that: Determining the operating current of each standard cell in the integrated circuit layout from the layout and routing configuration file of the integrated circuit layout includes: The operating current of each standard cell in the integrated circuit layout is determined from the operating current value of each standard cell recorded in the layout and routing configuration file.

4. The method according to claim 1, characterized in that: The determining the number of power lines in the power wiring layer in the integrated circuit layout based on the operating current of each standard cell in the integrated circuit layout comprises: summing the operating currents of the standard cells in the integrated circuit layout to obtain the total operating current of the integrated circuit layout; Dividing the set expected voltage loss by the total operating current of the integrated circuit layout to obtain an estimated resistance of the integrated circuit layout; The number of power lines in a power wiring layer in the integrated circuit layout is determined based on a ratio of a resistance of a single power line in the integrated circuit layout to an estimated resistance of the integrated circuit layout.

5. The method according to claim 1, characterized in that: After arranging power lines in the power wiring layer and connecting the arranged power lines to each standard cell, the method further includes: Calculate the actual voltage loss of integrated circuit layout; Determining a ratio of a total operating current of the integrated circuit layout to a spacing between adjacent power lines based on an actual voltage loss of the integrated circuit layout; Adjusting the power lines and standard cells arranged in the integrated circuit layout based on the difference between the actual voltage loss of the integrated circuit layout and the set expected voltage loss, and the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines; Based on the adjustment of the power lines and standard cells arranged in the integrated circuit layout, the arranged power lines are reconnected to each standard cell.

6. The method according to claim 5, characterized in that The calculating the actual voltage loss of the integrated circuit layout comprises: summing the operating currents of the standard cells in the integrated circuit layout to obtain the total operating current of the integrated circuit layout; Calculate the length of metal wires used in the layout of integrated circuits and determine the resistance of the integrated circuit layout; The total operating current of the integrated circuit layout is multiplied by the resistance of the integrated circuit layout to obtain the actual voltage loss of the integrated circuit layout.

7. The method according to claim 5, characterized in that The adjusting of the power lines and standard cells arranged in the integrated circuit layout based on the difference between the voltage loss and the expected voltage loss and the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines comprises: If the actual voltage loss of the integrated circuit layout is greater than the set expected voltage loss, the interval between the adjacent power lines is reduced based on the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines so that the ratio is equal to the estimated empirical value, thereby reducing the length of the metal connection in the power wiring layer in the integrated circuit layout.

8. The method according to claim 5, characterized in that The adjusting of the power lines and standard cells arranged in the integrated circuit layout based on the difference between the voltage loss and the expected voltage loss and the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines comprises: If the actual voltage loss of the integrated circuit layout is greater than the set expected voltage loss, based on the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines, the interval between the adjacent power lines is kept unchanged, and each standard unit is placed within an interval with a predetermined distance from the center line of the power line in the integrated circuit layout, thereby reducing the length of the metal connection in the power wiring layer in the integrated circuit layout.

9. The method according to claim 5, characterized in that The adjusting of the power lines and standard cells arranged in the integrated circuit layout based on the difference between the voltage loss and the expected voltage loss and the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines comprises: If the actual voltage loss of the integrated circuit layout is greater than the set expected voltage loss, then based on the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines, the width of the metal lines of the integrated circuit layout is increased so that the ratio is equal to the estimated empirical value, thereby reducing the resistance of the integrated circuit layout.

10. The method according to claim 1, characterized in that After arranging power lines in the power wiring layer and connecting the arranged power lines to each standard cell, the method further includes: Voltage decay analysis is performed based on the resistance of the integrated circuit layout and the operating current of each standard cell.

11. A layout and routing device for integrated circuit layout, characterized in that: include: A preparation unit, used to determine the position coordinates and operating current of each standard cell in the integrated circuit layout from a layout and routing configuration file of the integrated circuit layout; a placement and planning unit, configured to place each standard cell in the integrated circuit layout at a corresponding position in the integrated circuit layout based on the position coordinates of each standard cell in the integrated circuit layout, and determine the number of power lines in the power wiring layer in the integrated circuit layout based on the operating current of each standard cell in the integrated circuit layout; The wiring unit is used to arrange the power lines in the power wiring layer based on the number of power lines in the power wiring layer in the integrated circuit layout and the preset distance between adjacent power lines, and connect the arranged power lines to each standard unit.

12. The device according to claim 11, characterized in that The preparation unit is specifically used for: Determine the number of power connection holes of a standard unit in the layout and routing configuration file based on the power connection hole marks in the layout and routing configuration file; wherein each power connection hole corresponds to a specified operating current; The operating currents represented by the power connection holes of the standard unit are added together to obtain the operating current of the standard unit.

13. The device according to claim 11, characterized in that The preparation unit is further specifically used for: The operating current of each standard cell in the integrated circuit layout is determined from the operating current value of each standard cell recorded in the layout and routing configuration file.

14. The device according to claim 11, characterized in that The placement and planning unit is specifically used for: summing the operating currents of the standard cells in the integrated circuit layout to obtain the total operating current of the integrated circuit layout; Dividing the set expected voltage loss by the total operating current of the integrated circuit layout to obtain an estimated resistance of the integrated circuit layout; The number of power lines in a power wiring layer in the integrated circuit layout is determined based on a ratio of a resistance of a single power line in the integrated circuit layout to an estimated resistance of the integrated circuit layout.

15. The device according to claim 11, characterized in that The device also includes: A loss calculation unit, used to calculate the actual voltage loss of the integrated circuit layout; a ratio calculation unit, configured to determine a ratio of a total operating current of the integrated circuit layout to a spacing between the adjacent power lines based on an actual voltage loss of the integrated circuit layout; an adjusting unit, configured to adjust the power lines and standard cells arranged in the integrated circuit layout based on a difference between an actual voltage loss of the integrated circuit layout and the set expected voltage loss, and a ratio of a total operating current of the integrated circuit layout to an interval between adjacent power lines; The rewiring unit is used for reconnecting the arranged power lines with each standard cell based on the adjustment of the power lines and standard cells arranged in the integrated circuit layout.

16. The device according to claim 15, characterized in that The loss calculation unit is specifically used for: summing the operating currents of the standard cells in the integrated circuit layout to obtain the total operating current of the integrated circuit layout; Calculate the length of metal wires used in the layout of integrated circuits and determine the resistance of the integrated circuit layout; The total operating current of the integrated circuit layout is multiplied by the resistance of the integrated circuit layout to obtain the actual voltage loss of the integrated circuit layout.

17. The device according to claim 15, characterized in that The adjustment unit is specifically used for: If the actual voltage loss of the integrated circuit layout is greater than the set expected voltage loss, the interval between the adjacent power lines is reduced based on the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines so that the ratio is equal to the estimated empirical value, thereby reducing the length of the metal connection in the power wiring layer in the integrated circuit layout.

18. The device according to claim 15, characterized in that The adjustment unit is further specifically used for: If the actual voltage loss of the integrated circuit layout is greater than the set expected voltage loss, based on the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines, the interval between the adjacent power lines is kept unchanged, and each standard unit is placed within an interval with a predetermined distance from the center line of each power line in the integrated circuit layout, thereby reducing the length of the metal connection in the power wiring layer in the integrated circuit layout.

19. The device according to claim 15, characterized in that The adjustment unit is further specifically used for: If the actual voltage loss of the integrated circuit layout is greater than the set expected voltage loss, then based on the ratio of the total operating current of the integrated circuit layout to the interval between the adjacent power lines, the width of the metal lines of the integrated circuit layout is increased so that the ratio is equal to the estimated empirical value, thereby reducing the resistance of the integrated circuit layout.

20. The device according to claim 11, characterized in that The device also includes: The attenuation analysis unit is used to perform voltage attenuation analysis based on the resistance of the integrated circuit layout and the operating current of each standard unit.

21. An electronic device, characterized in that: The electronic device comprises: a memory and a processor, wherein the memory is used to store computer-readable instructions; and the processor is used to read the computer-readable instructions and implement the layout and routing method according to any one of claims 1 to 10.

22. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-readable instructions, and when the computer-readable instructions are executed by a processor, the layout and routing method according to any one of claims 1 to 10 is implemented.

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