A method for drilling a through hole, a computer device, a program product and a storage medium

Abstract

The present invention provides a method, computer device, program product, and storage medium for drilling vias, including: obtaining layout pattern information of metal line layers in the power and ground networks of an integrated circuit; sequentially determining at least one intersecting first physical region between each adjacent metal line layer where a via layer is to be implemented, and drilling a first via in the first physical region; recording the via information of the first via and establishing a mapping relationship between the via layer and the via information; sequentially calculating all second physical regions between each adjacent metal line layer where a via layer is to be implemented based on the layout pattern information; determining the via type and absolute coordinate information of all required vias based on the absolute positions and mapping relationships of the second physical regions, and recording the information in a preset file for direct access and via drilling. This solution can solve the via implementation problem between power and ground metal lines with minimal runtime and low server resource requirements.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a method for drilling a through hole, a computer device, a program product, and a storage medium. Background Art

[0002] In digital integrated circuits, power is supplied to functional devices by metal wires flowing vertically from the top layer to the bottom layer, layer by layer. Each layer is connected by regularly spaced vias. As digital integrated circuits continue to evolve, the functionality of the entire chip becomes increasingly complex, and the area becomes larger. The probability of individual modules being very large increases, requiring more and more power and ground metal wires. This increases the number of vias required to connect these metal wires within a single module.

[0003] Existing via drilling solutions typically follow standard EDA commands, drilling vias between intersecting metal lines in adjacent metal layers, layer by layer, for the entire module's power and ground metal lines. EDA automation tools automatically divide the entire module area into multiple blocks and use multithreading to process multiple blocks in parallel to speed up via drilling. However, due to the large number of power and ground metal lines, a large number of vias need to be drilled. Parallel processing of multiple areas, on top of the already large memory requirements, requires checking physical rules in multiple locations in parallel, which requires even more memory and can easily cause computer crashes. Furthermore, the large number of intersecting metal layers that need to check physical rules to achieve via drilling requires a significant amount of runtime, impacting overall efficiency. Therefore, there is an urgent need for a solution that can address the physical implementation of vias between power and ground metal lines in large-area, high-performance modules using advanced processes while minimizing computer resources and runtime. Summary of the Invention

[0004] The purpose of the present invention is to provide a method for drilling through holes, a computer device, a program product and a storage medium, which can solve the problem of realizing through holes between power and ground metal lines in large-area, high-frequency modules under advanced processes with extremely short running time and low server resource requirements.

[0005] The technical solutions provided by the present invention are as follows:

[0006] In a first aspect, the present application provides a method for drilling a through hole, which is applied to EDA design of an integrated circuit, comprising the steps of:

[0007] Acquire layout pattern information of a metal line layer in a power ground network of an integrated circuit, wherein the layout pattern information includes the width of the metal line and the spacing between adjacent metal lines of the same type;

[0008] Determine in sequence at least one first physical region intersecting each other between adjacent metal line levels where a through-hole level is required, and automatically create a first through-hole in the first physical region using an EDA tool;

[0009] Recording through-hole information of the first through-hole and establishing a mapping relationship between the through-hole hierarchy and the through-hole information, wherein the through-hole information includes a through-hole type of the first through-hole and offset information of the first through-hole in the first physical area;

[0010] sequentially calculating all second physical areas between each adjacent metal line level that needs to implement the through-hole level according to the layout pattern information;

[0011] Determining the through-hole types and absolute coordinate information of all through-holes that need to be punched according to the absolute position of the second physical area and the mapping relationship, and recording them in a preset file;

[0012] During the EDA design process of the integrated circuit, the preset file is directly read, and the through-hole drilling operation is automatically performed through the EDA tool according to the through-hole types and absolute coordinate information of all through-holes required to be drilled recorded in the preset file.

[0013] In some embodiments, when there is only one type of layout pattern information of the metal line level in the power ground network of the integrated circuit, a mutually intersecting first physical area is determined in sequence between each adjacent metal line level that needs to implement a through-hole level, and a mapping relationship is established.

[0014] In some embodiments, when the layout pattern information of the metal line level in the power ground network of the integrated circuit includes multiple types, a first through hole is punched in sequence for each type of mutually intersecting first physical area corresponding to the layout pattern information, and the corresponding mapping relationships are established respectively.

[0015] In some embodiments, when the layout pattern information of the metal line level in the power ground network of the integrated circuit includes multiple types, all the second physical areas between each adjacent metal line level required to implement the via level are calculated by ANDing.

[0016] In some embodiments, the offset information includes an offset in a horizontal direction and an offset in a vertical direction of the first through hole in the first physical region relative to a reference point.

[0017] In some embodiments, the layout of the metal line layers in the power ground network of the integrated circuit is a regular layout, and the width of the metal lines and the intervals between adjacent metal lines of the same type are fixed values.

[0018] In some implementations, the preset file is a DEF file.

[0019] In a second aspect, the present application provides a computer device comprising a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the method for drilling a through hole described in the first aspect.

[0020] In a third aspect, the present application provides a computer storage medium having a computer program or instructions stored thereon, which, when executed by a processor, implements the steps of the method for drilling a through hole described in the first aspect.

[0021] In a fourth aspect, the present application provides a computer program product, comprising a computer program or instructions, which, when executed by a processor, implement the steps of the method for drilling a through hole described in the first aspect.

[0022] According to the present invention, a method for drilling a through hole, a computer device, a program product, and a storage medium can realize the operation of drilling a through hole between power and ground metal lines in the power supply network of large-area, high-frequency modules under advanced processes with extremely short running time and low server resource requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The preferred implementation scheme will be described below in a clear and understandable manner with reference to the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and implementation methods of this solution.

[0024] Figure 1 It is a physical diagram of the through-hole connections of a chip power network;

[0025] Figure 2 It is a schematic diagram of a fixed layout pattern of metal lines in a chip power network;

[0026] Figure 3 It is a flow chart of an embodiment of the present invention;

[0027] Figure 4 is a schematic diagram of a first physical region according to an embodiment of the present invention;

[0028] Figure 5 Schematic diagram of a first through hole according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the specific embodiments of the present invention will be described below with reference to the accompanying drawings. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings and other embodiments can be obtained based on these drawings without inventive work.

[0030] To simplify the drawings, only the parts relevant to the present invention are schematically shown in each figure. They do not represent the actual structure of the product. Furthermore, to simplify the drawings and facilitate understanding, in some figures, only one of the components with the same structure or function is schematically depicted or labeled. As used herein, "one" not only means "only one" but also "more than one."

[0031] In digital integrated circuits, in order to power functional devices, such as Figure 1 As shown, the metal lines on the top layer (e.g., M15) need to be passed down layer by layer in a perpendicular direction to the metal lines on the bottom layer (e.g., M1), and each two layers are connected by vias at a certain interval. From M15 to M1, each layer often needs power and ground metal lines, and each layer is laid down alternately horizontally and vertically, and each layer of metal lines is laid down according to a fixed layout pattern. For example, Figure 2 In a fixed layout mode shown, the vertical (or horizontal) metal lines that stagger the power supply (VDD) and ground (VSS) are all implemented by using a metal line width of 0.5um and a spacing of 2um for the same type of metal lines.

[0032] With the continuous advancement of digital integrated circuits, the functionality implemented by the entire chip has become increasingly complex, and the area has become larger and larger. The probability of individual modules being very large has also increased. Consequently, more power and ground metal lines are required, and the number of vias required to connect the power and ground metal lines within a single module has increased. At the same time, as chip operating frequencies increase, power consumption per unit area increases. This has led to a shift in the overall metal line layout pattern from a coarse and sparse pattern with large widths and large spacing to a fine and dense pattern with small widths and small spacing. This has further increased the number of vias required to connect the power and ground metal lines. Furthermore, with advanced processes, this fine and dense pattern complicates physical rule checking, resulting in more constraints on the vias used to connect the metal lines, requiring more checks during physical implementation, and increasing the cost of computer resources (primarily computer memory) and runtime.

[0033] Existing via drilling solutions typically follow standard EDA commands, drilling vias between intersecting metal lines in adjacent metal layers, layer by layer, for the entire module's power and ground metal lines. EDA automation tools automatically divide the entire module area into multiple blocks and use multithreading to process multiple blocks in parallel to speed up via drilling. However, due to the large number of power and ground metal lines, a large number of vias need to be drilled. Parallel processing of multiple areas, on top of the already large memory requirements, requires checking physical rules in multiple locations in parallel, which requires even more memory and can easily cause computer crashes. Furthermore, the large number of intersecting metal layers that need to check physical rules to achieve via drilling requires a significant amount of runtime, impacting overall efficiency. Therefore, there is an urgent need for a solution that can address the physical implementation of vias between power and ground metal lines in large-area, high-performance modules using advanced processes while minimizing computer resources and runtime.

[0034] This solution takes into account the generally regular metal layering within the power and ground networks, with power and ground metal lines repeated at fixed widths and intervals on each layer. Furthermore, when the power and ground metal lines and vias are created, layout and routing have not yet been completed, and nearby routing resources are available, giving power and ground vias priority. Furthermore, when EDA uses general commands to implement vias, it does not regularly check the physical rules for each intersection of adjacent metal layers before physically implementing the vias, resulting in a long runtime. Therefore, this solution only uses EDA tools to complete the via implementation at one location where adjacent metal layers intersect. This way, the EDA tool will select the best via for such a metal line intersection scenario (meeting DRC requirements and maximizing the contact area between two adjacent metal layers). Then, using this via information, including the via type and the relative offset position of the via at the intersection, DEF is applied to other intersections to complete the via implementation of the entire power ground network. This allows the via drilling operation between power and ground metal lines in the power network of large-area, high-frequency modules under advanced processes with extremely short runtimes and low server resource requirements. The following is a detailed description of this solution with the accompanying drawings:

[0035] In one embodiment, the reference Figure 3 The present application provides a method for drilling a through hole, which is applied to EDA design of an integrated circuit, comprising the steps of:

[0036] S100 , obtaining layout pattern information of metal line levels in a power ground network of an integrated circuit, where the layout pattern information includes the width of the metal lines and the spacing between adjacent metal lines of the same type.

[0037] Specifically, the layout of metal line layers in the power-ground network of an integrated circuit is generally regular, with fixed metal line widths and spacing between adjacent metal lines of the same type. This application utilizes this regularity to achieve mapping of individual via layers to the entire system without consuming significant computer resources. In other embodiments, this solution can also be applied to the layout of metal line layers in irregular or partially irregular power-ground networks, but this requires additional resources to determine the intersection locations of all adjacent metal lines.

[0038] S200 , sequentially determining at least one first physical region intersecting each other between adjacent metal line levels where a through-hole level is required, and automatically drilling a first through-hole in the first physical region using an EDA tool.

[0039] Before the specific chip large-area through-hole drilling operation is carried out, this solution first finds a mutually intersecting physical area for each adjacent metal layer that needs to realize the through-hole level as a demonstration of each through-hole level, such as Figure 4 and Figure 5 As shown, an EDA tool is used to automatically drill a via. Because the tool performs the automatic drilling, the hole type and offset position can be considered the optimal choice made by the EDA based on the actual situation. Furthermore, since this solution only drills a single via at an intersection, it is fast and requires very few computer resources.

[0040] S300 , recording the through-hole information of the first through-hole and establishing a mapping relationship between the through-hole hierarchy and the through-hole information, wherein the through-hole information includes the through-hole type of the first through-hole and the offset information of the first through-hole in the first physical region.

[0041] like Figure 5 As shown, the offset information includes the horizontal offset Offset_X and the vertical offset Offset_Y of the first via in the first physical region relative to the reference point. As previously mentioned, the type and offset position of the via generated by the EDA tool during automatic drilling can be considered the optimal choice made by the EDA based on actual conditions. Due to the regular layout of the metal line hierarchy in the power ground network, the type of the first via and the offset position at the metal line intersection are also applicable to other metal line intersections. Therefore, by establishing a mapping relationship between the via hierarchy and the via information, the drilling method of the first via can be applied to other intersections.

[0042] S400 , sequentially calculating all second physical areas between each adjacent metal line level where a through-hole level needs to be implemented according to the layout mode information.

[0043] Based on the fixed layout pattern information of the metal line layers of the power and ground networks, the intersection locations between adjacent metal layers for each required via layer can be calculated sequentially. Because the layout pattern information is fixed, simply calculating the coordinates of these intersection locations is very simple. Furthermore, the simple mathematical calculations are fast on modern computers and require minimal computing resources.

[0044] S500: Determine the through-hole types and absolute coordinate information of all through-holes that need to be punched according to the absolute position and mapping relationship of the second physical area, and record them in a preset file.

[0045] Based on the calculated absolute position and mapping relationship of the second physical region between each adjacent metal line layer where a via is required, the through-hole type and absolute coordinate information for all required through-holes in the entire design can be calculated and stored for direct application in subsequent EDA design processes. This step is also a simple mathematical calculation, which is fast on modern computers and requires minimal computing resources.

[0046] In this application, the preset file is a DEF file, and the calculated through-hole types and absolute coordinate information of all through-holes to be punched are written to a specific power_via.out.def file in accordance with the standard DEF format, which can be directly read by EDA. In other embodiments, the information can be stored in other files as required, and this application does not limit it.

[0047] S600. During the EDA design process of the integrated circuit, the preset file is directly read, and the through-hole punching operation is automatically performed through the EDA tool according to the through-hole types and absolute coordinate information of all through-holes required to be punched recorded in the preset file.

[0048] During the EDA design process of integrated circuits, the power_via.out.def file can be directly read to determine the via type and absolute coordinate information of all required vias, and then used for drilling operations, eliminating the time required to calculate the via type and position at each intersection. Moreover, this step simply reads in the design physical information, avoiding the need to perform design rule checks at every location, and avoiding the steps of selecting via type and physical implementation coordinates, resulting in shorter overall runtimes and less memory required.

[0049] This solution is based on the fact that the metal lines of the power ground network have a certain fixed layout pattern. Instead of using the traditional EDA universal command to complete the physical implementation of all through-holes, this solution uses the EDA tool to make the best optimization selection for a limited number of sample scenarios. This optimal selection is applied to all points that need to be implemented in the form of DEF, greatly optimizing the operational implementation and computer resource requirements of the through-hole implementation in the entire power network.

[0050] In addition, the present application is not limited to the scenario where each layer has only one type of layout mode for the power ground network, and can also be applied when some layers have a limited number of types of layout modes.

[0051] In one embodiment, based on the aforementioned embodiment, when the layout pattern information of the metal line level in the power ground network of the integrated circuit has only one type, a first intersecting physical region is determined between each adjacent metal line level where a via hierarchy is required, and a mapping relationship is established. When the layout pattern information of the metal line level in the power ground network of the integrated circuit includes multiple types, a first via is drilled in each intersecting first physical region corresponding to each type of layout pattern information, and a corresponding mapping relationship is established. Furthermore, when the layout pattern information of the metal line level in the power ground network of the integrated circuit includes multiple types, the second physical region between each adjacent metal line level where a via hierarchy is required can be calculated by performing an AND operation.

[0052] In one embodiment, the present application provides a computer device including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the method for drilling a through hole in the aforementioned embodiment.

[0053] In one embodiment, the present application provides a computer storage medium having a computer program or instructions stored thereon. When the computer program or instructions are executed by a processor, the steps of the method for drilling a through hole in the aforementioned embodiment are implemented.

[0054] In one embodiment, the present application provides a computer program product, including a computer program or instructions, which implements the steps of the method for drilling a through hole in the aforementioned embodiment when the computer program or instructions are executed by a processor.

[0055] The hole-drilling method of the present invention can be implemented using program codes executable by a computing device. Thus, the program codes can be stored in a storage device and executed by the computing device, or implemented as separate integrated circuit modules, or multiple modules or steps can be implemented as a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.

[0056] It should be noted that the above embodiments can be freely combined as needed. The above description is only a preferred embodiment of the present invention. It should be pointed out that those skilled in the art can make several improvements and modifications without departing from the principles of the present invention, and such improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for drilling a through hole, applied to EDA design of an integrated circuit, characterized in that: Including steps: Acquire layout pattern information of a metal line layer in a power ground network of an integrated circuit, wherein the layout pattern information includes the width of the metal line and the spacing between adjacent metal lines of the same type; Determine a mutually intersecting first physical region between each adjacent metal line level where a through-hole level is required, and automatically drill a first through-hole in each of the first physical regions using an EDA tool; Recording the through-hole information of the first through-holes, and establishing a mapping relationship between the through-hole level of each first through-hole and the corresponding through-hole information, wherein the through-hole information includes the through-hole type of each first through-hole and the offset information of each first through-hole in the first physical region corresponding to the first through-hole; Calculating each adjacent metal line level that needs to implement the through-hole level in sequence according to the layout pattern information to obtain all second physical areas between each adjacent metal line level that needs to implement the through-hole level; Determining the through-hole types and absolute coordinate information of all through-holes that need to be punched according to the absolute position of the second physical area and the mapping relationship, and recording them in a preset file; During the EDA design process of the integrated circuit, the preset file is directly read, and the through-hole drilling operation is automatically performed through the EDA tool according to the through-hole types and absolute coordinate information of all through-holes required to be drilled recorded in the preset file.

2. A method for punching a through hole according to claim 1, characterized in that: When the layout pattern information of the metal line level in the power ground network of the integrated circuit has only one type, a mutually intersecting first physical area is determined for each adjacent metal line level that needs to implement a through-hole level, and a mapping relationship is established.

3. A method for punching a through hole according to claim 1, characterized in that: When the layout pattern information of the metal line level in the power ground network of the integrated circuit includes multiple types, a first through hole is punched in sequence for each type of mutually intersecting first physical area corresponding to the layout pattern information, and the corresponding mapping relationships are established respectively.

4. A method for punching a through hole according to claim 3, characterized in that: When the layout pattern information of the metal line level in the power ground network of the integrated circuit includes multiple types, each adjacent metal line level that needs to implement the through-hole level is calculated through an AND logic operation to obtain all the second physical areas.

5. A method for punching a through hole according to claim 1, characterized in that: The offset information includes an offset amount of the first through hole in a horizontal direction and a vertical direction relative to a reference point in the first physical area.

6. A method for punching a through hole according to claim 1, characterized in that: The layout of the metal line layers in the power ground network of the integrated circuit is a regular layout, and the width of the metal lines and the intervals between adjacent metal lines of the same type are both fixed values.

7. A method for punching a through hole according to claim 1, characterized in that: The preset file is a DEF file.

8. A computer device comprising a memory, a processor, and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of the method for drilling a through hole according to any one of claims 1 to 7.

9. A computer storage medium having a computer program or instruction stored thereon, characterized in that: When the computer program or instruction is executed by a processor, the steps of the method for drilling a through hole according to any one of claims 1 to 7 are implemented.

10. A computer program product comprising a computer program or instructions, characterized in that When the computer program or instruction is executed by a processor, the steps of the method for drilling a through hole according to any one of claims 1 to 7 are implemented.

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