Circuit layout verification method and system
By performing DC analysis and regulation setting of the circuit layout in the computing device, the problems of circuit layout verification complexity and manual cost determination in the prior art are solved, and fast and effective circuit layout verification is achieved.
Patent Information
- Application Number
- CN202311607995.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-11-14
- Filing Date
- 2023-11-29
- Publication Date
- 2025-05-16
AI Technical Summary
The prior art is difficult to quickly and effectively deal with the design problems in circuit geometric design in circuit layout verification, resulting in a large amount of manual judgment, which increases the working pressure and cost.
By reading the circuit layout in the calculation device, adjusting and setting the component parameters, using DC analysis to calculate the maximum possible voltage and minimum possible values of the conductor segments, and input these values into the preset design specifications, marking the conductor segments that exceed the specifications as abnormal.
This method can quickly reduce computing requirements, simplify the complexity of circuit layout, reduce the time and manual discrimination cost required for verification, and improve the efficiency of circuit design.
Smart Images
Figure CN120012704A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a circuit layout verification method and system, and in particular to a circuit layout verification method and system using a direct current electrical transmission simulation method. Background Art
[0002] In the process of laying out a circuit (e.g., an integrated circuit or a circuit on a board), the design of each circuit trace in the layout needs to consider many parameters before it can be determined. For example, the circuit trace itself and the voltage environment around it in the integrated circuit have a significant impact on the yield and quality of chip manufacturing. The same integrated circuit can lead to performance or physical differences such as energy consumption, yield or performance due to layout differences.
[0003] Therefore, after completing the circuit layout, it is often necessary to use some verification tools to inspect and test the circuit layout according to the design rules to ensure that the actual manufactured chip can have the expected performance and does not cause a decrease in yield due to poor layout. With the evolution of technology, the number of transistors or circuit elements per unit area or volume has increased significantly, resulting in increasingly complex circuit layouts. Therefore, the time required to verify the circuit layout and the computing resources of the computer have also increased significantly.
[0004] In addition, taking the verification tool of integrated circuit layout as an example, the Simulation Program with Integrated Circuit Emphasis (SPICE) is often used to simulate the electrical characteristics of the integrated circuit layout. However, the verification results of SPICE can often only present the design problems of the electrical characteristics in the circuit architecture (Topology) design, and cannot directly use SPICE to present the design problems of the electrical characteristics of the circuit layout in the circuit geometry (Geometry) design. For example, SPICE cannot be used to present the voltage relationship between the layout traces. Therefore, there are still many operations in the circuit geometry design that rely on human judgment. As the design of integrated circuits becomes increasingly complex, conducting such verification processes will cause greater operational pressure on designers or verification.
[0005] As can be seen from the above, in the verification of circuit layout, there are still many problems in the prior art that need to be overcome and solved. Summary of the invention
[0006] Therefore, the present invention proposes a circuit layout verification method and system to effectively solve the problems encountered in the prior art.
[0007] More specifically, one of the objectives of the present invention is to provide a circuit layout verification method and system that is fast and reduces computational requirements.
[0008] One of the purposes of the present invention is to provide a circuit layout verification method and system that can verify design problems in circuit geometry design, so as to reduce the operation cost of manual judgment required in the prior art.
[0009] A preferred specific embodiment according to the present invention is a method for verifying a circuit layout in a computing device. In this embodiment, the circuit layout verification method includes: reading the circuit layout; performing adjustment and setting on the component parameters on the circuit layout; performing a DC analysis on the circuit layout after the adjustment and setting according to the preset voltage value of at least one port on the circuit layout to calculate the maximum possible voltage value and the minimum possible voltage value of the conductor line segment on the circuit layout; and inputting the maximum possible voltage value and the minimum possible voltage value into the preset design specification, wherein when the maximum possible voltage value or the minimum possible voltage value exceeds the preset design specification, the conductor line segment is marked as abnormal. The adjustment and setting is based on the following conditions: the voltage drop between the first and third electrodes of the transistor on the circuit layout is equivalent to the transistor voltage drop, the resistor on the circuit layout is regarded as a short circuit, and the voltage drop between the anode and cathode of the diode on the circuit layout is equivalent to the diode voltage drop.
[0010] In one embodiment, the transistor voltage drop is 0V.
[0011] In one embodiment, the diode voltage drop is 0V.
[0012] In one embodiment, the control setting is further based on: an output terminal of an inverter on the circuit layout is regarded as a predetermined stop point.
[0013] In one embodiment, the control setting is further based on: considering the capacitor on the circuit layout as an open circuit, and considering the inductor on the circuit layout as a short circuit.
[0014] In one embodiment, the control setting is further based on: considering the bipolar junction transistors on the circuit layout as being forward-conducting according to the current direction.
[0015] Another preferred embodiment of the present invention is a circuit layout verification system. In this embodiment, the circuit layout verification system includes a storage unit and a processor coupled to the storage unit. The storage unit is used to store an instruction set and a circuit layout. The processor reads the instruction set to perform the following operations: read the circuit layout; perform adjustment settings for the component parameters on the circuit layout; perform DC analysis on the circuit layout after the adjustment settings according to the preset voltage value of at least one port on the circuit layout to calculate the maximum possible voltage value and the minimum possible voltage value of the conductor line segment on the circuit layout; and input the maximum possible voltage value and the minimum possible voltage value into the preset design specification, wherein when the maximum possible voltage value or the minimum possible voltage value exceeds the preset design specification, the conductor line segment is marked as abnormal. The adjustment setting is based on the following conditions: the first and third poles of the transistor on the circuit layout are equivalent to a transistor voltage drop, the resistor on the circuit layout is regarded as a short circuit, and the anode to cathode of the diode on the circuit layout is equivalent to a diode voltage drop.
[0016] In one embodiment, the transistor voltage drop is 0V.
[0017] In one embodiment, the diode voltage drop is 0V.
[0018] In one embodiment, the regulation setting is further based on: the output end of the inverter on the circuit layout is regarded as the agreed stopping point.
[0019] In one embodiment, the control setting is further based on: considering the capacitor on the circuit layout as an open circuit, and considering the inductor on the circuit layout as a short circuit.
[0020] In one embodiment, the control setting is further based on: considering the bipolar junction transistors on the circuit layout as being forward-conducting according to the current direction.
[0021] Compared to the prior art, the circuit layout verification method and system of the present invention is to perform regulation settings on the components (for example, passive components, diodes, transistors or gates) on the circuit layout. The regulation settings can assign preset parameters to the circuit components. The components with preset parameters are fed back to the original circuit layout for DC analysis. Because the components in the circuit are assigned preset parameters, the complexity of the original circuit layout can be simplified while verifying the maximum and minimum voltages that the circuit can tolerate. Simplifying complexity can effectively reduce the computing resources required by the computer or system and reduce the time required for verification. In addition, the maximum and minimum voltages that the circuit can tolerate are verified and imported into the preset design specifications, and the abnormal positions are marked, which can effectively reduce the operating costs of manual judgment required by the prior art.
[0022] The circuit layout verification method and system of the present invention can simplify the verification process. Compared with the verification tools used in the prior art, the present invention is conducive to the proof of concept (POC) in the early stage of circuit design. In other words, in the POC stage, designers often do not need 100% verification accuracy, but to quickly check out the unreasonable parts in the layout design. Therefore, the circuit layout verification method and system of the present invention that simplifies the verification process can enable layout designers to quickly verify early design results. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] The drawings presented in this disclosure are intended to help describe various embodiments of the present invention. However, in order to simplify the drawings and / or highlight the content to be presented in the drawings, the existing structures and / or elements in the drawings may be drawn in a simple schematic manner or presented in an omitted manner. On the other hand, the number of elements in the drawings may be singular or plural. The drawings presented in this disclosure are only intended to illustrate these embodiments and are not intended to limit them.
[0024] Figure 1 FIG. 4 is a flow chart of a circuit layout verification method in a first specific embodiment of the present invention.
[0025] Figure 2 The control settings of the circuit formed by resistors according to the first specific embodiment.
[0026] Figure 3 The control settings of the circuit formed by transistors according to the first specific embodiment.
[0027] 4A to 4D The control setting of the circuit formed by the diode according to the first specific embodiment.
[0028] Figure 5 The control settings of the circuit using an inverter as an example according to the first specific embodiment.
[0029] Figure 6 The first embodiment is based on the control settings of the circuit formed by passive components.
[0030] Figure 7 It is a schematic diagram of the correspondence between the circuit diagram and the circuit layout diagram according to the first specific embodiment.
[0031] Figure 8 FIG. 4 is a schematic diagram of a system for circuit layout verification according to a second embodiment.
[0032] Description of main component symbols:
[0033] 100 Circuit Layout Verification System
[0034] 110 Processor
[0035] 120 storage units
[0036] C Capacitor
[0037] IS instruction set
[0038] R1, R2 resistors
[0039] T1, T2 transistors
[0040] V DD ,V SS Preset voltage value
[0041] V P ,V P1 ,V P2 ,V P3 Voltage
[0042] V T1 ,V T2 Transistor voltage drop
[0043] V D1 Diode voltage drop
[0044] V R Zener voltage
[0045] V F Diode voltage drop
[0046] L Inductor
[0047] LP conductor segment
[0048] P,P1,P2,P3 nodes
[0049] S1, S2, S3, S4 steps DETAILED DESCRIPTION
[0050] Any reference to elements using names such as "first", "second" and the like in this article does not generally limit the number or order of these elements. On the contrary, these names are used as a convenient way to distinguish two or more elements or element instances in this article. Therefore, it should be understood that the names "first", "second" and the like in the claims do not necessarily correspond to the same names in the written description. In addition, it should be understood that the reference to the first and second elements does not mean that only two elements can be used or that the first element must be before the second element. "Including", "including", "having", "containing" and the like used in this article are all open terms, that is, they mean including but not limited to.
[0051] The term "coupled" is used herein to refer to direct or indirect electrical coupling between two structures. For example, in one example of indirect electrical coupling, one structure may be coupled to another structure via a passive element such as a resistor, capacitor, or inductor.
[0052] In the present invention, the words "exemplary" and "for example" are used to mean "used as an example, instance or illustration". Any implementation or aspect described herein as "exemplary" or "for example" is not necessarily to be construed as preferred or advantageous over other aspects of the present invention. The terms "approximately" and "substantially" as used herein with respect to a specified value or characteristic are intended to mean within a certain value (for example, 10%) of the specified value or characteristic.
[0053] The first specific embodiment of the present invention is a method for verifying a circuit layout in a computing device. In this embodiment, the component parameters on the circuit layout are adjusted and set; according to the preset voltage value of at least one port on the circuit layout, a DC analysis is performed on the circuit layout after the adjustment and setting to calculate the maximum possible voltage value and the minimum possible voltage value of the conductor line segment on the circuit layout; and the maximum possible voltage value and the minimum possible voltage value are input into the preset design specification. Therefore, the computing resources required by the computer or system and the time required for verification can be reduced, and the operation cost of manual judgment required by the prior art can be reduced, but it is not limited to this.
[0054] Please refer to Figure 1 , Figure 1 FIG. 1 is a flow chart of a circuit layout verification method in a first embodiment of the present invention. Figure 1 As shown, the circuit layout verification method includes: (step S1) reading the circuit layout; (step S2) adjusting and setting the component parameters on the circuit layout, wherein the adjustment and setting are based on the following conditions: the first and third electrodes of the transistor on the circuit layout are equivalent to the transistor voltage drop, the resistor on the circuit layout is regarded as a short circuit, and the anode to the cathode of the diode on the circuit layout is equivalent to the diode voltage drop; (step S3) according to the preset voltage value of at least one port on the circuit layout, a DC analysis is performed on the circuit layout after the adjustment and setting to calculate the maximum possible voltage value and the minimum possible voltage value of the conductor line segment on the circuit layout; and (step S4) the maximum possible voltage value and the minimum possible voltage value are input into the preset design specification, wherein when the maximum possible voltage value or the minimum possible voltage value exceeds the preset design specification, the conductor line segment is marked as abnormal.
[0055] With respect to step S1, the present invention is not limited to the type and size level of the circuit. For example, the circuit layout of the present invention is, for example, a nanometer-level integrated circuit layout on a wafer (semiconductor substrate), or a micrometer-level to millimeter-level circuit layout on a printed circuit board (PCB). The circuit layout referred to in the present invention can be, for example, file data exported by designing through existing circuit layout design software (e.g., Cadence, OrCAD, Altium designer). The present invention is not limited to the file format of the circuit layout, and it should be understood that any file format used to describe the circuit layout in any prior art (e.g., Gerber, HSPICE, or any drawing file) can fall within the scope of the present invention. The circuit layout is preferably stored in a storage unit (e.g., a memory, a hard disk, a magnetic disk, or an optical disk) of a computing device (e.g., a computer), and the computing device can read the circuit layout by accessing the storage unit, but is not limited thereto.
[0056] After reading the circuit layout, the type, position and interconnection relationship of each component on the circuit layout can be obtained. In step S2, the component parameters on the circuit layout are adjusted and set. Specifically, each component in the circuit has component parameters that can describe its electrical characteristics. For example, when the component is a resistor, the component parameters are parameters that are considered during DC circuit analysis, such as resistance value, voltage drop across the resistor, or current value flowing through the resistor itself. The read circuit layout can be modified by a computing device. For example, the circuit layout can be read in the form of a hardware description language, and the component parameters on the circuit layout are adjusted and set by adjusting the values or parameters of each component defined in the hardware description language. In the control setting that the first pole and the third pole of the transistor on the circuit layout are equivalent to the transistor voltage drop, specifically, in the control setting of the present invention, the first pole and the third pole of the transistor are the input end and the output end of the corresponding transistor respectively. Taking the existing field effect transistor (FET) as an example, the field effect transistor has three external terminals such as the drain, the gate and the source. Among them, the gate is usually used as the control end of the field effect transistor, and the drain and the source are usually used as the input end or the output end of the field effect transistor. In the circuit layout, the first pole and the third pole of the transistor are regarded as the transistor voltage drop, and the transistor voltage drop can be expressed as the voltage difference between the input end or the output end of the transistor. Thus, the complex transistor circuit can be simplified into a voltage node to simplify the complexity of analysis. In this embodiment, the transistor voltage drop can even be zero volts (0V), thereby further simplifying the complexity of analysis. It should be noted that the present invention is not limited to the type of transistor, and the field effect transistor can be replaced by other transistors, such as a bipolar junction transistor (BJT), a JFET or an IGBT.
[0057] In the control setting of treating the resistors on the circuit layout as short circuits, specifically, the present invention omits the voltage drop of the resistor itself as much as possible. Treating the resistor as a short circuit (the resistance value is regarded as zero ohm) can simplify the number of nodes in the circuit to the greatest extent. It should be noted that when computing resources are more abundant or more accurate DC analysis is required, some resistors can be equivalent to voltage drops. For example, when a resistor greater than a certain resistance value is controlled in the form of a voltage drop, a resistor less than a certain resistance value is directly controlled in the form of a short circuit. In this way, a balance can be achieved between omitting circuit nodes and verifying simulation accuracy, but is not limited to this.
[0058] In the setting of regulating the diode voltage drop between the anode and cathode of the diode on the circuit layout, specifically, the existing diode has two external terminals, the anode and the cathode. By equivalencing the anode and the cathode with the diode voltage drop, the complex diode circuit can be simplified into a voltage node to simplify the analysis complexity. It should be noted that the existing diode can be divided into forward bias and reverse bias. When the diode is forward biased (the anode voltage is greater than the cathode voltage and the voltage difference is greater than the diode's conduction voltage), the diode voltage drop from the anode to the cathode of the diode is the diode's conduction voltage. In this embodiment, the diode voltage drop can even be further simplified to zero volts (0V), thereby further simplifying the complexity of analyzing the diode circuit. When the diode is reverse biased (the anode voltage is less than the cathode voltage), the diode can be regulated and set as a predetermined stop point. In the present invention, the "predetermined stop point" means that the voltages at both ends will not be transmitted to each other. In other words, when the element is an existing diode, only the anode to cathode unidirectional conduction can be considered. However, the regulation setting during reverse bias is not limited thereto. For example, when the diode is a Zener diode and is reverse biased, the equivalent diode voltage drop between the anode and the cathode may be equal to the Zener voltage of the Zener diode.
[0059] In one embodiment, the control setting may also be based on the following conditions: the output end of the inverter on the circuit layout is regarded as the agreed stop point. Specifically, the existing inverter can be composed of one or more transistors, such as an NMOS inverter, a PMOS inverter, a CMOS inverter or a TTL inverter. The output end of the inverter can be regarded as the agreed stop point.
[0060] In one embodiment, the control setting can also be based on the following conditions: the bipolar junction transistor on the circuit layout is considered to be forward-conducting according to the current direction. Specifically, the junction types of existing bipolar junction transistors can be divided into NPN type and PNP type, so the base (Base) to emitter (Emitter) and the base to collector (Collector) of the bipolar junction transistor can be respectively regarded as a diode, so the base to emitter and the base to collector of the bipolar junction transistor can be regarded as forward-conducting and equivalent to a diode voltage drop or regarded as a reverse bias and regarded as a predetermined stop point according to the junction type and current direction of the bipolar junction transistor.
[0061] In one embodiment, the control setting may also be based on the following conditions: the capacitor on the circuit layout is regarded as an open circuit, and the inductor on the circuit layout is regarded as a short circuit. Specifically, as a passive component, the capacitor is an energy storage element in the DC circuit, and the voltage of the capacitor after energy storage is the voltage difference between the two ends of the coupling, so it can be represented as an open circuit (i.e., an agreed stopping point). In direct current analysis, the inductor can be regarded as a wire with extremely low resistance value, so it can be regarded as a short circuit (similar to a resistor). This can also greatly reduce the nodes required for subsequent analysis.
[0062] When the computing device completes the control and setting of some or all of the components in the circuit layout, the controlled circuit layout can be generated. The computing device can perform the analysis steps described in step S3 on the controlled circuit layout.
[0063] Take the circuit composed of resistors as an example, please refer to Figure 2 , Figure 2 The resistors (R1, R2) in step S2 can be regarded as short circuits due to the control setting in step S2, and the maximum possible voltage value (max V) can be calculated for each node (for example, node P) according to the circuit after the control. P ) and the minimum possible voltage (min V P ). Specifically, Figure 2 The preset voltage value (V DD 、V SS ) can be directly transmitted to the node P because the resistors (R1, R2) are set to be short-circuited. At this time, the voltage V P The maximum value (max V P ) will be equal to the preset voltage value (V DD 、V SS ), and the voltage V P The minimum value (min V P ) will be equal to the preset voltage value (V DD 、V SSIt should be noted that the number of preset voltage values can be determined according to the number of ports preset in the circuit and is not limited to Figure 2 In addition, in this DC analysis, the overlap theorem can be used to consider the impact of only one preset voltage value on each node of the circuit at a time, and the remaining preset voltage values can be set to ground. In addition, the calculation can also be simplified by existing circuit calculation methods such as Thevenin's theorem.
[0064] Take the circuit composed of transistors as an example, please refer to Figure 3 , Figure 3 The first transistor (T1) and the second transistor (T2) in the embodiment have already set the voltage drop between the first and third electrodes of the respective transistors to be equivalent to the voltage drop of the first transistor (V T1 ) and the voltage drop of the second transistor (V T2 In step S3, the maximum possible voltage value (max V P ) and the minimum possible voltage (min V P ). Specifically, Figure 3 The preset voltage value (V DD 、V SS ) because the first and second transistors (T1, T2) are equivalent to the first and second transistor voltage drops (V T1 、V T2 ) and the voltage V P With the first and second transistor voltage drops (V T1 、V T2 ) difference. At this time, the voltage V P The maximum value (maxV P ) will be equal to the preset voltage value (V DD ) and the voltage drop of the first transistor (V T1 ) difference (V DD -V T1 ) and the preset voltage value (V SS ) and the voltage drop of the second transistor (V T2 ) and (V SS +V T2 ) whichever has the higher value. On the other hand, the voltage V P The minimum value (min V P ) will be equal to the preset voltage value (V DD ) and the voltage drop of the first transistor (V T1 ) difference (V DD -V T1 ) and the preset voltage value (V SS ) and the voltage drop of the second transistor (VT2 ) and (V SS +V T2 ) whichever has the lower value. It should be noted that Figure 3 In the embodiment shown, only two transistors are connected in series for simplicity of description. When the circuit is modified, those skilled in the art can calculate the maximum possible voltage value (maxV P ) and the minimum possible voltage (min V P In addition, the voltage drop of the first transistor (V T1 ) and the voltage drop of the second transistor (V T2 ) can be set to be the same or different. Specifically, they can be set differently according to the channel lengths of the first and second transistors (T1, T2) or other transistor parameters, but are not limited thereto.
[0065] Take the circuit composed of diodes as an example, please refer to 4A to 4D It should be noted that 4A to 4D In order to simplify the calculation in the embodiment, the preset voltage value (V DD ) will be greater than the preset voltage value (V SS ) and the difference is sufficient to forward bias or reverse bias the diode (D1).
[0066] At Figure 4A In the embodiment shown, the circuit is composed of a diode (D1) and resistors (R1, R2), and the diode (D1) is forward biased. In the regulated circuit, the resistors (R1, R2) are considered to be short-circuited, and the voltage between the anode and cathode of the diode (D1) is equivalent to a diode voltage drop (V D1 In step S3, the maximum possible voltage value and the minimum possible voltage value are calculated for each node (for example, nodes P1 and P2) according to the regulated circuit. Specifically, the voltage V P1 The maximum value (max V P1 ) will be equal to the preset voltage value (V DD ), and the voltage V P1 The minimum value (min V P1 ) will be equal to the preset voltage value (V SS ) and the diode voltage drop (V D1 ) and (V SS +V D1 ). On the other hand, the voltage V at the node P2 P2 The maximum value (maxV P2 ) will be equal to the preset voltage value (V DD ) and the diode voltage drop (V D1 ) difference (V DD-V D1 ), and the voltage V P2 The minimum value (min V P2 ) will be equal to the preset voltage value (V SS ).
[0067] At Figure 4B In the embodiment shown, compared with Figure 4A , the diode (D1) is reverse biased. In the regulated circuit, the resistors (R1, R2) are considered short circuits, and the anode and cathode of the diode (D1) can be considered as "agreed stopping points". Specifically, the voltage V P1 The maximum value (max V P1 ) will be equal to the preset voltage value (V DD ). And, because of the setting of the “agreed stop point”, the voltage V P1 The minimum value (min V P1 ) will be equal to the preset voltage value (V DD ) without being affected by the preset voltage value (V SS ) is affected. Similarly, the voltage V P2 The maximum value (max V P2 ) and minimum value (min V P2 ) will be equal to the preset voltage value (V SS ) without being affected by the preset voltage value (V DD )’s impact.
[0068] At Figure 4C In the embodiment shown, the circuit is formed by a Zener diode (ZD1) and resistors (R1, R2), and the Zener diode (ZD1) is forward biased. Figure 4A The situation is similar to that of the Zener diode (ZD1), which is forward biased. Therefore, the voltage between the anode and cathode of the Zener diode (ZD1) is equivalent to a diode voltage drop (V F ). The voltage V at node P1 P1 The maximum value (maxV P1 ) will be equal to the preset voltage value (V DD ), and the voltage V P1 The minimum value (min V P1 ) will be equal to the preset voltage value (V SS ) and the diode voltage drop (V F ) and (V SS +V F ). On the other hand, the voltage V at the node P2 P2 The maximum value (max V P2 ) will be equal to the preset voltage value (V DD ) and the diode voltage drop (VF ) difference (V DD -V F ), and the voltage V P2 The minimum value (min V P2 ) will be equal to the preset voltage value (V SS ).
[0069] At Figure 4D In the embodiment shown, compared with Figure 4C , the Zener diode (ZD1) is reverse biased. In the regulated circuit, the resistors (R1, R2) are considered to be short circuits, and the Zener diode (ZD1) can be equivalent to a Zener voltage (V R ). The voltage V at node P1 P1 The maximum value (max V P1 ) will be equal to the preset voltage value (V DD ), and the voltage V P1 The minimum value (min V P1 ) will be equal to the preset voltage value (V SS ) and Zener voltage (V R ) and (V SS +V R ). On the other hand, the voltage V at the node P2 P2 The maximum value (max V P2 ) will be equal to the preset voltage value (V DD ) and Zener voltage (V R ) difference (V DD -V R ), and the voltage V P2 The minimum value (min V P2 ) will be equal to the preset voltage value (V SS ).
[0070] Take the circuit composed of resistors as an example, please refer to Figure 5 , in order to simplify the explanation, Figure 5 It is an inverter using a CMOS architecture, but it should be understood that the concept of this embodiment can be applied to various inverters. Specifically, Figure 5 It is a CMOS inverter composed of PMOS (T1) and NMOS (T2). The voltage drop between the first and third electrodes of PMOS (T1) and NMOS (T2) can be equivalent to the voltage drop of the first transistor (V T1 ) and the voltage drop of the second transistor (V T2 ). The output of the CMOS inverter (node P2) is set to the "agreed stop point". In the analysis of step S3, the voltage V P1 The maximum value (max V P1) will be equal to the preset voltage value (V DD ). And, because of the setting of the “agreed stop point”, the voltage V P1 The minimum value (min V P1 ) will be equal to the preset voltage value (V DD ) without being affected by the preset voltage value (V SS ) is affected. Similarly, the voltage V P3 The maximum value (max V P3 ) and minimum value (min V P3 ) will be equal to the preset voltage value (V SS ) without being affected by the preset voltage value (V DD ) is affected. As for node P2, it is necessary to consider the preset voltage value (V DD 、V SS ) and the first transistor voltage drop (V T1 ) and the voltage drop of the second transistor (V T2 ). Therefore, the voltage V at node P2 P2 The maximum value (max V P2 ) will be equal to the preset voltage value (V DD ) and the voltage drop of the first transistor (V T1 ) difference (V DD -V T1 ) and the preset voltage value (V SS ) and the voltage drop of the second transistor (V T2 ) and (V SS +V T2 ) whichever has the higher value. On the other hand, the voltage V P2 The minimum value (min V P2 ) will be equal to the preset voltage value (V DD ) and the voltage drop of the first transistor (V T1 ) difference (V DD -V T1 ) and the preset voltage value (V SS ) and the voltage drop of the second transistor (V T2 ) and (V SS +V T2 ) whichever has the lower value.
[0071] Take the circuit composed of passive components (e.g., capacitor C, inductor L, and resistor R) as an example. Figure 6 .At Figure 6 In the circuit shown, the capacitor C can be regarded as an open circuit, and the resistor R and the inductor L can be regarded as a short circuit. After this setting, the voltage V P1 The maximum value (max V P1 ) will be equal to the preset voltage value (VDD ). And, because the capacitor C is considered to be disconnected (equivalent to the “appointment stop”), the voltage V at the node P1 is P1 The minimum value (min V P1 ) will be equal to the preset voltage value (V DD ) without being affected by the preset voltage value (V SS ) is affected. Similarly, the voltage V between the node P2 and the node P3 P2 The maximum value (max V P2 ) and minimum value (min V P2 ) are the same as each other and equal to the preset voltage value (V SS ) without being affected by the preset voltage value (V DD )’s impact.
[0072] It should be noted that the various embodiments described above are not mutually exclusive, but the control settings disclosed in the embodiments described above can be used in combination according to the complexity of the circuit.
[0073] After performing DC analysis on the circuit layout after the control setting, the maximum possible voltage value and the minimum possible voltage value corresponding to each node on the circuit structure can be obtained. The maximum possible voltage value and the minimum possible voltage value of the conductor line segment on the circuit layout can be marked according to the corresponding relationship between the circuit structure and the circuit layout diagram. For details, please refer to Figure 7 , Figure 7 is a schematic diagram of the correspondence between the circuit architecture diagram and the circuit layout diagram. For example, the node P can be drawn as a conductor line segment LP in the circuit layout diagram. According to step S2 and step S3, the maximum possible voltage value (maxV P ) and the minimum possible voltage (min V P At this time, the maximum possible voltage value (maxV P ) and the minimum possible voltage (min V P ) inputs the preset design specification or compares it with the rules in the design specification to verify whether the line segment LP meets the preset design specification. P ) and the minimum possible voltage (min V P ) exceeds the preset design specifications, the conductor line segment LP can be marked as abnormal.
[0074] The circuit layout verification method of the present invention can assign preset parameters to the components on the circuit layout to simplify the complexity of the original circuit layout. Simplifying the complexity can effectively reduce the computing resources required by the computer or system and reduce the time required for verification. In addition, the maximum and minimum voltages that the circuit can tolerate are verified and imported into the preset design specifications, and the abnormal positions are marked, which can effectively reduce the operating costs of the existing technology that requires manual judgment.
[0075] The second embodiment of the present invention is a circuit layout verification system. In this embodiment, the circuit layout verification system includes a storage unit and a processor coupled to the storage unit. The processor reads an instruction set to execute the circuit layout verification method in the first embodiment of the present application.
[0076] Please refer to Figure 8 , Figure 8 A circuit layout verification system 100 is described. In this embodiment, the circuit layout verification system 100 includes a storage unit 120 and a processor 110 coupled to the storage unit 120. The storage unit 120 is, for example, a data storage medium such as a hard disk, an optical disk, a memory, a register, etc. The processor 110 is, for example, a processing element with computing capabilities such as a central processing unit, a microprocessor, an FPGA, an application specific integrated circuit (ASIC), a single chip system (SoC), etc. The processor 110 executes the various circuit layout verification methods described above by accessing an instruction set IS stored in the storage unit 120. The instruction set IS is, for example, various codes performed in a high-level programming language, but is not limited thereto.
[0077] Compared with the verification tools used in the prior art, the circuit layout verification system 100 of the present invention is advantageous in quickly checking out the unreasonable parts in the layout design, and can enable the layout designer to quickly verify the early design results.
[0078] The previous description of the invention is provided to enable those skilled in the art to make or implement the invention. Various modifications to the invention will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations or the various embodiments may be combined with one another or implemented separately without departing from the spirit or scope of the invention. Therefore, the invention is not intended to be limited to the examples described herein, but rather to the widest scope consistent with the principles and novel features of the invention herein.
Claims
1. A circuit layout verification method, characterized in that: Include: reading a circuit layout; A control setting is performed on the component parameters on the circuit layout, wherein the control setting is based on: The voltage between the first and third electrodes of the transistor on the circuit layout is equivalent to a transistor voltage drop. Treat the resistors on the layout as short circuits, and The voltage between the anode and cathode of the diode on the circuit layout is equivalent to a diode voltage drop; According to a preset voltage value of at least one port on the circuit layout, a DC analysis is performed on the circuit layout after the adjustment setting is performed to calculate a maximum possible voltage value and a minimum possible voltage value of a conductor line segment on the circuit layout; as well as The maximum possible voltage value and the minimum possible voltage value are input into a preset design specification, wherein when the maximum possible voltage value or the minimum possible voltage value exceeds the preset design specification, the conductor line segment is marked as abnormal.
2. The circuit layout verification method according to claim 1, characterized in that: The transistor voltage drop is 0V.
3. The circuit layout verification method according to claim 1, characterized in that: The voltage drop across this diode is 0V.
4. The circuit layout verification method according to claim 1, characterized in that: The control setting is also based on: The output terminal of an inverter on the circuit layout is regarded as a predetermined stopping point.
5. The circuit layout verification method according to claim 1, wherein: The control setting is also based on: Treat the capacitors on the circuit layout as open circuits, and Treat the inductor on this circuit layout as a short circuit.
6. The circuit layout verification method according to claim 1, wherein: The control setting is also based on: The bipolar junction transistors on the circuit layout are considered to be forward conducting according to the current direction.
7. A circuit layout verification system, characterized in that: Include: a storage unit for storing an instruction set and a circuit layout; and A processor coupled to the storage unit, the processor reading the instruction set to perform the following operations: reading a circuit layout; A control setting is performed on the component parameters on the circuit layout, wherein the control setting is based on: The voltage between the first and third electrodes of the transistor on the circuit layout is equivalent to a transistor voltage drop. Treat the resistors on the layout as short circuits, and The voltage between the anode and cathode of the diode on the circuit layout is equivalent to a diode voltage drop; According to a preset voltage value of at least one port on the circuit layout, a DC analysis is performed on the circuit layout after the adjustment setting is performed to calculate a maximum possible voltage value and a minimum possible voltage value of a conductor line segment on the circuit layout; as well as The maximum possible voltage value and the minimum possible voltage value are input into a preset design specification, wherein when the maximum possible voltage value or the minimum possible voltage value exceeds the preset design specification, the conductor line segment is marked as abnormal.
8. The circuit layout verification system according to claim 7, characterized in that: The transistor voltage drop is 0V.
9. The circuit layout verification system according to claim 7, characterized in that: The voltage drop across this diode is 0V.
10. The circuit layout verification system according to claim 7, characterized in that: The control setting is also based on: The output terminal of an inverter on the circuit layout is regarded as a predetermined stopping point.
11. The circuit layout verification system according to claim 7, wherein: The control setting is also based on: Treat the capacitors on the circuit layout as open circuits, and Treat the inductor on this circuit layout as a short circuit.
12. The circuit layout verification system according to claim 7, characterized in that: The control setting is also based on: The bipolar junction transistors on the circuit layout are considered to be forward conducting according to the current direction.