Standard unit feature evaluation method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention discloses a standard cell feature evaluation method and device, electronic equipment and a storage medium, relates to the technical field of integrated circuits, and is convenient for accurately reflecting feature performance of a standard cell. The method comprises the following steps: constructing a logic environment according to an HDL netlist of a standard unit to be evaluated and at least one application scene; forming a target logic implementation path and an optimal logic implementation path for simulating the standard unit to be evaluated based on the logic environment; under a preset feature constraint condition, inputting consistent signal excitation to the target logic implementation path and the optimal logic implementation path; comparing the output result of the target logic implementation path with the output result of the optimal logic implementation path, and evaluating the characteristic performance of the target logic implementation path; wherein the characteristic performance representation of the target logic implementation path reflects whether the characteristic of the standard unit to be evaluated meets an expected value or not. The method is suitable for characteristic evaluation of the standard unit.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a method, device, electronic equipment and storage medium for evaluating standard cell characteristics. Background Art

[0002] In large-scale integrated circuit (IC) design, standard cells are widely used to improve the efficiency of converting chip hardware description language (HDL) into gate-level netlists, and the diversity of standard cells enables designers to flexibly coordinate between performance, area, power consumption and cost to adapt to different application scenarios. Generally speaking, the development of standard cells starts with circuit design, goes through layout design, simulation verification, and finally generates a feature database.

[0003] In related technologies, the performance of standard cell characteristics is generally evaluated from the analysis of the physical layout level, such as through parameter analysis at the physical layout level, abstract mathematical models are used to calculate delays, power consumption, etc., which usually involves the evaluation of the physical layout implementation scheme. However, since the physical layout implementation includes a large number of complex logic standard cells, the evaluation task is large, and there are multiple implementation schemes from complex logic standard cells to the physical layout. In addition, the physical layout implementation scheme may also involve different layout formation process nodes, and the performance of the final physical layout is very different. Therefore, it is difficult to accurately reflect the true performance of the characteristics of the standard cell under different conditions based on the evaluation of the layout of the standard cell characteristic data. Summary of the invention

[0004] In view of this, embodiments of the present invention provide a standard cell characteristic evaluation method, device, electronic device and storage medium, which are convenient for accurately reflecting the characteristic performance of the standard cell.

[0005] In a first aspect, an embodiment of the present invention provides a method for evaluating characteristics of a standard cell, comprising: constructing a logic environment according to an HDL netlist of a standard cell to be evaluated and at least one application scenario; based on the logic environment, forming a target logic implementation path for simulating the standard cell to be evaluated, and forming an optimal logic implementation path; under preset characteristic constraint conditions, inputting consistent signal stimuli to the target logic implementation path and the optimal logic implementation path respectively; evaluating the characteristic performance of the target logic implementation path by comparing the output result of the target logic implementation path with the output result of the optimal logic implementation path; wherein the characteristic performance characterization of the target logic implementation path reflects whether the characteristics of the standard cell to be evaluated meet the expected values.

[0006] In one embodiment, a logic environment is constructed according to an HDL netlist of a standard unit to be evaluated and at least one application scenario, including: obtaining the HDL netlist of the standard unit to be evaluated to form an evaluated module, wherein the evaluated module is used to simulate the logic function of the standard unit to be evaluated; constructing a driver module and a load module according to the application scenario, wherein the driver module is used to generate an input signal stimulus, and the load module is used to simulate the load condition of the output terminal; connecting the driver module to the input terminal of the evaluated module, and connecting the load module to the output terminal of the evaluated module to form an evaluation logic environment.

[0007] In one embodiment, the application scenarios include: input flip time and load capacitance extracted from a feature data table, or input flip time and output load status obtained based on HDL synthesis results of an integrated circuit and statistics in a gate-level netlist after layout and routing.

[0008] In one embodiment, the forming of the target logic implementation path includes: based on the logic environment, obtaining basic standard cells from the standard cell library, and forming the target logic implementation path according to the target logic implementation construction of the standard cell to be evaluated; the forming of the optimal logic implementation path includes: based on the logic environment, obtaining basic standard cells from the standard cell library, and forming the optimal logic implementation path according to the optimal logic implementation construction of the standard cell to be evaluated; wherein the optimal logic implementation path is used to characterize the best characteristic performance of the standard cell to be evaluated under predetermined characteristic constraint conditions, so as to serve as a reference standard for characteristic performance evaluation of the standard cell to be evaluated.

[0009] In one implementation, the preset characteristic constraint condition includes at least one of delay time, flip time, dynamic power consumption, static power consumption, unit driving capability, area occupancy, and clock signal frequency.

[0010] In one embodiment, the signal stimulus includes: an ideal rising or falling signal, a signal generated by an actual standard cell in a high-frequency application, or an equivalent driving signal composed of basic standard cells in a standard cell library.

[0011] In one embodiment, comparing the output result of the target logic implementation path with the output result of the optimal logic implementation path to evaluate the characteristic performance of the target logic implementation path includes: comparing the output result of the target logic implementation path with the output result of the optimal logic implementation path; if the output result of the target logic implementation path is the same as the output result of the optimal logic implementation path, or is better than the output result of the optimal logic implementation path, determining that the characteristic performance of the target logic implementation path meets the expected value.

[0012] In one embodiment, after comparing the output result of the target logic implementation path with the output result of the optimal logic implementation path, it also includes: if it is determined that the characteristic performance of the target logic implementation path does not meet the expected value, iteratively optimizing the characteristic parameters of the tested evaluation standard unit until the output evaluation result representation reflects that the characteristics of the tested evaluation unit meet the expected value.

[0013] In one embodiment, the comparing the output result of the target logic implementation path with the output result of the optimal logic implementation path to evaluate the characteristic performance of the target logic implementation path also includes: extracting each characteristic data from the output results of the target logic implementation path and the optimal logic implementation path respectively; configuring a corresponding weight value for each characteristic data according to the application scenario and characteristic constraint conditions of the standard unit to be evaluated; and comparing the weighted comprehensive value of the characteristic data in the output result of the target logic implementation path with the weighted comprehensive value of the characteristic data in the output result of the optimal logic implementation path to evaluate the characteristic performance of the target logic implementation path.

[0014] In one embodiment, before constructing a logic environment, it includes: constructing a standard cell library according to a specified process node environment, wherein the standard cell library at least includes a set of basic standard cells composed of basic logic cells, and characteristic data corresponding to the basic standard cells; and constructing the standard cell to be evaluated according to user instructions, and generating characteristic data of the standard cell to be evaluated; and defining an application scenario of each standard cell to be evaluated.

[0015] In a second aspect, an embodiment of the present invention further provides a standard cell feature evaluation device, comprising: a construction unit, for constructing a logic environment according to an HDL netlist of a standard cell to be evaluated and at least one application scenario; a formation unit, for forming a target logic implementation path that simulates the standard cell to be evaluated based on the logic environment, and for forming an optimal logic implementation path; an input unit, for inputting consistent signal stimuli to the target logic implementation path and the optimal logic implementation path respectively under preset feature constraints; an evaluation unit, for comparing an output result of the target logic implementation path with an output result of the optimal logic implementation path, and evaluating the feature performance of the target logic implementation path; wherein the feature performance characterization of the target logic implementation path reflects whether the standard cell to be evaluated meets the expected value.

[0016] In one embodiment, the construction unit includes: a first acquisition module, used to acquire the HDL netlist of the standard unit to be evaluated to form an evaluated module, and the evaluated module is used to simulate the logical function of the standard unit to be evaluated; a construction module, used to construct a driving module and a load module according to the application scenario, the driving module is used to generate input signal excitation, and the load module is used to simulate the load condition of the output end; a connection module, used to connect the driving module to the input end of the evaluated module, and to connect the load module to the output end of the evaluated module to form an evaluation logic environment.

[0017] In one embodiment, the formation unit includes: a first formation module, which is used to obtain basic standard cells from a standard cell library based on the logic environment, and form the target logic implementation path according to the target logic implementation construction of the standard cell to be evaluated; a second formation module, which is used to obtain basic standard cells from a standard cell library based on the logic environment, and form the optimal logic implementation path according to the optimal logic implementation construction of the standard cell to be evaluated; wherein the optimal logic implementation path is used to characterize the best feature performance of the standard cell to be evaluated under predetermined feature constraints, so as to serve as a reference standard for feature performance evaluation of the standard cell to be evaluated.

[0018] In one embodiment, the evaluation unit includes: a comparison module, which is used to compare the output result of the target logic implementation path with the output result of the optimal logic implementation path; a determination module, which is specifically used to determine that the characteristic performance of the target logic implementation path meets the expected value if the output result of the target logic implementation path is the same as the output result of the optimal logic implementation path, or is better than the output result of the optimal logic implementation path; an optimization module, which is specifically used to iteratively optimize the characteristic parameters of the evaluated standard unit under test if it is determined that the characteristic performance of the target logic implementation path does not meet the expected value, until the output evaluation result representation reflects that the characteristics of the evaluated unit under test meet the expected value.

[0019] In one embodiment, the evaluation unit also includes: an extraction module, which is used to extract each feature data from the output results of the target logic implementation path and the optimal logic implementation path; a configuration module, which is used to configure a corresponding weight value for each feature data according to the application scenario and feature constraint conditions of the standard unit to be evaluated; and a comparison module, which is used to compare the weighted comprehensive value of the feature data in the output results of the target logic implementation path with the weighted comprehensive value of the feature data in the output results of the optimal logic implementation path, so as to evaluate the feature performance of the target logic implementation path.

[0020] In a third aspect, an embodiment of the present invention further provides an electronic device, comprising: a housing, a processor, a memory, a circuit board and a power supply circuit, wherein the circuit board is placed inside the space enclosed by the housing, and the processor and the memory are arranged on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to execute the method for standard cell feature evaluation provided in any embodiment of the present invention.

[0021] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the method for standard cell feature evaluation provided by any embodiment of the present invention.

[0022] The method, device, electronic device and storage medium for evaluating the characteristics of a standard cell provided by an embodiment of the present invention form a target logic implementation path for simulating the standard cell to be evaluated based on a logical environment, and form an optimal logic implementation path; compare the output result of the target logic implementation path with the output result of the optimal logic implementation path to evaluate the characteristic performance of the target logic implementation path. In this way, since this solution starts from the characteristic data of the standard cell, there is no need to evaluate from the physical layout level, and compare the output result of the target logic implementation path with the output result of the optimal logic implementation path, so as to accurately reflect the characteristic performance of the standard cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 A flow chart of an evaluation method provided by an embodiment of the present invention; Figure 2 A schematic diagram of selectable components of a load module in an evaluation system in an embodiment of the present invention; Figure 3 A schematic diagram of the logical structure of an evaluation system in an embodiment of the present invention; Figure 4 A schematic diagram of selectable components of feature constraints in an evaluation system in an embodiment of the present invention; Figure 5 A schematic diagram of selectable components of a driving module in an evaluation system in an embodiment of the present invention; Figure 6 A detailed flow chart of an evaluation method provided by an embodiment of the present invention; Figure 7 A schematic diagram of a structure of an evaluation device provided by an embodiment of the present invention; Figure 8 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0026] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] In order to enable those skilled in the art to better understand the technical concept, implementation plan and beneficial effects of the embodiments of the present application, specific embodiments are described in detail below.

[0028] In a first aspect, an embodiment of the present invention provides a method for evaluating the characteristics of a standard cell, which directly analyzes and evaluates the characteristic data of the standard cell, so as to accurately reflect the characteristic performance of the standard cell.

[0029] like Figure 1 As shown, an embodiment of the present invention provides a standard cell feature evaluation method, comprising: S11, constructing a logic environment according to the HDL netlist of the standard unit to be evaluated and at least one application scenario; In an embodiment of the present invention, a logic environment can be constructed by a logic synthesis tool or a software environment built by an engineer. In one example, the logic synthesis tool can be a DC (Design Compiler). The HDL netlist of the standard cell to be evaluated and the typical application scenario of the standard cell to be evaluated are imported into the logic synthesis tool to construct a logic environment, and a characteristic data evaluation system of the standard cell library is established under the logic environment. Among them, the number of standard cells to be evaluated is at least one, and the standard cell to be evaluated is an arbitrary standard cell; according to the different standard cells to be evaluated and the different characteristic data of the standard cells to be evaluated, the typical application scenario of the standard cell to be evaluated is modified.

[0030] S12, based on the logic environment, forming a target logic implementation path for simulating the standard unit to be evaluated, and forming an optimal logic implementation path; After the logic environment is built, according to the imported characteristic data of the standard cell to be evaluated and the relevant data of the template cell library, based on the selectable standard cell library, under the constraints of some characteristic data, the target logic implementation path and the optimal logic implementation path of the standard cell to be evaluated are formed with the standard cell as the smallest unit.

[0031] S13, under preset characteristic constraint conditions, inputting consistent signal stimulation to the target logic implementation path and the optimal logic implementation path respectively; Get feature data from the selectable standard cell library, and select relevant constraints as preset feature constraints based on the feature data content. Generally, the preset feature constraints are relatively critical values. For example, if the delay time is used as a preset feature constraint, the optimal delay time is 50 ps, ​​and the preset delay time should be close to 50 ps. According to the actual project, the value closest to 50 ps is selected, such as 49 ps or 48 ps.

[0032] Under preset feature constraints, the same signal stimulus is input from the input end to the target logic implementation path and the optimal logic implementation path, and the two paths are waited for to output results. The input signal stimulus type is different depending on the typical application scenario. In some examples, the signal stimulus can be virtual.

[0033] S14, comparing the output result of the target logic implementation path with the output result of the optimal logic implementation path, evaluating the characteristic performance of the target logic implementation path; wherein the characteristic performance characterization of the target logic implementation path reflects whether the characteristics of the standard unit to be evaluated meet the expected value.

[0034] The output result of the target logic implementation path and the output result of the optimal logic implementation path are obtained from the output end, and the difference in the result parameters is compared to evaluate the characteristic performance of the target logic implementation path. The characteristic performance of the target logic implementation path reflects the characteristics of the standard unit to be evaluated. For example, the characteristic performance of the target logic implementation path is the signal flip time, and the smaller signal flip time is the optimal value. When the signal flip time of the target logic implementation path is better than the signal flip time of the optimal logic implementation path, it is considered that the characteristic performance of the standard unit to be evaluated is more optimized.

[0035] The standard cell feature evaluation method provided by the embodiment of the present invention forms a target logic implementation path for simulating the standard cell to be evaluated based on the logic environment, and forms an optimal logic implementation path; compares the output result of the target logic implementation path with the output result of the optimal logic implementation path, and evaluates the characteristic performance of the target logic implementation path. In this way, since the present solution starts from the standard cell feature data, there is no need to evaluate from the physical layout level, and compares the output result of the target logic implementation path with the output result of the optimal logic implementation path, so as to accurately reflect the characteristic performance of the standard cell.

[0036] In some examples, a logic environment is constructed based on an HDL netlist of a standard unit to be evaluated and at least one application scenario, including: obtaining an HDL netlist of the standard unit to be evaluated to form an evaluated module, wherein the evaluated module is used to simulate the logic function of the standard unit to be evaluated; constructing a driver module and a load module according to the application scenario, wherein the driver module is used to generate an input signal stimulus, and the load module is used to simulate a load condition at an output end; connecting the driver module to an input end of the evaluated module, and connecting the load module to an output end of the evaluated module to form an evaluation logic environment.

[0037] Whether it is based on a logic synthesis tool or a software environment built by an engineer, the evaluation system established by the logic environment includes the module to be evaluated, the driver module and the load module. The three modules are built on the logic simulator and written in the form of a HDL netlist. In one example, the logic simulator can be a txt (text file).

[0038] The HDL of the standard cell to be evaluated is extracted or directly referenced to form an evaluated module. The HDL netlist of the evaluated module can be consistent with the standard cell to be evaluated, or a combination of multiple HDLs of the same standard cell. The evaluated module can be used to simulate the logical function of the standard cell to be evaluated, and the target logic implementation path and the optimal logic implementation path of the standard cell to be evaluated are formed in the evaluated module.

[0039] Figure 2 The load module in the evaluation system can be selected as a component diagram. According to the defined typical application scenarios, the driver module and the load module are constructed, where Figure 2 As shown, the optional components of the load module include but are not limited to: a fixed capacitance value, an equivalent load module composed of basic standard units, an equivalent load composed of a combination of capacitance and resistance models, etc.

[0040] The input signal stimulus is generated by the driving module and input into the target logic implementation path and the optimal logic implementation path of the standard unit to be evaluated of the module to be evaluated, while the load module is used to simulate the load condition of the output end, and the output result is output by the load module.

[0041] Figure 3 The logical structure diagram of the evaluation system is as follows: Figure 3 As shown, the driving module is directly connected to one or more input terminals of the evaluated module, and each output terminal of the evaluated module is directly connected to one or more complex load modules to form an evaluation logic environment.

[0042] In some examples, the application scenarios include: input flip time and load capacitance extracted from a feature data table, or input flip time and output load status obtained based on HDL synthesis results of an integrated circuit and statistics in a gate-level netlist after layout and routing.

[0043] When defining an application scenario, the application scenario data can be derived from the following data: given input flip time and load capacitance in the characteristic data table, fitting results of given input flip time and load capacitance in the characteristic data table. In one example, the characteristic data table is .lib data; in the HDL synthesis results of the large-scale integrated circuit, the flip time of each input terminal of the unit and the load condition of the output terminal are counted, and the typical value is calculated; in the gate-level netlist after the layout and routing of the large-scale integrated circuit, the flip time of each input terminal of the unit to be evaluated and the load condition of the output terminal are counted, and the typical value is calculated; randomly designed input flip time and load impedance. Application scenario data is not limited to the above sources. The standard unit to be evaluated in a specific project can also have other data as the source of application scenario data.

[0044] In some examples, forming a target logic implementation path includes: based on the logic environment, obtaining basic standard cells from a standard cell library, and forming the target logic implementation path according to the target logic implementation construction of the standard cell to be evaluated; forming an optimal logic implementation path includes: based on the logic environment, obtaining basic standard cells from a standard cell library, and forming the optimal logic implementation path according to the optimal logic implementation construction of the standard cell to be evaluated; wherein the optimal logic implementation path is used to characterize the best feature performance of the standard cell to be evaluated under predetermined feature constraints, so as to serve as a reference standard for feature performance evaluation of the standard cell to be evaluated.

[0045] Based on the established logic environment, the standard cell library and the data of the standard cell to be evaluated are imported, and the target logic implementation path is constructed using the logic synthesis tool according to the target logic of the standard cell to be evaluated; according to the optimal logic implementation of the standard cell to be evaluated, the required parameters are set to the optimal values, and the optimal logic implementation path is constructed using the logic synthesis tool. In some examples, the logic synthesis tool can be Synopsys's DC (design compiler) and FC (Fusion compiler); the data used in the logic synthesis includes but is not limited to the HDL of the cell to be evaluated, the SDC (design constraints) corresponding to the typical application scenarios, and the feature data of the template cell library and the basic standard cell library.

[0046] In some examples, the preset feature constraint condition includes at least one of delay time, flip time, dynamic power consumption, static power consumption, unit driving capability, area occupancy, and clock signal frequency.

[0047] Figure 4 To evaluate the characteristic constraints in the system, a component diagram can be selected, such as Figure 4 As shown, according to the characteristic data content, relevant constraints are selected as preset characteristic constraint conditions, and the relevant constraints may be delay time, flip time, dynamic power consumption, static power consumption, maximum driving capability of the unit, area occupied, clock signal frequency, etc. The preset characteristic constraint conditions are generally relatively critical values, and the critical values ​​of the above characteristics can be obtained from the following results: simulation calculation generation; given characteristic values ​​in the overall module characteristic data table, in some examples, the overall module characteristic data table is .lib data or .db data; when defining the typical application scenario of the standard unit to be evaluated, the statistical value of the calculation result of the HDL synthesis process of the large-scale integrated circuit; when defining the typical application scenario of the standard unit to be evaluated, the statistical value of the calculation structure of the gate-level netlist after the layout and routing of the large-scale integrated circuit; the characteristic value of the standard unit to be evaluated; random generation, etc.

[0048] In some examples, the signal stimulus includes: an ideal rising or falling signal, a signal generated by an actual standard cell in a high-frequency application, or an equivalent driving signal composed of basic standard cells in a standard cell library.

[0049] The input signal stimulus is generated by the driver module. There is no restriction on the tool for writing the stimulus. In an example, the signal stimulus can be generated by python. The signal stimulus is generally a typical PWL file. Figure 5 To evaluate the driver module in the system, you can select the component schematic, such as Figure 5 As shown, the selectable components of the signal excitation include but are not limited to: an ideal rising or falling signal, a specific standard unit used at a high frequency, an equivalent driving module composed of basic standard units, etc.

[0050] In some examples, comparing the output result of the target logic implementation path with the output result of the optimal logic implementation path to evaluate the characteristic performance of the target logic implementation path includes: comparing the output result of the target logic implementation path with the output result of the optimal logic implementation path; if the output result of the target logic implementation path is the same as the output result of the optimal logic implementation path, or is better than the output result of the optimal logic implementation path, determining that the characteristic performance of the target logic implementation path meets the expected value.

[0051] The output result of the target logic implementation path and the output result of the optimal logic implementation path are obtained by the load module, and the characteristic data of the output results are compared. Among the relevant characteristic data, the output result of the target logic implementation path is more optimized than the optimal value or is the same as the output result of the optimal logic implementation path, indicating that the characteristic performance of the target logic implementation path is relatively optimized, and it is determined that the characteristic performance of the target logic implementation path meets the expected value.

[0052] For example, characteristic data (such as power consumption) of the output results are extracted from the test results of the target logic implementation path and the optimal logic implementation path. If the power consumption of the target logic implementation path and the power consumption of the optimal logic implementation path are the same or smaller, it means that the characteristic performance of the target logic implementation path is relatively optimized, and it is determined that the characteristic performance of the target logic implementation path meets the expected value.

[0053] In some examples, after comparing the output result of the target logic implementation path with the output result of the optimal logic implementation path, it also includes: if it is determined that the characteristic performance of the target logic implementation path does not meet the expected value, iteratively optimizing the characteristic parameters of the tested evaluation standard unit until the output evaluation result representation reflects that the characteristics of the tested evaluation unit meet the expected value.

[0054] The output result of the target logic implementation path and the output result of the optimal logic implementation path are obtained by the load module, and the characteristic data of the output results are compared. In the relevant characteristic data, the output result of the target logic implementation path is very different from the optimal value data, indicating that the characteristic performance of the target logic implementation path is relatively poor, and it is determined that the characteristic of the target logic implementation path cannot meet the expected value. In the test results of the target logic implementation path and the optimal logic implementation path, the characteristic parameters with a large difference from the optimal value characteristic data continue to be optimized and evaluated again. If the output result still does not meet the expected value, continue to optimize, and iterate in this way until the output evaluation result characterizes the characteristics of the evaluation unit under test and meets the expected value.

[0055] In some examples, comparing the output result of the target logic implementation path with the output result of the optimal logic implementation path to evaluate the characteristic performance of the target logic implementation path further includes: Extract each feature data from the output results of the target logic implementation path and the optimal logic implementation path respectively; configure a corresponding weight value for each feature data according to the application scenario and feature constraint conditions of the standard unit to be evaluated; compare the weighted comprehensive value of the feature data in the output results of the target logic implementation path with the weighted comprehensive value of the feature data in the output results of the optimal logic implementation path to evaluate the feature performance of the target logic implementation path.

[0056] From the output results of the target logic implementation path and the optimal logic implementation path, extract each feature data and formulate the evaluation standard. The extracted feature data include: the sign-off frequency of the whole module; the rise and fall delay time between two nodes in the module; the dynamic power consumption between two nodes; the rise and fall flip time of the output end of the evaluated module; the dynamic power consumption of the whole module; the static power consumption of the whole module, the area occupied by the evaluated module, etc. The component feature data of the evaluation standard can be selected from the following aspects: pursuing a higher sign-off frequency; pursuing a smaller delay time; pursuing a smaller signal flip time; pursuing a smaller dynamic power consumption; pursuing a smaller static power consumption; pursuing a smaller area occupied, etc.

[0057] Since the priority of the constituent characteristic data of the evaluation criteria is different when evaluating different standard units to be evaluated, the corresponding weight values ​​are configured for the constituent characteristic data of the evaluation criteria according to the application scenarios and characteristic constraints of the standard units to be evaluated, so as to quantify the characteristic performance of the target logic implementation path. For example, from the test results of the target logic implementation path and the optimal logic implementation path, various characteristic data (such as delay, power consumption, driving capability, area occupancy, etc.) are extracted, and the weight values ​​of different characteristics are set according to the design requirements and specific characteristic constraints. The weight value determines the influence of each feature in the final comprehensive evaluation. For example, if the delay is critical to the design performance, a higher weight value can be given to the delay, while the power consumption may need to be reduced in some application scenarios. Since the impact of different characteristics (such as delay, power consumption, driving capability, etc.) on the final design performance may be different, a more accurate evaluation result is obtained. The flexibility of the evaluation and the ability of multi-dimensional analysis can be enhanced, especially in performance evaluation, the impact of different characteristics (such as delay, power consumption, driving capability, etc.) on the final design may be different.

[0058] The characteristic data is configured with corresponding weight values ​​to form a complete evaluation standard. According to the established evaluation standard, the weighted comprehensive value of the characteristic data in the output result of the target logic implementation path is compared with the weighted comprehensive value of the characteristic data in the output result of the optimal logic implementation path, and the difference in the output results is compared to evaluate the quality of the characteristic performance of the target logic implementation path. In some examples, before constructing the logic environment, it includes: constructing a standard cell library according to a specified process node environment, the standard cell library at least includes a set of basic standard cells composed of basic logic cells, and characteristic data corresponding to the basic standard cells; specifically, in a specified process node environment, for example: in a specific process technology, a group of basic standard cells are developed, and these basic standard cells are some basic cells with simple logical functions, such as AND gates, OR gates, inverters, etc. Among them, the basic standard cell design should cover a variety of driving capabilities and transistor types, and at least cover the logical implementation combinations of all standard cells to be evaluated. The characteristic data corresponding to the basic standard cell can be used as its characteristic data when forming the optimal logic implementation path, and used as the evaluation reference standard value of the standard cell to be evaluated, to ensure that the subsequent evaluation is consistent and standardized.

[0059] And, constructing the standard unit to be evaluated according to the user instruction, and generating characteristic data of the standard unit to be evaluated; and defining the application scenario of the standard unit to be evaluated for each standard unit to be evaluated.

[0060] Specifically, developers design the standard cells to be evaluated through forward development and generate corresponding feature data. Of course, they can also import relevant feature data of existing standard cells from the existing standard cell library according to requirements. It should be noted that in addition to the aforementioned set of basic standard cells, the standard cell library can also include standard cells with basic functional circuits built based on the basic standard cells. The feature data may include logical functions, driving capabilities, power consumption, etc., which are determined according to actual design requirements.

[0061] Specifically, before building the logic environment, you can directly import the template standard cell and the standard cell to be evaluated to generate data related to the standard cell library, or directly import the standard cell library related feature data of the unit to be evaluated. The feature data of the template cell can be used as a reference value for the unit to be evaluated in subsequent operations. The template standard cell has a variety of simpler logic functions and corresponds to a variety of driving capabilities and transistor types. At the same time, the maximum combination of the logic, driving capability, and transistor type of the template standard cell should cover the target logic implementation of all standard cells to be evaluated.

[0062] Other cells in the standard cell library can also be used as standard cells to be evaluated. If the standard cell to be evaluated is evaluated as qualified, the standard cell to be evaluated can also expand the template standard cell library for further iteration. In this way, a logical environment is constructed, and the standard cell library feature data evaluation system established under this logical environment is an adaptive standard cell feature evaluation system that is not limited by process nodes and design rules.

[0063] The standard unit evaluation method provided by the embodiment of the present invention is described in detail below through a specific embodiment.

[0064] like Figure 6 As shown, the standard cell characteristic evaluation method provided by the embodiment of the present invention may include: S201, generating library-related characteristic data for a template standard cell, where the library-related characteristic data includes a basic standard cell; S202, generating library-related feature data for the standard unit to be evaluated or directly importing the existing library-related feature data of the standard unit to be evaluated; S203, defining typical application scenarios of the standard unit to be evaluated; S204, constructing a logic environment according to the HDL netlist of the standard unit to be evaluated and at least one application scenario; S205, based on the logic environment, forming a target logic implementation path for simulating the standard unit to be evaluated, and forming an optimal logic implementation path; S206, extracting each feature data from the output results of the target logic implementation path and the optimal logic implementation path; configuring a corresponding weight value for each feature data according to the application scenario and feature constraint conditions of the standard unit to be evaluated; S207, comparing the weighted comprehensive value of the characteristic data in the output result of the target logic implementation path with the weighted comprehensive value of the characteristic data in the output result of the optimal logic implementation path, and evaluating the characteristic performance of the target logic implementation path; S208. If the output result of the target logic implementation path is the same as the output result of the optimal logic implementation path, or is better than the output result of the optimal logic implementation path, it is determined that the characteristic performance of the target logic implementation path meets the expected value; S209: If it is determined that the characteristic performance of the target logic implementation path does not meet the expected value, iteratively optimize the characteristic parameters of the tested evaluation standard unit until the output evaluation result characterizes that the characteristic of the tested evaluation unit meets the expected value.

[0065] In a second aspect, an embodiment of the present invention provides a standard cell characteristic evaluation device, which is convenient for accurately reflecting the characteristic performance of a standard cell.

[0066] like Figure 7 As shown, an embodiment of the present invention further provides a standard cell feature evaluation device, comprising: A construction unit 31, configured to construct a logic environment according to an HDL netlist of a standard unit to be evaluated and at least one application scenario; A forming unit 32, configured to form a target logic implementation path for simulating the standard cell to be evaluated based on the logic environment, and to form an optimal logic implementation path; An input unit 33 is used to input consistent signal stimulation to the target logic implementation path and the optimal logic implementation path respectively under preset feature constraint conditions; The evaluation unit 34 is used to compare the output result of the target logic implementation path with the output result of the optimal logic implementation path to evaluate the characteristic performance of the target logic implementation path; wherein the characteristic performance of the target logic implementation path reflects whether the standard unit to be evaluated meets the expected value.

[0067] The standard cell feature evaluation device provided by the embodiment of the present invention forms a target logic implementation path for simulating the standard cell to be evaluated based on the logic environment, and forms an optimal logic implementation path; compares the output result of the target logic implementation path with the output result of the optimal logic implementation path, and evaluates the characteristic performance of the target logic implementation path. In this way, since the present solution starts from the standard cell feature data, there is no need to evaluate from the physical layout level, and compares the output result of the target logic implementation path with the output result of the optimal logic implementation path, so as to accurately reflect the characteristic performance of the standard cell.

[0068] In one embodiment, the construction unit 31 includes: a first acquisition module, used to acquire the HDL netlist of the standard unit to be evaluated to form an evaluated module, and the evaluated module is used to simulate the logical function of the standard unit to be evaluated; a construction module, used to construct a driving module and a load module according to the application scenario, the driving module is used to generate input signal excitation, and the load module is used to simulate the load condition of the output end; a connection module, used to connect the driving module to the input end of the evaluated module, and to connect the load module to the output end of the evaluated module to form an evaluation logic environment.

[0069] In one embodiment, the formation unit includes: a first formation module, which is used to obtain basic standard cells from a standard cell library based on the logic environment, and form the target logic implementation path according to the target logic implementation construction of the standard cell to be evaluated; a second formation module, which is used to obtain basic standard cells from a standard cell library based on the logic environment, and form the optimal logic implementation path according to the optimal logic implementation construction of the standard cell to be evaluated; wherein the optimal logic implementation path is used to characterize the best feature performance of the standard cell to be evaluated under predetermined feature constraints, so as to serve as a reference standard for feature performance evaluation of the standard cell to be evaluated.

[0070] In one embodiment, the evaluation unit includes: a comparison module, which is used to compare the output result of the target logic implementation path with the output result of the optimal logic implementation path; a determination module, which is specifically used to determine that the characteristic performance of the target logic implementation path meets the expected value if the output result of the target logic implementation path is the same as the output result of the optimal logic implementation path, or is better than the output result of the optimal logic implementation path; an optimization module, which is specifically used to iteratively optimize the characteristic parameters of the evaluated standard unit under test if it is determined that the characteristic performance of the target logic implementation path does not meet the expected value, until the output evaluation result representation reflects that the characteristics of the evaluated unit under test meet the expected value.

[0071] In one embodiment, the evaluation unit also includes: an extraction module, which is used to extract each feature data from the output results of the target logic implementation path and the optimal logic implementation path; a configuration module, which is used to configure a corresponding weight value for each feature data according to the application scenario and feature constraint conditions of the standard unit to be evaluated; and a comparison module, which is used to compare the weighted comprehensive value of the feature data in the output results of the target logic implementation path with the weighted comprehensive value of the feature data in the output results of the optimal logic implementation path, so as to evaluate the feature performance of the target logic implementation path.

[0072] In a third aspect, an embodiment of the present invention further provides an electronic device that is convenient for accurately reflecting the characteristic performance of a standard unit.

[0073] like Figure 8 As shown, the electronic device provided by an embodiment of the present invention may include: a housing 51, a processor 52, a memory 53, a circuit board 54 and a power supply circuit 55, wherein the circuit board 54 is arranged inside the space enclosed by the housing 51, and the processor 52 and the memory 53 are arranged on the circuit board 54; the power supply circuit 55 is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory 53 is used to store executable program codes; the processor 52 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 53, so as to execute the evaluation method provided by any of the aforementioned embodiments.

[0074] The specific execution process of the above steps by the processor 52 and the steps further executed by the processor 52 by running the executable program code can be found in the description of the previous embodiment, which will not be repeated here.

[0075] In the fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, which stores one or more programs, and the one or more programs can be executed by one or more processors to implement any evaluation method provided by the aforementioned embodiments, thereby also being able to achieve the corresponding technical effects, which have been described in detail above and will not be repeated here.

[0076] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0077] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0078] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0079] For the convenience of description, the above device is described by dividing the functions into various units / modules. Of course, when implementing the present invention, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0080] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0081] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A standard cell characteristic evaluation method, characterized in that: include: Building a logic environment based on the HDL netlist of the standard unit to be evaluated and at least one application scenario; Based on the logic environment, forming a target logic implementation path that simulates the standard unit to be evaluated, and forming an optimal logic implementation path; Under preset characteristic constraints, inputting consistent signal stimulation to the target logic implementation path and the optimal logic implementation path respectively; The output result of the target logic implementation path is compared with the output result of the optimal logic implementation path to evaluate the characteristic performance of the target logic implementation path; wherein the characteristic performance characterization of the target logic implementation path reflects whether the characteristics of the standard unit to be evaluated meet the expected value.

2. The method according to claim 1, characterized in that: Constructing a logic environment based on the HDL netlist of the standard unit to be evaluated and at least one application scenario, including: Obtaining an HDL netlist of the standard cell to be evaluated to form an evaluated module, wherein the evaluated module is used to simulate the logic function of the standard cell to be evaluated; According to the application scenario, a driving module and a load module are constructed, wherein the driving module is used to generate input signal excitation, and the load module is used to simulate the load condition of the output end; The driving module is connected to the input terminal of the module to be evaluated, and the load module is connected to the output terminal of the module to be evaluated, so as to form an evaluation logic environment.

3. The method according to claim 2, characterized in that The application scenarios include: The input flip time and load capacitance extracted from the characteristic data table, or the input flip time and output load status obtained based on the HDL synthesis results of the integrated circuit and the gate-level netlist after layout and routing.

4. The method according to claim 1, characterized in that: The forming of the target logic implementation path comprises: Based on the logic environment, a basic standard cell is obtained from a standard cell library, and the target logic implementation path is formed according to the target logic implementation of the standard cell to be evaluated; The forming of the optimal logic implementation path comprises: Based on the logic environment, basic standard cells are obtained from a standard cell library, and the optimal logic implementation path is constructed according to the optimal logic implementation of the standard cell to be evaluated; wherein the optimal logic implementation path is used to characterize the best characteristic performance of the standard cell to be evaluated under predetermined characteristic constraint conditions, so as to serve as a reference standard for characteristic performance evaluation of the standard cell to be evaluated.

5. The method according to claim 4, characterized in that The preset feature constraint conditions include: At least one of delay time, switching time, dynamic power consumption, static power consumption, unit driving capability, area occupation and clock signal frequency.

6. The method according to claim 1, characterized in that The signal excitation includes: Ideal rising or falling signals, signals generated by actual standard cells in high-frequency applications, or equivalent driving signals composed of basic standard cells in a standard cell library.

7. The method according to claim 1, characterized in that The comparing the output result of the target logic implementation path with the output result of the optimal logic implementation path to evaluate the characteristic performance of the target logic implementation path includes: Comparing the output result of the target logic implementation path with the output result of the optimal logic implementation path; If the output result of the target logic implementation path is the same as the output result of the optimal logic implementation path, or is better than the output result of the optimal logic implementation path, it is determined that the characteristic performance of the target logic implementation path meets the expected value.

8. The method according to claim 7, characterized in that After comparing the output result of the target logic implementation path with the output result of the optimal logic implementation path, the method further includes: If it is determined that the characteristic performance of the target logic implementation path does not meet the expected value, the characteristic parameters of the tested evaluation standard unit are iteratively optimized until the output evaluation result characterizes that the characteristic of the tested evaluation unit meets the expected value.

9. The method according to claim 1, characterized in that: The comparing the output result of the target logic implementation path with the output result of the optimal logic implementation path to evaluate the characteristic performance of the target logic implementation path also includes: Extracting each feature data from the output results of the target logic implementation path and the optimal logic implementation path respectively; According to the application scenario and characteristic constraint conditions of the standard unit to be evaluated, a corresponding weight value is configured for each characteristic data; The weighted comprehensive value of the characteristic data in the output result of the target logic implementation path is compared with the weighted comprehensive value of the characteristic data in the output result of the optimal logic implementation path to evaluate the characteristic performance of the target logic implementation path.

10. The method according to claim 1, characterized in that Before building the logical environment, include: Constructing a standard cell library according to a specified process node environment, wherein the standard cell library at least includes a set of basic standard cells composed of basic logic cells and feature data corresponding to the basic standard cells; and, constructing the standard unit to be evaluated according to a user instruction, and generating characteristic data of the standard unit to be evaluated; For each standard unit to be evaluated, an application scenario of the standard unit to be evaluated is defined.

11. A standard cell characteristic evaluation device, characterized in that: include: A construction unit, configured to construct a logic environment according to an HDL netlist of a standard unit to be evaluated and at least one application scenario; A forming unit, used to form a target logic implementation path simulating the standard unit to be evaluated based on the logic environment, and to form an optimal logic implementation path; An input unit, used to input consistent signal stimulation to the target logic implementation path and the optimal logic implementation path respectively under preset feature constraint conditions; An evaluation unit is used to compare the output result of the target logic implementation path with the output result of the optimal logic implementation path to evaluate the characteristic performance of the target logic implementation path; wherein the characteristic performance of the target logic implementation path reflects whether the standard unit to be evaluated meets the expected value.

12. The device according to claim 11, characterized in that The building block comprises: An acquisition module, used for acquiring the HDL netlist of the standard unit to be evaluated to form an evaluated module, wherein the evaluated module is used for simulating the logic function of the standard unit to be evaluated; A construction module, used to construct a driving module and a load module according to the application scenario, wherein the driving module is used to generate input signal excitation, and the load module is used to simulate the load condition of the output end; The connection module is used to connect the driving module with the input end of the module to be evaluated, and to connect the load module with the output end of the module to be evaluated, so as to form an evaluation logic environment.

13. The device according to claim 11, characterized in that The forming unit comprises: A first forming module is used to obtain a basic standard cell from a standard cell library based on the logic environment, and to construct and form the target logic implementation path according to the target logic implementation of the standard cell to be evaluated; The second forming module is used to obtain basic standard cells from the standard cell library based on the logic environment, and construct the optimal logic implementation path according to the optimal logic implementation of the standard cell to be evaluated; wherein the optimal logic implementation path is used to characterize the best characteristic performance of the standard cell to be evaluated under predetermined characteristic constraint conditions, so as to serve as a reference standard for characteristic performance evaluation of the standard cell to be evaluated.

14. The device according to claim 11, characterized in that The evaluation unit comprises: A comparison module, used to compare the output result of the target logic implementation path with the output result of the optimal logic implementation path; A determination module, specifically configured to determine that the characteristic performance of the target logic implementation path meets the expected value if the output result of the target logic implementation path is the same as the output result of the optimal logic implementation path, or is better than the output result of the optimal logic implementation path; The optimization module is specifically used to iteratively optimize the characteristic parameters of the tested evaluation standard unit if it is determined that the characteristic performance of the target logic implementation path does not meet the expected value, until the output evaluation result characterizes that the characteristic of the tested evaluation unit meets the expected value.

15. The device according to claim 11, characterized in that The evaluation unit further comprises: An extraction module, used to extract each feature data from the output results of the target logic implementation path and the optimal logic implementation path; A configuration module, configured to configure a corresponding weight value for each feature data according to the application scenario and feature constraint conditions of the standard unit to be evaluated; The comparison module is used to compare the weighted comprehensive value of the characteristic data in the output result of the target logic implementation path with the weighted comprehensive value of the characteristic data in the output result of the optimal logic implementation path, so as to evaluate the characteristic performance of the target logic implementation path.

16. An electronic device, characterized in that: The electronic device comprises: a housing, a processor, a memory, a circuit board and a power supply circuit, wherein the circuit board is placed inside the space enclosed by the housing, and the processor and the memory are arranged on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program codes; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to execute the method described in any one of claims 1 to 10.

17. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the method of any one of claims 1 to 10.

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