Display device

Abstract

A display device may include: a display panel including a plurality of pixels; and a controller configured to control an operation of the display panel. The controller may be configured to generate an internal synchronization signal including one or more of an internal horizontal synchronization signal and an internal vertical synchronization signal based on an input external synchronization signal, the external synchronization signal having a frequency increased by a multiple, and the controller may be configured to generate a scan pulse to scan the display panel based on one or more of the generated internal horizontal synchronization signal and the generated internal vertical synchronization signal.

Description

Technical Field

[0001] The present invention relates to a display device. Background Art

[0002] Representative examples of the display device include a liquid crystal display device (LCD), a field luminescent display device (FED), an electroluminescent display device (ELD), an electrowetting display device (EWD), and an organic light emitting display device (OLED).

[0003] Among these display devices, an organic light emitting display device displays an image through pixels including an organic light emitting element as a self-luminous element. Therefore, compared with other display devices, the organic light emitting display device has advantages of a smaller thickness, a wider viewing angle, and a faster response speed.

[0004] Regarding data transmission in these display devices, an external system applies data and an external synchronization signal to a data driver to generate an internal synchronization signal. When the internal synchronization signal is generated based on the received external synchronization signal, the timing of all signals generated based on the generated internal synchronization signal deviates due to jitter.

[0005] Furthermore, among the generated signals, pulse signals affect images, eventually causing image defects due to noise. Summary of the invention

[0006] Since jitters in all signals are accumulated by jitters generated in the synchronization signal, image defects occur. Therefore, the inventors of the present invention have invented a display device that prevents jitters from occurring in signals generated based on a horizontal synchronization signal.

[0007] The present invention relates to a display device that generates a horizontal synchronization signal and generates a scan pulse signal for driving a display panel based on the horizontal synchronization signal. An embodiment of the present invention provides a display device that adjusts timing based on an oscillator clock period based on an internal synchronization signal.

[0008] Problems solved by the present invention include image defects caused by jitter accumulation generated by setting timing based on a horizontal synchronization signal.

[0009] Furthermore, an embodiment of the present invention provides a display apparatus which increases the frequency of an external synchronization signal input from an external system by a predetermined multiple and generates a horizontal synchronization signal based on the external synchronization signal having the frequency increased by the predetermined multiple.

[0010] An embodiment of the present invention provides a display device which generates a scanning signal for scanning a display panel based on a horizontal synchronization signal having a frequency increased by a predetermined multiple, thereby reducing jitter.

[0011] An embodiment of the present invention provides a display device, which includes a controller having a timing controller, wherein the timing controller generates a scan pulse configured to drive a display panel based on an internal synchronization signal, wherein the internal synchronization signal is generated based on an external synchronization signal; and an embodiment of the present invention provides a data driver, which is configured to convert image data into a data voltage and provide the data voltage to the display panel.

[0012] A display device according to an embodiment of the present invention is provided, which generates a horizontal synchronization signal and generates a scan pulse configured to operate a display panel based on the horizontal synchronization signal.

[0013] Furthermore, a display device according to an embodiment of the present invention is provided, which includes a controller generating an internal synchronization signal including an internal horizontal synchronization signal and an internal vertical synchronization signal based on an input external synchronization signal having a frequency increased by a predetermined multiple.

[0014] Furthermore, there is provided a display device according to an embodiment of the present invention, which includes a controller generating a scan pulse configured to scan a display panel based on an internal horizontal synchronization signal.

[0015] In addition, a display device according to an embodiment of the present invention is provided, which includes a controller, the controller including: a timing controller, the timing controller generates an internal horizontal synchronization signal based on an input external synchronization signal, the external synchronization signal has a frequency increased by one multiple, and the timing controller generates a scan pulse signal configured to drive a display panel based on the internal synchronization signal; and a data driver, which is configured to convert image data into a data voltage and provide the data voltage to the display panel. The timing controller and the data driver are integrated with each other.

[0016] A display device according to an embodiment of the present invention may include: a display panel including a plurality of pixels; and a controller configured to control the operation of the display panel. The controller may be configured to generate an internal synchronization signal including one or more of an internal horizontal synchronization signal and an internal vertical synchronization signal based on an input external synchronization signal, wherein the external synchronization signal has a frequency increased by a multiple, and the controller may be configured to generate a scan pulse signal for scanning the display panel based on one or more of the generated internal horizontal synchronization signal and the generated internal vertical synchronization signal.

[0017] A display device according to an embodiment of the present invention may include: a display panel including a plurality of pixels; and a controller configured to control the operation of the display panel. The controller may be configured to generate an internal synchronization signal based on an input synchronization signal, the input synchronization signal including a plurality of first clocks, the internal synchronization signal including a plurality of second clocks, each second clock corresponding to a first clock, so that a starting time point of a first edge of a second clock corresponds to a starting time point of a first edge of a corresponding first clock, and at least one first clock does not correspond to any second clock and is ahead of any first clock corresponding to a second clock.

[0018] According to an embodiment of the present invention, a timing controller generating a scan pulse and a data driver supplying a data voltage to a display panel are integrated with each other, thereby providing a display device optimized for use in a mobile device.

[0019] Furthermore, according to an embodiment of the present invention, a horizontal synchronization signal is generated using a synchronization signal having a frequency increased by a predetermined multiple, and a scan pulse for scanning a display panel is generated based on the generated horizontal synchronization signal, thereby minimizing jitter accumulation.

[0020] Furthermore, according to an embodiment of the present invention, the frequency of a synchronization signal may be increased by two times, and a horizontal synchronization signal may be generated based on the synchronization signal having the increased frequency, thereby reducing jitter accumulated in a scan pulse.

[0021] Furthermore, according to an embodiment of the present invention, the frequency of a synchronization signal may be increased four times, and a horizontal synchronization signal may be generated based on the synchronization signal having the increased frequency, thereby reducing jitter accumulated in a scan pulse. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate several aspects of the invention and together with the description serve to explain the principle of the invention.

[0023] Figure 1 A configuration of a display device according to an embodiment of the present invention is illustrated.

[0024] Figure 2 Illustrate the configuration of a pixel applied to a display device according to an embodiment of the present invention.

[0025] Figure 3 is an example in which the timing controller according to the embodiment of the present invention generates an internal synchronization signal based on an external synchronization signal and generates a scan pulse for scanning a display panel based on the internal synchronization signal.

[0026] Figure 4is an example showing a state in which jitter occurs in an internal synchronization signal generated by a timing controller according to an embodiment of the present invention.

[0027] Figure 5 is an example in which the timing controller generates an internal synchronization signal based on an external synchronization signal and generates a scan pulse for scanning a display panel based on the internal synchronization signal according to another embodiment of the present invention.

[0028] Figure 6 is an example in which the timing controller generates an internal synchronization signal based on an external synchronization signal and generates a scan pulse for scanning a display panel based on the internal synchronization signal according to another embodiment of the present invention. DETAILED DESCRIPTION

[0029] Reference will now be made in detail to various aspects of the present invention, some examples of which may be illustrated in the accompanying drawings. In the following description, detailed descriptions of known methods, functions, structures, or configurations may be omitted for the sake of brevity when such detailed descriptions would unnecessarily obscure aspects of the present invention. In addition, repeated descriptions may be omitted for the sake of brevity. The described processing steps and / or operational progressions are non-limiting examples.

[0030] The order of steps and / or operations is not limited to those set forth in the text, but may occur in an order different from that described herein, unless the steps and / or operations must occur in a particular order. In one or more examples, two operations in succession may be performed substantially simultaneously, or the two operations may be performed in a reverse order or in a different order depending on the functions or operations involved.

[0031] Unless otherwise specified, similar reference numerals may refer to similar elements throughout the specification, even if they are shown in different drawings. Unless otherwise specified, the same reference numerals may be used throughout the specification and drawings to refer to the same or substantially the same elements. In one or more aspects, the same elements (or elements with the same names) in different drawings may have the same or substantially the same functions and characteristics, unless otherwise specified. The names of the various elements used in the following description are selected for convenience only and may differ from the names used in the actual product.

[0032] The technical characteristics and features of the present invention and the methods for implementing the same are explained by referring to the embodiments described in the accompanying drawings. However, the present invention can be implemented in various forms and should not be construed as being limited to the exemplary aspects set forth herein. Rather, these exemplary aspects are examples, which are provided to make the present disclosure comprehensive and complete, to help those skilled in the art understand the inventive concept, and not to limit the scope of protection of the present invention.

[0033] The shapes, sizes (e.g., dimensions, lengths, widths, heights, thicknesses, positions, radii, diameters, and areas), proportions, ratios, angles, quantities, number of elements, etc. disclosed herein (including those shown in the drawings) are merely examples, and thus the invention is not limited to the details shown. However, it is noted that the relative sizes of the components shown in the drawings are part of the invention.

[0034] When terms such as "include", "have", "include", "contain", "comprise", etc. are used for one or more elements (e.g., layers, films, regions, parts, sections, components, parts, regions, parts, steps and / or operations, etc.), one or more other elements may be added unless terms such as "only" and the like are used. The terms used in the present invention are used only to describe specific exemplary aspects and are not intended to limit the scope of the present invention. Terms in the singular form may include plural forms unless the context clearly indicates otherwise.

[0035] The word "exemplary" is used to mean used as an example or illustration, unless otherwise specified. An embodiment is an exemplary embodiment. Multiple aspects are exemplary aspects. In one or more embodiments, "embodiment", "aspect", "example", etc. should not be interpreted as being more preferred or advantageous than other implementations. Aspects, examples, exemplary aspects, etc. may refer to one or more aspects, one or more examples, one or more exemplary aspects, etc., unless otherwise specified. In addition, the term "may" encompasses all meanings of the term "can".

[0036] In one or more aspects, unless otherwise expressly stated, an element, feature, or corresponding information (e.g., level, range, size, dimension, etc.) is interpreted as including an error or tolerance range, even if no explicit description of such error or tolerance range is provided. The error or tolerance range may be caused by various factors (e.g., process factors, internal or external impact, noise, etc.). When interpreting numerical values, the values ​​are interpreted as including the error range, unless otherwise expressly stated.

[0037] When describing a positional relationship, for example, when using "on", "above", "on top", "above", "below", "above", "below", "under", "near", "close", "adjacent", "next to", "aside", "on the side", etc. to describe the positional relationship between two parts (e.g., layers, films, regions, components, sections, etc.), one or more other parts may be placed between the two parts, unless more restrictive terms such as "immediately", "directly" or "closely" are used. For example, when a structure is described as being located "on", "above", "top", "above", "below", "above", "below", "below", "below", "near", "near", "adjacent", "next to", "aside", "on the side", etc. of another structure, the description should be interpreted as including the situation where these structures are in contact with each other and the situation where one or more additional structures are arranged or inserted between them. In addition, the terms "front", "back", "rear", "left", "right", "top", "bottom", "downward", "upward", "above", "below", "up", "down", "column", "row", "vertical", "horizontal", etc. refer to an arbitrary reference system.

[0038] Spatially relative terms such as "below," "under," "below," "on," "above," "above," and the like may be used to describe the relationship between the elements (e.g., layers, films, regions, components, sections, etc.) shown in the drawings. These spatially relative terms should be understood as terms that include different orientations of the elements when in use or operation in addition to the orientations depicted in the drawings. For example, if the elements shown in the drawings are reversed, the elements described as "below" or "beneath" other elements will be positioned "above" the other elements. Thus, the term "below" as an exemplary term may include all directions of "above" and "below." Similarly, the exemplary terms "above" or "on" may include both directions of "above" and "below."

[0039] When describing a temporal relationship, for example, when a time sequence is described as "after", "subsequently", "next", "before", "in front of", "before", etc., discontinuous or non-sequential situations may be included, so that one or more other events may occur in between, unless more restrictive terms such as "directly", "immediately" or "directly" are used.

[0040] Terms such as "below," "below," "above," "upper," etc. may be used herein to describe the relationship between elements illustrated in the drawings. It will be understood that these terms are spatially relative and are based on the orientation depicted in the drawings.

[0041] When a certain embodiment can be implemented differently, the function or operation specified in a specific block may occur in an order different from the order specified in the flow chart. For example, two consecutive blocks may actually be executed substantially simultaneously, or the two blocks may be executed in reverse order according to the functions or operations involved.

[0042] It will be understood that, although the terms "first", "second", etc. can be used to describe each element (such as layer, film, region, part, section, member, part, zone, position, step and / or operation, etc.), these elements, for example, should not be limited to any specific order, chronological order or number of elements by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present invention, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. In addition, without departing from the scope of the present invention, the first element, the second element, etc. can be arbitrarily named according to the convenience of those skilled in the art. For the sake of clarity, the function or structure of these elements (such as the first element, the second element, etc.) is not limited by the sequence number or name in front of these elements. In addition, the first element may include one or more first elements. Similarly, the second element, etc. may include one or more second elements, etc.

[0043] When describing the elements of the present invention, the terms "first", "second", "A", "B", "(a)", "(b)", etc. may be used. These terms are intended to distinguish the corresponding elements from other elements, and these terms are not used to limit the nature, basis, order or number of the elements.

[0044] When an element (for example, a layer, film, region, component, section, etc.) is described as being “connected,” “joined,” “attached,” “adhered,” etc. to another element, the element may not only be directly connected, joined, attached, adhered, etc. to the other element, but may also be indirectly connected, joined, attached, adhered, etc. to the other element with one or more intermediate elements disposed or interposed between the elements, unless otherwise specified.

[0045] When an element (for example, a layer, film, region, component, section, etc.) is expressed as “overlapping” or the like with another element, the element may not only be in direct contact with, overlap, etc. the other element, but may also be indirectly overlapped, etc. with the other element with one or more intermediate elements disposed or interposed between the elements, unless otherwise specified.

[0046] The expression that an element (e.g., a layer, a film, a region, a component, a section, etc.) is "provided", "arranged", "connected", "joined", etc. in / on another element can be understood as, for example, at least a portion of the element is provided, arranged, connected, joined, etc. in the other element, or the entire element is provided, arranged, connected, joined, etc. in the other element. The expression that an element (e.g., a layer, a film, a region, a component, a section, etc.) "contacts", "overlaps", etc. with another element can be understood as, for example, at least a portion of the element contacts, overlaps, etc. with at least a portion of the other element, the entire element contacts, overlaps, etc. with at least a portion of the other element, or at least a portion of the element contacts, overlaps, etc. with the entire other element.

[0047] Terms such as "line" or "direction" should not be interpreted based solely on the geometric relationship of each line or direction being parallel or perpendicular to each other. Such terms may refer to a wider range of lines or directions within the range in which the components of the present invention are functionally capable of operating. For example, terms such as "first direction", "second direction", etc., such as directions parallel or perpendicular to the "x-axis", "y-axis", or "z-axis", should not be interpreted based solely on the geometric relationship of each direction being parallel or perpendicular to each other, and may refer to directions with wider directivity within the range in which the components of the present invention are functionally capable of operating.

[0048] The term "at least one" should be understood to include any and all combinations of one or more of the relevant listed items. For example, the expression "at least one of the first item, the second item, or the third item" and the expression "at least one of the first item, the second item, and the third item" can each represent (i) a combination of one or more of the provided items of the first item, the second item, and the third item, and (ii) only one of the first item, the second item, and the third item.

[0049] The expression of the first element, the second element "and / or" the third element should be understood to cover one of the first element, the second element, or the third element; one of the first element, the second element, and the third element; and any and all combinations of the first element, the second element, and the third element. For example, A, B, and / or C covers: only A; only B; only C; any one of A, B, and C (e.g., A, B, or C); some combinations of A, B, and C (e.g., A and B; A and C; or B and C); and all of A, B, and C. In addition, the expression "A / B" may be understood as A and / or B. For example, the expression "A / B" may mean only A; only B; A or B; or A and B.

[0050] In one or more aspects, the terms "between" and "among" may be used interchangeably for convenience, unless otherwise specified. For example, the expression "between multiple elements" may be understood as being among multiple elements. In another example, the expression "among multiple elements" may be understood as being between multiple elements. In one or more examples, the number of elements may be two. In one or more examples, the number of elements may be more than two. In addition, when an element (e.g., a layer, a film, a region, a component, a section, etc.) is referred to as being "between" at least two elements, the element may be the only element between the at least two elements, or one or more intermediate elements may also be present.

[0051] In one or more aspects, the expressions "each other" and "mutually" may be used interchangeably for convenience, unless otherwise specified. For example, the expression "mutually different" may be understood as mutually different. In another example, the expression "mutually different" may be understood as mutually different. In one or more examples, the number of elements involved in the previous expression may be two. In one or more examples, the number of elements involved in the previous expression may be more than two.

[0052] In one or more aspects, the expressions "one or more of" and "one or more of" may be used interchangeably simply for convenience, unless otherwise noted.

[0053] The term "or" means an inclusive or rather than an exclusive or. For example, unless otherwise specified or clear from the context, the statement "x employs a or b" means any of the natural inclusive permutations. For example, "a or b" may mean "a", "b", or "a and b". For example, "a, b or c" may mean "a", "b", "c", "a and b", "b and c", "a and c", or "a, b, and c".

[0054] The features of various embodiments of the present invention may be combined or combined in part or in whole with each other, may be technically related to each other, and may be operated, linked or driven together in various ways. Aspects of the present invention may be implemented or implemented independently of each other, or may be implemented or implemented together in a mutually dependent or related relationship. In one or more aspects, the components of each device according to various aspects of the present invention may be operatively engaged and configured.

[0055] Unless otherwise defined, the terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary aspects belong. It should be further understood that terms, such as those defined in common dictionaries, should be interpreted as having a meaning consistent with the context of the relevant art, for example, and should not be interpreted in an idealized or overly formal sense, unless otherwise explicitly defined herein.

[0056] The terms used herein are selected as common terms in the relevant technical field. However, other terms other than these terms may exist according to the development and / or changes of technology, protocols, preferences of technicians, etc. Therefore, the terms used herein should not be understood as limiting the technical concept, but should be understood as examples of terms used to illustrate the implementation mode.

[0057] In addition, in specific cases, the applicant may arbitrarily select terms, in which case their detailed meanings will be described herein. Therefore, the terms used herein should be understood not only based on the names of the terms simply, but also based on the meanings of the terms and their contents.

[0058] The “X-axis direction”, “Y-axis direction” and “Z-axis direction” should not be interpreted by a geometric relationship of only being perpendicular to each other, but may have wider directivities within a range in which the elements of the present invention can function.

[0059] In the following description, various exemplary aspects of the present invention are described in detail with reference to the accompanying drawings. With respect to the reference numerals for the elements of each figure, the same elements may be shown in other figures, and similar reference numerals may refer to similar elements, unless otherwise specified. The same or similar elements may be referred to by the same reference numerals, even if they are depicted in different figures. In addition, for ease of presentation, the proportions, sizes, dimensions, and thicknesses of each element shown in the accompanying drawings may be different from the actual proportions, sizes, dimensions, and thicknesses, and therefore aspects of the present invention are not limited to the proportions, sizes, dimensions, and thicknesses shown in the drawings.

[0060] When describing a signal flow, for example, when a signal is transmitted from node A to node B, it may include a case where the signal is transmitted from node A to node B via other nodes, unless the expression "immediately transmitted" or "directly transmitted" is used.

[0061] Hereinafter, a display device according to each embodiment of the present invention will be described with reference to the accompanying drawings.

[0062] Figure 1 A configuration of a display device according to an embodiment of the present invention is illustrated. Figure 2 Illustrate the configuration of a pixel applied to a display device according to an embodiment of the present invention.

[0063] The display device according to the embodiment of the present invention may be a liquid crystal display device, an organic light emitting display device using an organic light emitting diode, or a light emitting display device using other types of light emitting elements. In other words, the embodiment of the present invention may also be applied to a liquid crystal display device using a liquid crystal instead of a light emitting element, and a light emitting display device using an inorganic light emitting element. In addition, the display device according to the embodiment of the present invention may be mounted on a portable device.

[0064] However, hereinafter, for convenience of description, an example in which the display apparatus is implemented as a light-emitting display device using a light-emitting element is described.

[0065] like Figure 1 and Figure 2 As shown, the area of ​​the display device 100 according to the embodiment of the present invention may be divided into or include a display area 120 and a non-display area 130 surrounding the display area 120. In addition, the display area 120 may include pixels 121 having light emitting elements ED and a pixel driver circuit PDC, and the non-display area 130 may have a gate driver built in the non-display area 130 to provide a gate signal to the pixel driver circuit PDC.

[0066] According to an embodiment of the present invention, a display device 100 may include: a display panel 110 including pixels 121 ; and a controller 140 .

[0067] For example, the controller 140 may include: a timing controller 160, which provides image data Data and an external synchronization signal to the data driver 150; and a data driver 150, which converts the image data Data transmitted from the timing controller 160 into a data voltage Vdata and outputs the converted data voltage Vdata to the data lines DL1 to DLd set in the display panel 110.

[0068] For example, the timing controller 160 and the data driver 150 may be configured as separate components in the display device 100 , or may be built into a single chip (eg, the controller 140 ).

[0069] For example, the timing controller 160 may generate an internal synchronization signal including an internal horizontal synchronization signal and an internal vertical synchronization signal based on an external synchronization signal input with a frequency increased by a predetermined multiple.

[0070] In addition, the timing controller 160 may generate a scan pulse for scanning the display panel 110 based on the generated internal horizontal synchronization signal and / or the generated internal vertical synchronization signal.

[0071] In addition, the display panel 110 is provided with a plurality of scan pulse lines SPL1 to SPLg, wherein the scan pulses generated by the timing controller 160 are transmitted through the scan pulse lines SPL1 to SPLg.

[0072] In addition, the display device 100 may include a power supply that supplies power to the display panel 110 and the controller 140 (eg, the timing controller 160 and the data driver 150 ).

[0073] Hereinafter, the above components are described in sequence.

[0074] According to an embodiment of the present invention, the display panel 110 according to an embodiment of the present invention may include a display area 120 provided with pixels 121 including light emitting elements ED and pixel driver circuits PDC; and a non-display area 130 surrounding the display area 120 .

[0075] For example, a gate driver that provides a gate signal to the gate driver circuit PDC may be built in the non-display area 130 .

[0076] like Figure 2 As shown, the display panel 110 may be provided with pixels 121 including light emitting elements ED and pixel driver circuits PDC. In addition, signal lines are formed in the display panel 110 so as to define a pixel region where the pixels 121 are provided and to provide a driving signal to the pixel driver circuits PDC.

[0077] According to an embodiment of the present invention, the light emitting element ED may include a first electrode, a light emitting layer disposed on the first electrode, and a second electrode disposed on the light emitting layer. For example, the light emitting layer may include one of a blue light emitting portion, a green light emitting portion, and a red light emitting portion to respectively emit light beams of colors corresponding to the colors in the pixel 121. In addition, the light emitting layer may include one of an organic light emitting layer, an inorganic light emitting layer, and a quantum dot light emitting layer, or may include a stacked or mixed structure of an organic light emitting layer (or an inorganic light emitting layer) and a quantum dot light emitting layer.

[0078] According to an embodiment of the present invention, the signal line may include a gate line GL, a scan pulse line SPL, a data line DL, a sensing line SL, a first driving power line PLA, and a second driving power line PLB.

[0079] For example, the gate lines may be arranged in parallel, may be spaced apart from each other at equal distances along a second direction of the display panel 110 , eg, a column direction, and may extend along a first direction of the display panel, eg, a row direction.

[0080] For example, the scan pulse lines SPL may be arranged in parallel, may be spaced apart from each other at equal distances along a second direction of the display panel 110, such as a column direction, and may extend along a first direction of the display panel, such as a row direction. The scan pulse lines SPL may be parallel to the gate lines. The scan pulses SP generated by the controller 140 are provided to the scan pulse lines SPL.

[0081] For example, the data lines DL may be arranged in parallel, may be spaced apart from each other at equal distances along a first direction of the display panel 110 , such as a row direction, may extend along a second direction of the display panel, such as a column direction, and may cross the gate lines and the scan pulse lines SPL.

[0082] Furthermore, the arrangement structure of the data lines DL and the gate lines may be changed in various ways.

[0083] For example, the sensing lines SL may be arranged in parallel, may be spaced apart from each other at equal distances along a first direction of the display panel 110, such as a row direction, may extend along a second direction of the display panel, such as a column direction, and may be parallel to the data lines DL. However, the embodiments of the present invention are not limited thereto. For example, at least three pixels 121 may constitute a unit pixel, in which case one sensing line SL may be formed in the unit pixel.

[0084] According to an embodiment of the present invention, the first driving power lines PLA may be arranged in parallel, may be spaced apart from each other at equal distances along a first direction of the display panel 110, such as a row direction, may extend along a second direction of the display panel, such as a column direction, and may be parallel to the data lines DL and the sensing lines SL. The first driving power lines PLA may be connected to a power source and may supply a first driving power EVDD supplied from the power source to each pixel 121.

[0085] According to an embodiment of the present invention, the second driving power line PLB may supply the second driving power EVSS provided from a power source to each pixel 121 .

[0086] According to an embodiment of the present invention, the pixel driver circuit PDC may include: a driving transistor Tdr that controls a current I flowing through the light emitting element ED; a switching transistor Tsw1 connected between the data line DL and the driving transistor Tdr and the gate line GL; a sensing transistor Tsw2 connected to the light emitting element ED and the sensing line SL; and a capacitor Cst. In addition, the pixel driver circuit PDC provided in each pixel 121 may further include a transistor for external compensation or internal compensation.

[0087] For example, the pixel driver circuit PDC may be modified into various structures that perform internal compensation or external compensation.The mechanism of driving the pixel driver circuit PDC may be changed in various ways.

[0088] The external compensation may include: calculating the amount of change in the threshold voltage or mobility of the driving transistor Tdr formed in the pixel 121; and changing the amplitude of the data voltage Vdata supplied to the pixel based on the amount of change. Therefore, the structure of the pixel 121 may be modified into various forms in which the amount of change in the threshold voltage or mobility of the driving transistor Tdr can be calculated.

[0089] Internal compensation can be performed so that the current transmitted to the light emitting element of the driving transistor Tdr formed in the pixel 121 is not affected by the threshold voltage of the driving transistor Tdr. To this end, the structure and driving mechanism of the pixel can be modified into various forms that can remove the threshold voltage from the current calculation formula.

[0090] The display area 120 of the display panel 110 refers to an area where an image is output by the pixels 121 , and the non-display area 130 refers to an area where no image is displayed. The non-display area 130 may be disposed outside the display area 120 .

[0091] According to an embodiment of the present invention, the gate driver may provide a gate signal to the pixel driver circuit PDC.

[0092] The gate driver may be disposed in the non-display area 130 , and may be manufactured in the same process as that of the pixel driver circuit PDC.

[0093] For example, the gate driver may be directly built into the display panel 110 through a gate-in-panel (GIP) approach.

[0094] The gate driver may include a plurality of stages connected to gate lines provided in the display panel 110 .

[0095] In each stage, the first terminal may be connected to an nth gate clock line to which an nth gate clock is provided. The second terminal may be connected to a gate-on transistor connected to the gate line, and the first terminal may be connected to a gate of the gate-on transistor. The second terminal may include a ripple compensation capacitor connected to an inverted gate clock line to which another gate clock is provided.

[0096] The gate driver may provide the gate turn-on signal GP to the gate lines provided in the display panel 110 through the gate control signal (GCS) transmitted from the timing controller 160. The gate control signal (GCS) may include a plurality of gate clocks.

[0097] In this regard, the gate-on signal GP may refer to a signal that can turn on the switch transistor Tsw1 connected to the gate line. A signal that can turn off the switch transistor Tsw1 is referred to as a gate-off signal. The gate-on signal GP and the gate-off signal are collectively referred to as a gate signal.

[0098] The gate driver may generate a gate signal for data addressing in response to a gate control signal (GCS) provided from the timing controller 160, and sequentially provide the generated gate signal to the m gate lines. For example, the gate driver may include a shift register that sequentially outputs the gate signal based on the gate control signal (GCS).

[0099] According to an embodiment of the present invention, the non-display area 130 may include a gate clock line configured to provide a gate clock to the gate driver.

[0100] According to an embodiment of the present invention, the power supply may provide power to the display panel 110 , the gate driver, the data driver 150 , and the timing controller 160 .

[0101] According to an embodiment of the present invention, the data driver 150 converts the image data Data transmitted from the timing controller 160 into a data voltage Vdata and then supplies the data voltage Vdata to the data lines DL1 to DLd.

[0102] The data driver 150 receives the data control signal (DCS) and the modulated input image data provided from the timing controller 160. In addition, the data driver 150 samples the modulated input image data on a first horizontal line basis based on the data control signal (DCS), converts the sampled data into a data voltage Vdata in an analog form based on a plurality of reference gamma voltages, and provides the data voltage Vdata to the data line DL of each pixel P.

[0103] According to an embodiment of the present invention, the timing controller 160 may generate an internal synchronization signal including an internal horizontal synchronization signal and an internal vertical synchronization signal through a synchronization signal (e.g., an external synchronization signal) input from an external system. In addition, the timing controller 160 may generate a scan pulse (e.g., GIP signals GIP1 to GIPg) for scanning the display panel 110 based on the internal horizontal synchronization signal or the generated internal vertical synchronization signal.

[0104] According to an embodiment of the present invention, the timing controller 160 may generate a gate control signal (GCS) configured to control driving of a gate driver and a data control signal (DCS) configured to control driving of a data driver based on a synchronization signal sync input from an external system.

[0105] In addition, the timing controller 160 may convert input image data (Ri, Gi, Bi) input from an external system into image data Data and transmit the image data Data to the data driver 150 .

[0106] To this end, the timing controller 160 may rearrange the input image data (Ri, Gi, Bi) transmitted from the external system through a synchronization signal transmitted from the external system, and may transmit the rearranged image data to the data driver 150 .

[0107] The gate control signal (GCS) may include a gate clock for generating a gate signal.

[0108] The timing controller 160 may generate a compensation value for external compensation by sensing data received from the pixel driver circuit PDC through the data driver 150 .

[0109] In addition, the timing controller 160 may generate various control signals and transmit the various control signals to the gate driver and the data driver 150 , so that an operation for internal compensation may be performed.

[0110] According to an embodiment of the present invention, the timing controller 160 may increase the frequency of a synchronization signal (eg, an external synchronization signal) transmitted from an external system by a predetermined multiple.

[0111] According to an embodiment of the present invention, the timing controller 160 (or an external system) may generate an internal synchronization signal including an internal horizontal synchronization signal (hsync) and an internal vertical synchronization signal (vsync) based on a synchronization signal (Xsync) (e.g., an external synchronization signal) having a frequency increased by a predetermined multiple (e.g., 2 times, 3 times, 4 times, etc.) as received from the timing controller 160 (or an external system). Then, the timing controller 160 may generate a scan pulse (e.g., a GIP signal) for scanning the display panel 110 based on the generated internal horizontal synchronization signal or the generated internal vertical synchronization signal.

[0112] According to an embodiment of the present invention, the timing controller 160 may generate an internal synchronization signal (e.g., an internal horizontal synchronization signal and / or an internal vertical synchronization signal) having a frequency increased by a predetermined multiple (e.g., 2 times, 3 times, 4 times, etc.) based on a synchronization signal (Xsync) (e.g., an external synchronization signal) having a frequency increased by a predetermined multiple (e.g., 2 times, 3 times, 4 times, etc.) as received from the timing controller 160 (or an external system).

[0113] According to an embodiment of the present invention, the timing controller 160 may generate an internal horizontal synchronization signal whose voltage changes from a low level to a high level at a point (or time point) when the voltage of an input synchronization signal rises from a low level to a high level.

[0114] According to an embodiment of the present invention, when a synchronization signal with a frequency increased by two times is input from an external system to the timing controller 160, the timing controller 160 may generate an internal horizontal synchronization signal so that after the voltage of the first clock of the input synchronization signal drops from a high voltage to a low voltage, the point (or time point) at which the voltage of the second clock of the input synchronization signal rises from a low voltage to a high voltage and the point (or time point) at which the voltage of the first clock of the internal horizontal synchronization signal rises from a low voltage to a high voltage are consistent with or correspond to each other.

[0115] According to an embodiment of the present invention, the timing controller 160 may generate an internal horizontal synchronization signal so that after the voltage of the second clock of the input synchronization signal drops from a high voltage to a low voltage, the point (or time point) at which the voltage of the third clock of the input synchronization signal rises from a low voltage to a high voltage is consistent with or corresponds to the point (or time point) at which the voltage of the second clock of the internal horizontal synchronization signal rises from a low voltage to a high voltage.

[0116] According to an embodiment of the present invention, the timing controller 160 may generate a scan pulse as follows: when the voltage of the first clock of the internal horizontal synchronization signal drops from a high voltage to a low voltage, the scan pulse transmitted to the first scan pulse line SPL1 drops from a high voltage to a low voltage; when the voltage of the second clock of the internal horizontal synchronization signal drops from a high voltage to a low voltage, the scan pulse that has dropped to a low voltage rises to a high voltage.

[0117] For example, the generated scan pulse may be generated based on a point (or time point) at which a voltage of a first clock of the internal horizontal synchronization signal falls and a point (or time point) at which a voltage of a second clock of the internal horizontal synchronization signal falls.

[0118] According to an embodiment of the present invention, when a synchronization signal with a frequency increased four times is input from an external system to the timing controller 160, the timing controller 160 may generate an internal horizontal synchronization signal so that after the voltage of the second clock of the input synchronization signal drops from a high voltage to a low voltage, the point (or time point) at which the voltage of the third clock of the input synchronization signal rises from a low voltage to a high voltage and the point (or time point) at which the voltage of the first clock of the internal horizontal synchronization signal rises from a low voltage to a high voltage are consistent with or correspond to each other.

[0119] According to an embodiment of the present invention, the timing controller 160 may generate an internal horizontal synchronization signal so that after the voltage of the third clock of the input synchronization signal drops from a high voltage to a low voltage, the point (or time point) at which the voltage of the fourth clock of the input synchronization signal rises from a low voltage to a high voltage is consistent with or corresponds to the point (or time point) at which the voltage of the second clock of the internal horizontal synchronization signal rises from a low voltage to a high voltage.

[0120] According to an embodiment of the present invention, the timing controller 160 may generate a scan pulse as follows: when the voltage of the first clock of the internal horizontal synchronization signal drops from a high voltage to a low voltage, the scan pulse transmitted to the first scan pulse line SPL1 drops from a high voltage to a low voltage; when the voltage of the fourth clock of the internal horizontal synchronization signal drops from a high voltage to a low voltage, the scan pulse that has dropped to a low voltage rises to a high voltage.

[0121] For example, the generated scan pulse may be generated based on a point (or time point) at which a voltage of a first clock of the internal horizontal synchronization signal falls and a point (or time point) at which a voltage of a fourth clock of the internal horizontal synchronization signal falls.

[0122] Therefore, the timing controller 160 may adjust the timing based on the oscillator clock cycle based on the generated internal horizontal synchronization signal (or internal vertical synchronization signal).

[0123] Then, the timing controller 160 may generate a scan pulse configured to drive the display panel 110 based on the generated internal horizontal synchronization signal or the generated internal vertical synchronization signal, and may then output the generated scan pulse to a scan pulse line provided in the display panel 110 .

[0124] Figure 3 is an example in which the timing controller according to the embodiment of the present invention generates an internal synchronization signal based on an external synchronization signal and generates a scan pulse for scanning a display panel based on the internal synchronization signal. Figure 4 is an example showing a state in which jitter occurs in an internal synchronization signal generated by a timing controller according to an embodiment of the present invention.

[0125] Reference Figure 3 and Figure 4 , the external system according to one embodiment of the present invention outputs a synchronization signal 310 to the controller 140. Then, the timing controller 160 in the controller 140 may generate an internal synchronization signal including an internal horizontal synchronization signal and an internal vertical synchronization signal based on the synchronization signal (input Xsync) 320 output from the external system and input.

[0126] For example, the timing controller 160 may generate the internal horizontal synchronization signal 330 based on the synchronization signal 310 input from the external system as the external synchronization signal. Alternatively or additionally, the timing controller 160 may generate the internal vertical synchronization signal through the synchronization signal 310 input from the external system.

[0127] The synchronization signal (Xsync) 310 input from the external system includes a clock (or clock cycle) of a certain time period. For example, the synchronization signal (Xsync) 310 may be output from the external system, and the synchronization signal (Xsync) 310 output from the external system is input to the timing controller 160. The clock may maintain a logic high level during its duty cycle, or maintain a logic low level during its duty cycle. In the description herein, for the purpose of illustration, the signal clock may be described as maintaining a high logic level (or high level) during its duty cycle, which does not limit the scope of the present invention. The same signal may include a clock that maintains a logic low level during its duty cycle, which does not deviate from the concept of the present invention and is included within the scope of the present invention.

[0128] The synchronization signal (Xsync) 310 output from the external system may be delayed, and then the delayed synchronization signal 320 may be input to the timing controller 160 as an input synchronization signal.

[0129] For example, a synchronization signal (Xsync) 310 output from an external system may be delayed, and the delayed synchronization signal (input Xsync) 320 may be input to the timing controller 160 as an input synchronization signal.

[0130] For example, a first clock 311 of a synchronization signal (Xsync) 310 output from an external system may be delayed 301 and then input to the timing controller 160. Similarly, a second clock 312 of a synchronization signal (Xsync) 310 output from an external system may be delayed 302 and then input to the timing controller 160.

[0131] According to an embodiment of the present invention, the timing controller 160 may generate an internal horizontal synchronization signal (hsync) 330 based on an input synchronization signal (Xsync) 320 .

[0132] For example, the timing controller 160 may generate the internal horizontal sync signal 330 whose voltage changes from a low level to a high level at a point (or time point) at which the voltage of the input sync signal drops from a high level to a low level.

[0133] For example, the timing controller 160 may generate an internal horizontal synchronization signal 330 having a first clock 331. In this regard, the voltage of the first clock 331 of the internal horizontal synchronization signal 330 changes from a logic low level "low level" to a logic high level "high level" at a point (or time point) at which the voltage of the first clock 321 of the input synchronization signal 320 changes (or drops) from a logic high level voltage "high voltage" to a logic low level voltage "low voltage", and then the voltage of the clock of the internal horizontal synchronization signal 330 remains at a high level for a certain period of time. In the description herein, an event occurring at a point in time also includes situations in which the event occurs around and after the point in time.

[0134] Similarly, the timing controller 160 may generate an internal horizontal synchronization signal 330 having a second clock 332. In this regard, the voltage of the second clock 332 of the internal horizontal synchronization signal 330 changes from a low level to a high level at a point (or time point) at which the voltage of the second clock 322 of the input synchronization signal 320 changes (or drops) from a high voltage to a low voltage, and then the voltage of the clock of the internal horizontal synchronization signal 330 is maintained at a high level for a determined period of time.

[0135] Similarly, the timing controller 160 may generate an internal horizontal synchronization signal 330 having an n-th clock. In this regard, the voltage of the n-th clock of the internal horizontal synchronization signal 330 changes from a low level to a high level at a point (or time point) at which the n-th clock of the input synchronization signal 320 changes (or drops) from a high voltage to a low voltage, and then the voltage of the n-th clock of the internal horizontal synchronization signal 330 is maintained at a high level for a determined period of time.

[0136] According to an embodiment of the present invention, the timing controller 160 may generate scan pulse signals (or scan pulses) 340 and 350 for scanning pixels of the display panel 110 based on the internal horizontal synchronization signal 330 .

[0137] For example, the timing controller 160 may generate a scan pulse signal (or scan pulse) 340 having a clock 341 of a determination period 303 after the voltage of the first clock 331 of the internal horizontal synchronization signal 330 changes from a high level to a low level. After the voltage of the first clock 331 of the internal horizontal synchronization signal 330 changes from a high level to a low level, the clock 341 changes from a logic high voltage to a logic low voltage, and after the determination period 303, the voltage of the scan pulse 340 changes from a low voltage to a high voltage. In addition, the timing controller 160 may output the generated scan pulse 340 to the first scan pulse line SPL1 of the display panel 110.

[0138] Similarly, the timing controller 160 may generate a scan pulse 350 having a clock 351 of a certain period 304 after the voltage of the second clock 332 of the internal horizontal synchronization signal 330 changes from a high level to a low level. In addition, the timing controller 160 may output the generated scan pulse 350 to the second scan pulse line SPL2 of the display panel 110.

[0139] However, jitters 401, 402, 403, and 404 may be generated in the internal horizontal synchronization signal 330 generated by the timing controller 160 based on the external synchronization signal. In this case, the timing of all signals generated based on the internal horizontal synchronization signal may be deviated. For example, jitters 405 and 406 generated in the scan pulse signal 340 may affect the image of the display panel, thereby causing noise and other image defects of the display panel.

[0140] For example, in the scan pulse signal 340 , the jitter 405 corresponding to the point (or time point) at which the voltage of the first clock 331 of the internal horizontal synchronization signal 330 rises is greater than the jitter 406 corresponding to the point (or time point) at which the voltage of the first clock 331 falls.

[0141] Figure 5According to another embodiment of the present invention, the timing controller generates an internal synchronization signal based on an external synchronization signal and generates a scan pulse signal for scanning a display panel based on the internal synchronization signal.

[0142] Reference Figure 5 , according to another embodiment of the present invention, an external system (external to the timing controller 160) outputs a synchronization signal 510. Then, the timing controller 160 may generate one or more internal synchronization signals including an internal horizontal synchronization signal and an internal vertical synchronization signal using a synchronization signal (input Xsync) 520 output from the external system and input to the timing controller 160.

[0143] For example, the timing controller 160 may generate the internal horizontal synchronization signal 530 based on the synchronization signal 510 input from the external system. Alternatively or additionally, the timing controller 160 may generate the internal vertical synchronization signal based on the synchronization signal 510 input from the external system.

[0144] The synchronization signal (Xsync) 510 input from the external system includes a clock of a certain period of time. For example, the synchronization signal (Xsync) 510 may be output from the external system. The synchronization signal (Xsync) 510 output from the external system is input to the timing controller 160 .

[0145] A synchronization signal (Xsync) 510 output from an external system may be delayed, and then the delayed synchronization signal 520 may be input to the timing controller 160 as a synchronization signal.

[0146] For example, a synchronization signal (Xsync) 510 output from an external system may be delayed and input to the timing controller 160 as an input synchronization signal (input Xsync) 520 .

[0147] According to an embodiment of the present invention, the timing controller 160 may increase the frequency of the synchronization signal (Xsync) 510 (e.g., an external synchronization signal) by a predetermined multiple (e.g., 2 times). For example, increasing the frequency of the synchronization signal (Xsync) 510 by a predetermined multiple (e.g., 2 times) may indicate that, for example, the number of clocks of the synchronization signal within a certain duration is increased by a predetermined multiple (e.g., 2 times).

[0148] According to an embodiment of the present invention, a first clock 511 of a synchronization signal (Xsync) 510 output from an external system may be delayed 501 to become a clock 521 of a delayed input synchronization signal 520, and then input to the timing controller 160. Similarly, a second clock 512 of a synchronization signal (Xsync) 510 output from an external system may be delayed 502 to become a clock 522 of a delayed input synchronization signal 520, and then input to the timing controller 160.

[0149] According to an embodiment of the present invention, the timing controller 160 may generate an internal horizontal synchronization signal (hsync) 530 based on an input synchronization signal (Xsync) 520 .

[0150] For example, the timing controller 160 may generate an internal horizontal synchronization signal 530 having a first clock 531. The voltage of the first clock 531 may be changed from a low level to a high level (e.g., a rising edge of the first clock 531) at or around a point (or time point, such as a starting point of a rising edge) at which the voltage of the second clock 522 (i.e., a clock after the first clock 521) of the input synchronization signal rises from a low level to a high level (e.g., a rising edge of the second clock 522). For example, jitter 531a may be generated when the voltage of the first clock 531 changes from a low level to a high level. In addition, jitter 531b may be generated when the voltage of the first clock 531 changes from a high level to a low level.

[0151] Similarly, the internal horizontal synchronization signal 530 has a second clock 532 whose voltage changes from a low level to a high level (rising edge) at a point (or time point) at which the voltage of the third clock 523 (i.e., a clock after the second clock 522) of the input synchronization signal 520 rises from a low level to a high level. For example, jitter 532a may be generated when the voltage of the second clock 532 changes from a low level to a high level. In addition, jitter 532b may be generated when the voltage of the second clock 532 changes from a high level to a low level.

[0152] For example, the timing controller 160 generates an internal horizontal synchronization signal 530 so that the voltage of the first clock 531 of the internal horizontal synchronization signal 530 changes from a low level to a high level at a point (or time point) when the voltage of the second clock 522 (for example, a clock after the first clock 521) of the input synchronization signal 520 rises from a low voltage to a high voltage, and then, the voltage of the first clock 531 can be maintained at a high level for a determined time period.

[0153] Similarly, the timing controller 160 generates an internal horizontal synchronization signal 530 so that the voltage of the second clock 532 of the internal horizontal synchronization signal 530 changes from a low level to a high level at a point (or time point) when the voltage of the third clock 523 (for example, a clock after the second clock 522) of the input synchronization signal 520 rises from a low voltage to a high voltage, and then, the voltage of the second clock 532 can be maintained at a high level for a determined time period.

[0154] Similarly, the timing controller 160 generates the internal horizontal synchronization signal 530 so that the voltage of the nth clock of the internal horizontal synchronization signal 530 changes from a low level to a high level at a point (or time point) at which the voltage of the (n+1)th clock (e.g., the clock after the nth clock) of the input synchronization signal 520 rises from a low voltage to a high voltage, and then the voltage of the nth clock of the internal horizontal synchronization signal 530 can be maintained at a high level for a certain period of time. That is, the nth clock of the internal horizontal synchronization signal 530 corresponds to the (n+1)th clock (e.g., the clock after the nth clock) of the input synchronization signal 520 so that the starting points of their rising edges correspond to each other. And there is at least one clock 521 in the input synchronization signal 520 that does not correspond to any clock in the internal horizontal synchronization signal 530 (which precedes other clocks of the input synchronization signal 520 that correspond to the clocks in the internal horizontal synchronization signal 530). Please note that most of the first clocks 531 in the internal horizontal synchronization signal 530 correspond to the clocks 522 in the input synchronization signal 520 (which lag behind the clocks 521 of the input synchronization signal 520 that do not correspond to any clock in the internal horizontal synchronization signal 530).

[0155] According to an embodiment of the present invention, the timing controller 160 may generate scan pulse signals 540 and 550 configured to drive pixels of the display panel 110 based on the internal horizontal synchronization signal 530 .

[0156] For example, the timing controller 160 may generate a scan pulse 540 of a clock 541 having a certain period 570 after the voltage of the first clock 531 of the internal horizontal synchronization signal 530 changes from a high level to a low level. The timing controller 160 may be configured to generate the scan pulse 540 so that when the voltage of the first clock 531 of the internal horizontal synchronization signal 530 drops from a high voltage to a low voltage, the scan pulse 540 drops from a high voltage to a low voltage; and when the voltage of the second clock 532 of the internal horizontal synchronization signal 530 drops from a high voltage to a low voltage, the scan pulse 540 dropped to a low voltage rises to a high voltage. The generated scan pulse 540 may be generated based on a point at which the voltage of the first clock 531 of the internal horizontal synchronization signal 530 drops and a point at which the voltage of the second clock 532 of the internal horizontal synchronization signal 530 drops. After the voltage of the first clock 531 of the internal horizontal synchronization signal 530 changes from a high level to a low level (e.g., a falling edge), the voltage of the second clock 532 of the internal horizontal synchronization signal 530 changes from a high level to a low level, and then the voltage of the clock 541 may be converted from a low voltage to a high voltage (e.g., a rising edge). For example, after a certain period of time 570 after the voltage of the clock 541 changes from a high voltage to a low voltage, the voltage of the clock 541 changes from a low voltage to a high voltage. For example, when the voltage of the clock 541 changes from a high level to a low level, a jitter 541a may be generated. In addition, when the voltage of the clock 541 changes from a low level to a high level, a jitter 541b may be generated. And, the timing controller 160 may output the generated scan pulse 540 to the first scan pulse line SPL1 of the display panel 110. That is, the falling edge and the rising edge of the clock 541 in the scan pulse signal 540 correspond to the falling edges of two different clocks 531 and 532 of the internal horizontal synchronization signal 530, respectively.

[0157] Similarly, the timing controller 160 may generate a scan pulse 550 of a clock 551 having a certain period 580 after the voltage of the third clock 533 of the internal horizontal synchronization signal 530 changes from a high level to a low level. After the voltage of the third clock 533 of the internal horizontal synchronization signal 530 changes from a high level to a low level, the voltage of the fourth clock 534 of the internal horizontal synchronization signal 530 may change from a high level to a low level, and then the voltage of the clock 551 may change from a low voltage to a high voltage again. For example, after a certain period 580 after the voltage of the clock 551 changes from a high voltage to a low voltage, the voltage of the clock 551 may change from a low voltage to a high voltage again. For example, when the voltage of the clock 551 changes from a high level to a low level, a jitter 551a may be generated. In addition, when the voltage of the clock 551 changes from a low level to a high level, a jitter 551b may be generated. Also, the timing controller 160 may output the generated scan pulse 550 to the second scan pulse line SPL2 of the display panel 110 .

[0158] As described above, the controller 140 (e.g., the timing controller 160) according to the embodiment of the present invention may generate an internal synchronization signal including one or more of an internal horizontal synchronization signal and an internal vertical synchronization signal based on an input external synchronization signal having a frequency increased by a predetermined multiple, and may generate a scan pulse signal for scanning the display panel 110 based on one or more of the generated internal horizontal synchronization signal and the generated internal vertical synchronization signal. For example, the external synchronization signal may be received from an external system or from the timing controller 160.

[0159] According to an embodiment of the present invention, when a synchronization signal having a frequency increased by a predetermined multiple (e.g., 2 times) is input from an external system to the controller 140 (e.g., the timing controller 160), the controller 140 (e.g., the timing controller 160) may generate an internal horizontal synchronization signal so that after the voltage of the first clock 521 of the input synchronization signal drops from a high voltage to a low voltage, the point (or time point) at which the voltage of the second clock 522 of the input synchronization signal 520 rises from a low voltage to a high voltage is consistent with the point (or time point) at which the voltage of the first clock 531 of the internal horizontal synchronization signal 530 rises from a low voltage to a high voltage. In addition, the controller 140 (for example, the timing controller 160) can generate an internal horizontal synchronization signal 530 so that after the voltage of the second clock 522 of the input synchronization signal 520 drops from a high voltage to a low voltage, the point (or time point) at which the voltage of the third clock 523 of the input synchronization signal 520 rises from a low voltage to a high voltage and the point (or time point) at which the voltage of the second clock 532 of the internal horizontal synchronization signal 530 rises from a low voltage to a high voltage are consistent with each other.

[0160] Although jitters 531a, 531b, 532a, and 532b may be generated in the internal horizontal synchronization signal 530 generated by the timing controller 160 based on the external synchronization signal, Figure 5 The delay between the point (or time point) at which the voltage of the clock 541 of the scanning pulse signal 540 changes from a low level to a high level and the point (or time point) at which the voltage of the second clock 532 of the internal horizontal synchronization signal 530 changes from a high level to a low level is less than Figure 4 The delay between the point (or time point) at which the voltage of the clock 341 in the internal horizontal synchronization signal 330 changes from a low level to a high level and the point (or time point) at which the voltage of the first clock 331 of the internal horizontal synchronization signal 330 changes from a high level to a low level. Figure 5 The jitter in can be less than Figure 4 The jitter in .

[0161] Figure 6is an example in which the timing controller generates an internal synchronization signal based on an external synchronization signal and generates a scan pulse for scanning a display panel based on the internal synchronization signal according to another embodiment of the present invention.

[0162] Reference Figure 6 , an external system (or timing controller 160) according to another embodiment of the present invention outputs a synchronization signal 610. The synchronization signal 610 may be a signal having a frequency increased by a predetermined multiple. In addition, the timing controller 160 may generate an internal synchronization signal including an internal horizontal synchronization signal and an internal vertical synchronization signal based on a synchronization signal (input Xsync) 620 output from the external system and then input.

[0163] For example, the timing controller 160 may generate the internal horizontal synchronization signal 630 based on the synchronization signal 610 input from the external system. Alternatively or additionally, the timing controller 160 may generate the internal vertical synchronization signal using the synchronization signal 610 input from the external system.

[0164] The synchronization signal (Xsync) 610 input from the external system includes a clock of a certain period of time. For example, the synchronization signal (Xsync) 610 may be a signal having a frequency increased four times, and may include clocks 611, 612, 613, and 614.

[0165] According to an embodiment of the present invention, the timing controller 160 may increase the frequency of the synchronization signal (Xsync) 610 (e.g., an external synchronization signal) by a predetermined multiple (e.g., 4 times). For example, increasing the frequency of the synchronization signal (Xsync) 610 by a predetermined multiple (e.g., 4 times) may indicate that the number of clocks of the synchronization signal is increased by a predetermined multiple (e.g., 4 times).

[0166] According to an embodiment of the present invention, the timing controller 160 may generate an internal horizontal synchronization signal (hsync) 630 based on an input synchronization signal (Xsync in) 620 having clocks 621 , 622 , 623 , 624 delayed relative to corresponding clocks 611 , 612 , 613 , 614 in the synchronization signal 610 .

[0167] For example, the timing controller 160 may generate an internal horizontal synchronization signal 630 having a first clock 631. The voltage of the first clock 631 changes from a low level to a high level (e.g., a rising edge) at a point (or time point, such as a starting point of a rising edge) at which the voltage of the third clock 623 (i.e., a clock after the second clock 622) of the input synchronization signal rises from a low level to a high level. For example, jitter 631a may be generated when the voltage of the first clock 631 changes from a low level to a high level. In addition, jitter 631b may be generated when the voltage of the first clock 631 changes from a high level to a low level.

[0168] Similarly, the internal horizontal synchronization signal 630 has a second clock 632 whose voltage changes from a low level to a high level at a point (or time point) at which the voltage of the fourth clock 624 (i.e., the clock after the third clock 623) of the input synchronization signal 620 rises from a low level to a high level. For example, jitter 632a may be generated when the voltage of the second clock 632 changes from a low level to a high level. In addition, jitter 632b may be generated when the voltage of the second clock 632 changes from a high level to a low level.

[0169] For example, the timing controller 160 generates an internal horizontal synchronization signal 630 so that the voltage of the first clock 631 of the internal horizontal synchronization signal 630 changes from a low level to a high level at a point (or time point) when the voltage of the third clock 623 (for example, a clock after the second clock 622) of the input synchronization signal 620 rises from a low voltage to a high voltage, and then, the voltage of the first clock 631 can be maintained at a high level for a determined time period.

[0170] Similarly, the timing controller 160 generates an internal horizontal synchronization signal 630 so that the voltage of the second clock 632 of the internal horizontal synchronization signal 630 changes from a low level to a high level at a point (or time point) when the voltage of the fourth clock 624 (for example, a clock after the third clock 623) of the input synchronization signal 620 rises from a low voltage to a high voltage, and then, the voltage of the second clock 632 remains at a high level for a determined time period.

[0171] Similarly, the timing controller 160 generates the internal horizontal synchronization signal 630 so that the voltage of the nth clock of the internal horizontal synchronization signal 630 changes from a low level to a high level at a point (or time point) at which the voltage of the (n+2)th clock (e.g., the clock after the (n+1)th clock) of the input synchronization signal 620 rises from a low voltage to a high voltage, and then the voltage of the nth clock of the internal horizontal synchronization signal 630 can be maintained at a high level for a certain period of time. That is, the nth clock of the internal horizontal synchronization signal 630 corresponds to the (n+2)th clock (e.g., the clock after the (n+1)th clock) of the input synchronization signal 620, so that the starting points of their rising edges correspond to each other. And there are at least two clocks 621, 622 in the input synchronization signal 620 that do not correspond to any clock in the internal horizontal synchronization signal 630 (which precede the other clocks of the input synchronization signal 620 that correspond to the clocks in the internal horizontal synchronization signal 630). Please note that most of the first clocks 631 in the internal horizontal synchronization signal 630 correspond to the clock 623 in the input synchronization signal 620 (which lags behind the clocks 621 and 622 of the input synchronization signal 620 that do not correspond to any clock in the internal horizontal synchronization signal 630).

[0172] According to an embodiment of the present invention, the timing controller 160 may generate scan pulses 640 and 650 configured to drive the pixels of the display panel 110 based on the internal horizontal synchronization signal 630 .

[0173] For example, the timing controller 160 may generate a scan pulse signal 640 of a clock 641 having a certain period 670 after the voltage of the first clock 631 of the internal horizontal synchronization signal 630 changes from a high level to a low level (e.g., a falling edge). The timing controller 160 may be configured to generate the scan pulse 640 so that when the voltage of the first clock 631 of the internal horizontal synchronization signal 630 drops from a high voltage to a low voltage, the scan pulse 640 drops from a high voltage to a low voltage; and when the voltage of the fourth clock 634 of the internal horizontal synchronization signal 630 drops from a high voltage to a low voltage, the scan pulse 640 dropped to a low voltage rises to a high voltage. The generated scan pulse 640 may be generated based on a point at which the voltage of the first clock 631 of the internal horizontal synchronization signal 630 drops and a point at which the voltage of the fourth clock 634 of the internal horizontal synchronization signal 630 drops. After the voltage of the first clock 631 of the internal horizontal synchronization signal 630 changes from a high level to a low level (e.g., a falling edge), the voltage of the fourth clock 634 of the internal horizontal synchronization signal 630 changes from a high level to a low level (e.g., a falling edge). At this time, the voltage of the clock 641 changes from a low voltage to a high voltage (e.g., a rising edge). For example, after a certain period of time 670 after the voltage of the clock 641 changes from a high voltage to a low voltage (e.g., a falling edge), the voltage of the clock 641 changes from a low voltage to a high voltage (e.g., a rising edge). For example, when the voltage of the clock 641 changes from a high level to a low level, a jitter 641a may be generated. In addition, when the voltage of the clock 641 changes from a low level to a high level, a jitter 641b may be generated. And, the timing controller 160 may output the generated scan pulse 640 to the first scan pulse line SPL1 of the display panel 110. That is, the falling edge and the rising edge of the clock 641 in the scan pulse signal 640 correspond to the falling edges of the two different clocks 631 and 634 of the internal horizontal synchronization signal 630, respectively.

[0174] Similarly, the timing controller 160 may generate a scan pulse 650 of a clock 651 having a determined time period 680 after the voltage of the fifth clock 635 of the internal horizontal synchronization signal 630 changes from a high level to a low level. After the voltage of the fifth clock 635 of the internal horizontal synchronization signal 630 changes from a high level to a low level, the voltage of the eighth clock 638 of the internal horizontal synchronization signal 630 changes from a high level to a low level. At this time, the voltage of the clock 651 changes from a low voltage to a high voltage again. For example, after a determined time period 680 after the voltage of the clock 651 changes from a high voltage to a low voltage, the voltage of the clock 651 changes from a low voltage to a high voltage again. For example, when the voltage of the clock 651 changes from a high level to a low level, a jitter 651a may be generated. In addition, when the voltage of the clock 651 changes from a low level to a high level, a jitter 651b may be generated. And, the timing controller 160 may output the generated scan pulse 650 to the second scan pulse line SPL2 of the display panel 110.

[0175] As described above, the controller 140 (e.g., the timing controller 160) according to the embodiment of the present invention may generate one or more internal synchronization signals including an internal horizontal synchronization signal and an internal vertical synchronization signal based on an input external synchronization signal having a frequency increased by a predetermined multiple, and may generate a scan pulse signal for scanning the display panel 110 based on the generated internal horizontal synchronization signal or the generated internal vertical synchronization signal. For example, the external synchronization signal may be received from an external system or from the timing controller 160.

[0176] According to an embodiment of the present invention, when a synchronization signal having a frequency increased by a predetermined multiple (e.g., 4 times) is input from an external system to the controller 140 (e.g., the timing controller 160), the controller 140 (e.g., the timing controller 160) may generate an internal horizontal synchronization signal so that after the voltage of the second clock 622 of the input synchronization signal 620 drops from a high voltage to a low voltage, the point (or time point) at which the voltage of the third clock 623 of the input synchronization signal 620 rises from a low voltage to a high voltage is consistent with or corresponds to the point (or time point) at which the voltage of the first clock 631 of the internal horizontal synchronization signal 630 rises from a low voltage to a high voltage.

[0177] Although jitters 631a, 631b, 632a, and 632b may be generated in the internal horizontal synchronization signal 630 generated by the timing controller 160 based on the external synchronization signal, Figure 6 The delay between the point (or time point) at which the voltage of the clock 641 of the scan pulse signal 640 changes from a low level to a high level and the point (or time point) at which the voltage of the fourth clock 634 of the internal horizontal synchronization signal 630 changes from a high level to a low level may be less than that in Figure 5The delay between the point (or time point) at which the voltage of the clock 541 in the internal horizontal synchronization signal 530 changes from a low level to a high level and the point (or time point) at which the voltage of the second clock 532 of the internal horizontal synchronization signal 530 changes from a high level to a low level. Figure 6 The jitter in can be less than Figure 5 The jitter in .

[0178] A display device according to an embodiment of the present invention is briefly described as follows.

[0179] A display device according to an embodiment of the present invention may include: a display panel including a plurality of pixels; and a controller configured to control the operation of the display panel. The controller may be configured to generate an internal synchronization signal including one or more of an internal horizontal synchronization signal and an internal vertical synchronization signal based on an input external synchronization signal, wherein the external synchronization signal has a frequency increased by a multiple, and the controller may be configured to generate a scan pulse signal for scanning the display panel based on one or more of the generated internal horizontal synchronization signal and the generated internal vertical synchronization signal.

[0180] According to an embodiment of the present invention, the controller may include: a timing controller, which is configured to generate the internal synchronization signal based on the external synchronization signal, and generate a scan pulse signal configured to drive the display panel based on the generated internal synchronization signal; and a data driver, which is configured to convert the image data transmitted from the timing controller into a data voltage and provide the data voltage to the display panel.

[0181] According to an embodiment of the present invention, the timing controller may be further configured to generate an input synchronization signal having a frequency increased by the multiple based on an external synchronization signal having a frequency increased by the multiple.

[0182] According to an embodiment of the present invention, the timing controller may be further configured to generate an internal horizontal synchronization signal whose voltage changes from a low level to a high level at a time point when the voltage of the input synchronization signal rises from a low level to a high level.

[0183] According to an embodiment of the present invention, the multiple may be 2. The timing controller may be further configured to generate the internal horizontal synchronization signal so that after the voltage of the first clock of the input synchronization signal drops from a first high voltage to a first low voltage, a first point at which the voltage of the second clock of the input synchronization signal rises from a low voltage to a high voltage and a second point at which the voltage of the first clock of the internal horizontal synchronization signal rises from a low level to a high level are consistent with or correspond to each other.

[0184] According to an embodiment of the present invention, the timing controller can also be configured to generate the internal horizontal synchronization signal so that after the voltage of the second clock of the input synchronization signal drops from a high voltage to a low voltage, the third point at which the voltage of the third clock of the input synchronization signal rises from a low voltage to a high voltage is consistent with or corresponds to the fourth point at which the voltage of the second clock of the internal horizontal synchronization signal rises from a low level to a high level.

[0185] According to an embodiment of the present invention, the scan pulse signal may be transmitted to the first scan pulse line. The timing controller may also be configured to generate the scan pulse signal so that when the voltage of the first clock of the internal horizontal synchronization signal drops from a high level to a low level, the scan pulse signal drops from a high voltage level to a low voltage level; and when the voltage of the second clock of the internal horizontal synchronization signal drops from a high level to a low level, the scan pulse signal rises from a low voltage level to a high voltage level.

[0186] According to an embodiment of the present invention, the scan pulse signal may be generated based on a point at which a voltage of a first clock of the internal horizontal synchronization signal falls and a point at which a voltage of a second clock of the internal horizontal synchronization signal falls.

[0187] According to an embodiment of the present invention, the multiple may be 4. The timing controller may also be configured to generate the internal horizontal synchronization signal so that after the voltage of the second clock of the input synchronization signal drops from a high voltage to a low voltage, a first point at which the voltage of the third clock of the input synchronization signal rises from a low voltage to a high voltage and a second point at which the voltage of the first clock of the internal horizontal synchronization signal rises from a low level to a high level are consistent with or correspond to each other.

[0188] According to an embodiment of the present invention, the timing controller can also be configured to generate the internal horizontal synchronization signal so that after the voltage of the third clock of the input synchronization signal drops from a high voltage to a low voltage, the third point at which the voltage of the fourth clock of the input synchronization signal rises from a low voltage to a high voltage is consistent with or corresponds to the fourth point at which the voltage of the second clock of the internal horizontal synchronization signal rises from a low level to a high level.

[0189] According to an embodiment of the present invention, the scan pulse signal may be transmitted to the first scan pulse line. The timing controller may also be configured to generate the scan pulse signal so that when the voltage of the first clock of the internal horizontal synchronization signal drops from a high level to a low level, the scan pulse signal drops from a high voltage level to a low voltage level; and when the voltage of the fourth clock of the internal horizontal synchronization signal drops from a high level to a low level, the scan pulse signal rises from a low voltage level to a high voltage level.

[0190] According to an embodiment of the present invention, the scan pulse signal may be generated based on a point at which a voltage of a first clock of the internal horizontal synchronization signal falls and a point at which a voltage of a fourth clock of the internal horizontal synchronization signal falls.

[0191] According to an embodiment of the present invention, the external synchronization signal may be input to the controller from an external system.

[0192] According to an embodiment of the present invention, the input synchronization signal may be obtained by delaying the external synchronization signal.

[0193] According to an embodiment of the present invention, the timing controller can also be configured to: generate a scan pulse signal with a clock of a time period after the voltage of the third clock of the internal horizontal synchronization signal changes from a high level to a low level, and the scan pulse signal with the clock of the time period is transmitted to the second scan pulse line.

[0194] According to an embodiment of the present invention, the timing controller may be further configured to: after the voltage of the fourth clock of the internal horizontal synchronization signal changes from a high level to a low level, change the voltage of the clock in the time period from a low voltage to a high voltage.

[0195] According to an embodiment of the present invention, the timing controller can also be configured to: generate a scan pulse signal with a clock of a time period after the voltage of the fifth clock of the internal horizontal synchronization signal changes from a high level to a low level, and the scan pulse signal with the clock of the time period is transmitted to the second scan pulse line.

[0196] According to an embodiment of the present invention, the timing controller may be further configured to: when the voltage of the eighth clock of the internal horizontal synchronization signal changes from a high level to a low level, the voltage of the clock in the time period changes from a low voltage to a high voltage.

[0197] According to an embodiment of the present invention, the timing controller and the data driver may be integrated with each other.

[0198] A display device according to an embodiment of the present invention may include: a display panel including a plurality of pixels; and a controller configured to control the operation of the display panel. The controller may be configured to generate an internal synchronization signal based on an input synchronization signal, the input synchronization signal including a plurality of first clocks, the internal synchronization signal including a plurality of second clocks, each second clock corresponding to a first clock, so that a starting time point of a first edge of a second clock corresponds to a starting time point of a first edge of a corresponding first clock, and at least one first clock does not correspond to any second clock and is ahead of any first clock corresponding to a second clock.

[0199] According to an embodiment of the present invention, the first edge of the first clock and the first edge of the second clock may both be rising edges.

[0200] According to an embodiment of the present invention, the input synchronization signal may be generated based on an external synchronization signal, and may have a delay relative to the external synchronization signal.

[0201] According to an embodiment of the present invention, the controller may be configured to generate a scan pulse signal based on the internal synchronization signal.

[0202] According to an embodiment of the present invention, the scan pulse signal may include multiple third clocks, the first edge of the third clock corresponds to the second edge of the second clock of the internal synchronization signal, and the second edge of the third clock corresponds to the second edge of another second clock of the internal synchronization signal.

[0203] According to an embodiment of the present invention, the first edge of the third clock may be a falling edge, the second edge of the third clock may be a rising edge, and the second edge of the second clock may be a falling edge.

[0204] According to an embodiment of the present invention, the at least one first clock that does not correspond to any second clock may include two first clocks that do not correspond to any second clock.

[0205] It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the scope of the invention. Thus, the present invention is intended to cover the modifications and variations of the present invention.

[0206] The various embodiments described above can be combined to provide further embodiments. Aspects of the invention can be modified, if necessary, taking the concepts of the various embodiments to provide still further embodiments.

[0207] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments within the full range of equivalents given to these claims. Therefore, the claims are not limited by the specific embodiments.

Claims

1. A display device, comprising: A display panel including a plurality of pixels; as well as a controller configured to control the operation of the display panel, The controller is configured as follows: generating one or more internal synchronization signals including an internal horizontal synchronization signal and an internal vertical synchronization signal based on an input external synchronization signal, the external synchronization signal having a frequency increased by a multiple; and A scan pulse signal for scanning the display panel is generated based on one or more of the generated internal horizontal synchronization signal and the generated internal vertical synchronization signal.

2. The display device according to claim 1, wherein the controller comprises: a timing controller configured to generate the internal synchronization signal based on the external synchronization signal, and to generate a scan pulse signal configured to drive the display panel based on the generated internal synchronization signal; as well as A data driver is configured to convert image data transmitted from the timing controller into data voltages and provide the data voltages to the display panel. 3 . The display device according to claim 2 , wherein the timing controller is further configured to generate the input synchronization signal having the frequency increased by the multiple based on the external synchronization signal having the frequency increased by the multiple. 4 . The display device according to claim 3 , wherein the timing controller is further configured to generate an internal horizontal synchronization signal whose voltage changes from a low level to a high level at a time point when the voltage of the input synchronization signal rises from a low level to a high level.

5. The display device according to claim 3, wherein the multiple is 2, The timing controller is also configured to generate the internal horizontal synchronization signal so that after the voltage of the first clock of the input synchronization signal drops from a first high voltage to a first low voltage, a first point at which the voltage of the second clock of the input synchronization signal rises from a low voltage to a high voltage corresponds to a second point at which the voltage of the first clock of the internal horizontal synchronization signal rises from a low level to a high level.

6. The display device according to claim 5, wherein the timing controller is further configured to generate the internal horizontal synchronization signal so that after the voltage of the second clock of the input synchronization signal drops from a high voltage to a low voltage, a third point at which the voltage of the third clock of the input synchronization signal rises from a low voltage to a high voltage corresponds to a fourth point at which the voltage of the second clock of the internal horizontal synchronization signal rises from a low level to a high level.

7. The display device according to claim 6, wherein the scan pulse signal is transmitted to a first scan pulse line, The timing controller is also configured to generate the scan pulse signal so that when the voltage of the first clock of the internal horizontal synchronization signal drops from a high level to a low level, the scan pulse signal drops from a high voltage level to a low voltage level; and when the voltage of the second clock of the internal horizontal synchronization signal drops from a high level to a low level, the scan pulse signal rises from a low voltage level to a high voltage level.

8. The display device according to claim 7, wherein the scan pulse signal is generated based on a point at which a voltage of a first clock of the internal horizontal synchronization signal falls and a point at which a voltage of a second clock of the internal horizontal synchronization signal falls.

9. The display device according to claim 3, wherein the multiple is 4, The timing controller is also configured to generate the internal horizontal synchronization signal so that after the voltage of the second clock of the input synchronization signal drops from a high voltage to a low voltage, the first point at which the voltage of the third clock of the input synchronization signal rises from a low voltage to a high voltage corresponds to the second point at which the voltage of the first clock of the internal horizontal synchronization signal rises from a low level to a high level.

10. A display device, comprising: A display panel including a plurality of pixels; as well as a controller configured to control the operation of the display panel, The controller is configured to generate an internal synchronization signal based on an input synchronization signal, the input synchronization signal includes multiple first clocks, and the internal synchronization signal includes multiple second clocks, each second clock corresponds to a first clock, so that the starting time point of the first edge of the second clock corresponds to the starting time point of the first edge of the corresponding first clock, and at least one first clock does not correspond to any second clock and is ahead of any first clock corresponding to the second clock.

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