Panel gate drive circuit based on LTPS CMOS

Abstract

The invention discloses a panel gate drive circuit based on LTPS CMOS, which comprises n levels of cascade units, each level of cascade unit receives a control signal and provides a scanning drive signal G for a panel gate, the STVU end of the Nth level of cascade unit is connected with the NEXT end of the (N-1) th level of cascade unit, and the STVD end of the Nth level of cascade unit is connected with the NEXT end of the (N + 1) th level of cascade unit. Bidirectional scanning is realized on the basis of a basic logic gate of an LTPS CMOS (Low Temperature Poly-Silicon Complementary Metal Oxide Semiconductor).

Description

Technical Field

[0001] The invention relates to a panel gate driving circuit, in particular to a panel gate driving circuit based on LTPS CMOS, and belongs to the technical field of semiconductor integrated circuits. Background Art

[0002] The panel gate drive circuit opens the TFT gate lines of the panel display row by row, and then writes the display information into the pixels through the TFT source lines. When the gate drive pulse of the Nth row is completed, the gate drive pulse of the N+1th row can be output through clock control, and then passed on in this way. Due to the increasing proportion of circuit delay in high-resolution and high-refresh-rate panels, a gate drive circuit with bidirectional scanning is required.

[0003] LTPS CMOS (Low Temperature Poly-Silicon, CMOS) is often used to integrate the gate drive circuit of the panel display with the array process on a glass substrate or a flexible panel. This technology also has the low power consumption, high hole mobility, high electron mobility, and noise tolerance of CMOS circuits, and is also used to make other integrated circuit chips.

[0004] Therefore, it is necessary to design a panel gate drive circuit based on the basic logic gates of LTPS CMOS and using bidirectional scanning. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a panel gate driving circuit based on LTPS CMOS, which is based on the basic logic gates of LTPS CMOS and realizes bidirectional scanning.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is: A panel gate drive circuit based on LTPS CMOS includes n-stage cascade units, each stage of the cascade unit receives a control signal and provides a scan drive signal G to the panel gate, wherein the STVU end of the N-th stage cascade unit is connected to the NEXT end of the N-1-th stage cascade unit, and the STVD end of the N-th stage cascade unit is connected to the NEXT end of the N+1-th stage cascade unit.

[0007] Further, the control signal includes a global clock signal CLK1, a global clock signal CLK2, a global top-down scan control signal U2D, a global bottom-up scan control signal D2U and a global reset signal GRESET, the CKV1 end of the Nth level cascade unit is connected to the global clock signal CLK1, the CKV2 end of the Nth level cascade unit is connected to the global clock signal CLK2, the UD end of the Nth level cascade unit is connected to the global top-down scan control signal U2D, the DU end of the Nth level cascade unit is connected to the global bottom-up scan control signal D2U, the RESET end of the Nth level cascade unit is connected to the global reset signal GRESET, the CKV1 end of the N+1th level cascade unit and the N-1th level cascade unit is connected to the global clock signal CLK2, and the CKV2 end of the N+1th level cascade unit and the N-1th level cascade unit is connected to the global clock signal CLK1.

[0008] Furthermore, the NEXT terminal of the cascade unit outputs a next-level signal output control signal.

[0009] Further, the cascade unit includes a video control switch, an inverter INV1, a latch, a reset transistor T1, an enable NAND gate N1 and an inverter INV4, the first input end of the video control switch serves as the UD end of the cascade unit, the second input end of the video control switch serves as the DU end of the cascade unit, the third input end of the video control switch serves as the STVU end of the cascade unit, the fourth input end of the video control switch serves as the STVD end of the cascade unit, the output end of the video control switch is connected to the input end of the inverter INV1, the output end of the inverter INV1 is connected to the first input end of the latch, the second input end of the latch serves as the cascade unit, and the output end of the video control switch is connected to the input end of the inverter INV1. The CKV1 terminal of the cascade unit, the third input terminal of the latch serves as the CKV2 terminal of the cascade unit and is connected to the first input terminal of the enable NAND gate N1, the fourth input terminal of the latch is connected to the drain of the reset transistor T1, the source of the reset transistor T1 is connected to the global high potential VGH, the gate of the reset transistor T1 serves as the RESET terminal of the cascade unit, the output terminal of the latch is connected to the second input terminal of the enable NAND gate N1 and serves as the NEXT terminal of the cascade unit, the output terminal of the enable NAND gate N1 is connected to the input terminal of the inverter INV4, the output terminal of the inverter INV4 serves as the output terminal of the cascade unit and generates a scan drive signal G.

[0010] Further, the video control switch includes a CMOS transmission gate TG1 and a CMOS transmission gate TG2, the IN end of the CMOS transmission gate TG1 serves as the third input end of the video control switch, the IN end of the CMOS transmission gate TG2 serves as the fourth input end of the video control switch, the OUT end of the CMOS transmission gate TG1 is connected to the OUT end of the CMOS transmission gate TG2 and serves as the output end of the video control switch, the CN end of the CMOS transmission gate TG1 is connected to the CP end of the CMOS transmission gate TG2 and serves as the first input end of the video control switch, and the CP end of the CMOS transmission gate TG1 is connected to the CN end of the CMOS transmission gate TG2 and serves as the second input end of the video control switch.

[0011] Further, the latch includes a CMOS transmission gate TG3, a CMOS transmission gate TG4, an inverter INV2 and an inverter INV3, the IN end of the CMOS transmission gate TG3 serves as the first input end of the latch, the OUT end of the CMOS transmission gate TG3 is connected to the OUT end of the CMOS transmission gate TG4 and the input end of the inverter INV2 and serves as the fourth input end of the latch, the CN end of the CMOS transmission gate TG3 is connected to the CP end of the CMOS transmission gate TG4 and serves as the second input end of the latch, the CP end of the CMOS transmission gate TG3 is connected to the CN end of the CMOS transmission gate TG4 and serves as the third input end of the latch, the output end of the inverter INV2 is connected to the input end of the inverter INV3 and serves as the output end of the latch, and the output end of the inverter INV3 is connected to the IN end of the CMOS transmission gate TG4.

[0012] Furthermore, the inverter includes a transistor T2 and a transistor T3, the gate of the transistor T2 is connected to the gate of the transistor T3 and serves as the input end of the inverter, the source of the transistor T2 is connected to the global high potential VGH, the source of the transistor T3 is connected to the global low potential VGL, and the drain of the transistor T2 is connected to the drain of the transistor T3 and serves as the output end of the inverter.

[0013] Further, the CMOS transmission gate includes a transistor T4 and a transistor T5, the drain of the transistor T4 is connected to the drain of the transistor T5 and serves as the IN terminal of the CMOS transmission gate, the source of the transistor T4 is connected to the source of the transistor T5 and serves as the OUT terminal of the CMOS transmission gate, the gate of the transistor T4 serves as the CP terminal of the CMOS transmission gate, and the gate of the transistor T5 serves as the CN terminal of the CMOS transmission gate.

[0014] Further, the enabling NAND gate includes a transistor T6, a transistor T7, a transistor T8 and a transistor T9, the source of the transistor T6 is connected to the source of the transistor T7 and connected to the global high potential VGH, the gate of the transistor T6 is connected to the gate of the transistor T8 and serves as a first input terminal of the enabling NAND gate, the drain of the transistor T6 is connected to the drain of the transistor T7 and the drain of the transistor T8 and serves as an output terminal of the enabling NAND gate, the gate of the transistor T7 is connected to the gate of the transistor T9 and serves as a second input terminal of the enabling NAND gate, the source of the transistor T8 is connected to the drain of the transistor T9, and the source of the transistor T9 is connected to the global low potential VGL.

[0015] Compared with the prior art, the present invention has the following advantages and effects: the present invention provides a panel gate drive circuit based on LTPS CMOS, which can integrate Array process to achieve the purpose of less peripheral circuits, low manufacturing cost, narrow frame, high resolution, high degree of freedom, flexible screen and customizable design; the present invention adopts bidirectional GOA scanning to improve the panel refresh rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of a panel gate driving circuit based on LTPS CMOS of the present invention.

[0017] Figure 2 is a circuit diagram of the cascade unit of the present invention.

[0018] Figure 3 Schematic diagram of the inverter of the present invention.

[0019] Figure 4 Schematic diagram of a CMOS transmission gate of the present invention.

[0020] Figure 5 Schematic diagram of an enable NAND gate of the present invention.

[0021] Figure 6 The present invention is a simulation waveform diagram of a panel gate driving circuit based on LTPS CMOS. DETAILED DESCRIPTION

[0022] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0023] like Figure 1As shown, a panel gate driving circuit based on LTPS CMOS of the present invention comprises n-stage cascade units, each stage of the cascade unit receives a control signal and provides a scan driving signal G to the panel gate, wherein the STVU end of the N-th stage cascade unit is connected to the NEXT end of the N-1-th stage cascade unit, and the STVD end of the N-th stage cascade unit is connected to the NEXT end of the N+1-th stage cascade unit.

[0024] The control signal includes a global clock signal CLK1, a global clock signal CLK2, a global top-down scan control signal U2D, a global bottom-up scan control signal D2U and a global reset signal GRESET. The CKV1 end of the Nth level cascade unit is connected to the global clock signal CLK1, the CKV2 end of the Nth level cascade unit is connected to the global clock signal CLK2, the UD end of the Nth level cascade unit is connected to the global top-down scan control signal U2D, the DU end of the Nth level cascade unit is connected to the global bottom-up scan control signal D2U, the RESET end of the Nth level cascade unit is connected to the global reset signal GRESET, the CKV1 end of the N+1th level cascade unit and the N-1th level cascade unit is connected to the global clock signal CLK2, and the CKV2 end of the N+1th level cascade unit and the N-1th level cascade unit is connected to the global clock signal CLK1.

[0025] The NEXT terminal of the cascade unit outputs the next-level signal output control signal.

[0026] like Figure 2 As shown, the cascade unit includes a video control switch 121, an inverter INV1, a latch 122, a reset transistor T1, an enable NAND gate N1 and an inverter INV4, the first input end of the video control switch 121 serves as the UD end of the cascade unit, the second input end of the video control switch 121 serves as the DU end of the cascade unit, the third input end of the video control switch 121 serves as the STVU end of the cascade unit, the fourth input end of the video control switch 121 serves as the STVD end of the cascade unit, the output end of the video control switch 121 is connected to the input end of the inverter INV1, the output end of the inverter INV1 is connected to the first input end of the latch 122, the fourth input end of the latch 122 serves as the STVU end of the cascade unit, the fourth input end of the video control switch 121 serves as the STVD end of the cascade unit, the output end of the video control switch 121 is connected to the input end of the inverter INV1, the output end of the inverter INV1 is connected to the first input end of the latch 122, the The second input terminal serves as the CKV1 terminal of the cascade unit, the third input terminal of the latch 122 serves as the CKV2 terminal of the cascade unit and is connected to the first input terminal of the enable NAND gate N1, the fourth input terminal of the latch 122 is connected to the drain of the reset transistor T1, the source of the reset transistor T1 is connected to the global high potential VGH, the gate of the reset transistor T1 serves as the RESET terminal of the cascade unit, the output terminal of the latch 122 is connected to the second input terminal of the enable NAND gate N1 and serves as the NEXT terminal of the cascade unit, the output terminal of the enable NAND gate N1 is connected to the input terminal of the inverter INV4, the output terminal of the inverter INV4 serves as the output terminal of the cascade unit and generates a scan drive signal G.

[0027] like Figure 2 As shown, the video control switch 121 includes a CMOS transmission gate TG1 and a CMOS transmission gate TG2, the IN terminal of the CMOS transmission gate TG1 serves as the third input terminal of the video control switch, the IN terminal of the CMOS transmission gate TG2 serves as the fourth input terminal of the video control switch, the OUT terminal of the CMOS transmission gate TG1 is connected to the OUT terminal of the CMOS transmission gate TG2 and serves as the output terminal of the video control switch, the CN terminal of the CMOS transmission gate TG1 is connected to the CP terminal of the CMOS transmission gate TG2 and serves as the first input terminal of the video control switch, and the CP terminal of the CMOS transmission gate TG1 is connected to the CN terminal of the CMOS transmission gate TG2 and serves as the second input terminal of the video control switch.

[0028] like Figure 2 As shown, the latch 122 includes a CMOS transmission gate TG3, a CMOS transmission gate TG4, an inverter INV2 and an inverter INV3, the IN terminal of the CMOS transmission gate TG3 serves as the first input terminal of the latch, the OUT terminal of the CMOS transmission gate TG3 is connected to the OUT terminal of the CMOS transmission gate TG4 and the input terminal of the inverter INV2 and serves as the fourth input terminal of the latch, the CN terminal of the CMOS transmission gate TG3 is connected to the CP terminal of the CMOS transmission gate TG4 and serves as the second input terminal of the latch, the CP terminal of the CMOS transmission gate TG3 is connected to the CN terminal of the CMOS transmission gate TG4 and serves as the third input terminal of the latch, the output terminal of the inverter INV2 is connected to the input terminal of the inverter INV3 and serves as the output terminal of the latch, and the output terminal of the inverter INV3 is connected to the IN terminal of the CMOS transmission gate TG4.

[0029] like Figure 3 As shown, the inverter includes a transistor T2 and a transistor T3, the gate of the transistor T2 is connected to the gate of the transistor T3 and serves as the input end of the inverter, the source of the transistor T2 is connected to the global high potential VGH, the source of the transistor T3 is connected to the global low potential VGL, and the drain of the transistor T2 is connected to the drain of the transistor T3 and serves as the output end of the inverter.

[0030] like Figure 4 As shown, the CMOS transmission gate includes a transistor T4 and a transistor T5, the drain of the transistor T4 is connected to the drain of the transistor T5 and serves as the IN terminal of the CMOS transmission gate, the source of the transistor T4 is connected to the source of the transistor T5 and serves as the OUT terminal of the CMOS transmission gate, the gate of the transistor T4 serves as the CP terminal of the CMOS transmission gate, and the gate of the transistor T5 serves as the CN terminal of the CMOS transmission gate.

[0031] like Figure 5As shown, the enable NAND gate includes a transistor T6, a transistor T7, a transistor T8 and a transistor T9, the source of the transistor T6 is connected to the source of the transistor T7 and connected to the global high potential VGH, the gate of the transistor T6 is connected to the gate of the transistor T8 and serves as the first input terminal of the enable NAND gate, the drain of the transistor T6 is connected to the drain of the transistor T7 and the drain of the transistor T8 and serves as the output terminal of the enable NAND gate, the gate of the transistor T7 is connected to the gate of the transistor T9 and serves as the second input terminal of the enable NAND gate, the source of the transistor T8 is connected to the drain of the transistor T9, and the source of the transistor T9 is connected to the global low potential VGL.

[0032] The CMOS transmission gates TG1-TG4, inverters INV1-INV4 and enable NAND gate N1 are all composed of complementary ntft and ptft transistors, and the transistors T1-T9 are all LTPS CMOS transistors.

[0033] like Figure 6 As shown, the working principle of the present invention is: The video control switch is a bidirectional selection switch composed of a CMOS transmission gate TG1 and a CMOS transmission gate TG2. The global top-to-bottom scan control signal U2D and the global bottom-to-top scan control signal D2U are opposite signals. When the global top-to-bottom scan control signal U2D is a global high potential VGH and the global bottom-to-top scan control signal D2U is a global low potential VGL, the video control signal STV enters the inverter INV1 from the STVU end through the CMOS transmission gate TG1 to obtain a reverse STV signal NSTV.

[0034] The global clock signal CLK1 and the global clock signal CLK2 are opposite clock signals, and the pulse width of the video control signal STV covers the width of the global clock signal CLK1.

[0035] When the first rising edge of the global clock signal CLK1 arrives, the working state of the Nth stage cascade unit is: the CKV1 end of the Nth stage cascade unit is the global high potential VGH, the CKV2 end is the global low potential VGL, the video control signal STV is the global high potential VGH, the video control signal STV enters the inverter INV1 from the STVU end through the CMOS transmission gate TG1, the output signal NSTV of the inverter INV1 is the global low potential VGL, at this time, the CMOS transmission gate TG3 is opened to allow the signal NSTV to enter the latch 122 of the Nth stage cascade unit and obtain the global high potential VGH at the NEXT end of the Nth stage cascade unit, the NEXT end and the CKV2 end pass through the enable NAND gate N1, the enable NAND gate N1 output is the global high potential VGH, and then pass through the inverter INV4, the output end of the inverter INV4 is the global low potential VGL.

[0036] At this time, the working state of the N+1th cascade unit: Since the CKV1 end of the N+1th cascade unit is at the global low potential VGL, the CKV2 end is at the global high potential VGH, and the CMOS transmission gate TG3 of the latch of the N+1th cascade unit is in the closed state. The NEXT end of the N+1th cascade unit is not affected by the Nth cascade unit at this time and is still at the global low potential VGL. The NEXT end and the CKV2 end are connected through the enable NAND gate N1, and the output of the enable NAND gate N1 is the global high potential VGH, and then through the inverter INV4, the output end of the inverter INV4 is the global low potential VGL.

[0037] When the first falling edge of the global clock signal CLK1 arrives, the working state of the Nth stage cascade unit is: when the CKV1 end of the Nth stage cascade unit is the global low potential VGL and the CKV2 end is the global high potential VGH, the CMOS transmission gate TG3 is closed, the CMOS transmission gate TG4 is opened, and the latch locks the current state at the NEXT end as the global high potential VGH. The NEXT end and the CKV2 end of the Nth stage cascade unit pass through the enable NAND gate N1, and the enable NAND gate N1 outputs the global low potential VGL, and then passes through the inverter INV4, and the inverter INV4 outputs the global high potential VGH.

[0038] At this time, the working state of the N+1th cascade unit is: since the CKV1 end of the N+1th cascade unit is the global high potential VGH, the CKV2 end is the global low potential VGL, the CMOS transmission gate TG3 is open, and the CMOS transmission gate TG4 is closed, the NEXT end of the N+1th cascade unit is the global high potential VGH, and the global high potential VGH is obtained at the NEXT end of the N+1th cascade unit. The NEXT end and the CKV2 end of the N+1th cascade unit are connected through the enable NAND gate N1, and the output of the enable NAND gate N1 is the global high potential VGH, and then the output of the inverter INV4 is still the global low potential VGL.

[0039] When the second rising edge of the global clock signal CLK1 arrives, the working state of the Nth stage cascade unit is: the CKV1 end of the Nth stage cascade unit is the global high potential VGH, the CKV2 end is the global low potential VGL, the video control signal STV is the global low potential VGL, the video control signal STV enters the inverter INV1 from the STVU end through the CMOS transmission gate TG1, the output signal NSTV of the inverter INV1 is the global high potential VGH, at this time, the CMOS transmission gate TG3 is opened to allow the signal NSTV to enter the latch 122 of the Nth stage cascade unit and obtain the global low potential VGL at the NEXT end of the Nth stage cascade unit, the NEXT end and the CKV2 end pass through the enable NAND gate N1, the enable NAND gate N1 output is the global high potential VGH, and then pass through the inverter INV4, the output end of the inverter INV4 is the global low potential VGL.

[0040] At this time, the working state of the N+1th cascade unit is: since the CKV1 end of the N+1th cascade unit is the global low potential VGL, the CKV2 end is the global high potential VGH, the CMOS transmission gate TG3 is closed, and the CMOS transmission gate TG4 is opened, the NEXT end of the N+1th cascade unit locks the global high potential VGH. The NEXT end and the CKV2 end of the N+1th cascade unit are connected through the enable NAND gate N1, and the enable NAND gate N1 outputs the global low potential VGL, and then outputs the global high potential VGH through the inverter INV4. The row-by-row scanning from the Nth cascade unit to the output end of the N+1th cascade unit is realized.

[0041] When the global reset signal GRESET is low, the reset transistor T1 is turned on, and after the global high potential VGH passes through the inverter INV2, the NEXT terminal signal output of the Nth stage cascade unit is the global low potential VGL, the output terminal of the enable NAND gate N1 is the global high potential VGH, and the output terminal of the inverter INV4 is the global low potential VGL.

[0042] The present invention provides a panel gate drive circuit based on LTPS CMOS, which can integrate Array process to achieve the purpose of less peripheral circuits, low manufacturing cost, narrow frame, high resolution, high degree of freedom, flexible screen and customizable design; the present invention adopts bidirectional GOA scanning to improve the panel refresh rate.

[0043] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A panel gate drive circuit based on LTPS CMOS, characterized in that: It comprises n cascade units, each cascade unit receives a control signal and provides a scan drive signal G to the panel gate, wherein the STVU end of the Nth cascade unit is connected to the NEXT end of the N-1th cascade unit, and the STVD end of the Nth cascade unit is connected to the NEXT end of the N+1th cascade unit.

2. The panel gate driving circuit based on LTPS CMOS according to claim 1, characterized in that: The control signal includes a global clock signal CLK1, a global clock signal CLK2, a global top-down scan control signal U2D, a global bottom-up scan control signal D2U and a global reset signal GRESET. The CKV1 end of the Nth cascade unit is connected to the global clock signal CLK1, the CKV2 end of the Nth cascade unit is connected to the global clock signal CLK2, the UD end of the Nth cascade unit is connected to the global top-down scan control signal U2D, the DU end of the Nth cascade unit is connected to the global bottom-up scan control signal D2U, the RESET end of the Nth cascade unit is connected to the global reset signal GRESET, the CKV1 ends of the N+1th cascade unit and the N-1th cascade unit are connected to the global clock signal CLK2, and the CKV2 ends of the N+1th cascade unit and the N-1th cascade unit are connected to the global clock signal CLK1.

3. The panel gate driving circuit based on LTPS CMOS according to claim 1, characterized in that: The NEXT terminal of the cascade unit outputs a next-level signal output control signal.

4. The panel gate driving circuit based on LTPS CMOS according to claim 1, characterized in that: The cascade unit includes a video control switch, an inverter INV1, a latch, a reset transistor T1, an enable NAND gate N1 and an inverter INV4, the first input end of the video control switch serves as the UD end of the cascade unit, the second input end of the video control switch serves as the DU end of the cascade unit, the third input end of the video control switch serves as the STVU end of the cascade unit, the fourth input end of the video control switch serves as the STVD end of the cascade unit, the output end of the video control switch is connected to the input end of the inverter INV1, the output end of the inverter INV1 is connected to the first input end of the latch, the second input end of the latch serves as the cascade unit The third input terminal of the latch serves as the CKV2 terminal of the cascade unit and is connected to the first input terminal of the enable NAND gate N1, the fourth input terminal of the latch is connected to the drain of the reset transistor T1, the source of the reset transistor T1 is connected to the global high potential VGH, the gate of the reset transistor T1 serves as the RESET terminal of the cascade unit, the output terminal of the latch is connected to the second input terminal of the enable NAND gate N1 and serves as the NEXT terminal of the cascade unit, the output terminal of the enable NAND gate N1 is connected to the input terminal of the inverter INV4, the output terminal of the inverter INV4 serves as the output terminal of the cascade unit and generates a scan drive signal G.

5. The panel gate driving circuit based on LTPS CMOS according to claim 4, characterized in that: The video control switch comprises a CMOS transmission gate TG1 and a CMOS transmission gate TG2, wherein the IN end of the CMOS transmission gate TG1 serves as the third input end of the video control switch, the IN end of the CMOS transmission gate TG2 serves as the fourth input end of the video control switch, the OUT end of the CMOS transmission gate TG1 is connected to the OUT end of the CMOS transmission gate TG2 and serves as the output end of the video control switch, the CN end of the CMOS transmission gate TG1 is connected to the CP end of the CMOS transmission gate TG2 and serves as the first input end of the video control switch, and the CP end of the CMOS transmission gate TG1 is connected to the CN end of the CMOS transmission gate TG2 and serves as the second input end of the video control switch.

6. The panel gate driving circuit based on LTPS CMOS according to claim 4, characterized in that: The latch comprises a CMOS transmission gate TG3, a CMOS transmission gate TG4, an inverter INV2 and an inverter INV3, the IN end of the CMOS transmission gate TG3 serves as the first input end of the latch, the OUT end of the CMOS transmission gate TG3 is connected to the OUT end of the CMOS transmission gate TG4 and the input end of the inverter INV2 and serves as the fourth input end of the latch, the CN end of the CMOS transmission gate TG3 is connected to the CP end of the CMOS transmission gate TG4 and serves as the second input end of the latch, the CP end of the CMOS transmission gate TG3 is connected to the CN end of the CMOS transmission gate TG4 and serves as the third input end of the latch, the output end of the inverter INV2 is connected to the input end of the inverter INV3 and serves as the output end of the latch, and the output end of the inverter INV3 is connected to the IN end of the CMOS transmission gate TG4.

7. A panel gate driving circuit based on LTPS CMOS according to claim 5 or 6, characterized in that: The inverter comprises a transistor T2 and a transistor T3, wherein the gate of the transistor T2 is connected to the gate of the transistor T3 and serves as the input end of the inverter, the source of the transistor T2 is connected to the global high potential VGH, the source of the transistor T3 is connected to the global low potential VGL, and the drain of the transistor T2 is connected to the drain of the transistor T3 and serves as the output end of the inverter.

8. The panel gate driving circuit based on LTPS CMOS according to claim 5 or 6, characterized in that: The CMOS transmission gate includes a transistor T4 and a transistor T5, the drain of the transistor T4 is connected to the drain of the transistor T5 and serves as the IN terminal of the CMOS transmission gate, the source of the transistor T4 is connected to the source of the transistor T5 and serves as the OUT terminal of the CMOS transmission gate, the gate of the transistor T4 serves as the CP terminal of the CMOS transmission gate, and the gate of the transistor T5 serves as the CN terminal of the CMOS transmission gate.

9. The panel gate driving circuit based on LTPS CMOS according to claim 5 or 6, characterized in that: The enabling NAND gate comprises a transistor T6, a transistor T7, a transistor T8 and a transistor T9, the source of the transistor T6 is connected to the source of the transistor T7 and to the global high potential VGH, the gate of the transistor T6 is connected to the gate of the transistor T8 and serves as the first input terminal of the enabling NAND gate, the drain of the transistor T6 is connected to the drain of the transistor T7 and the drain of the transistor T8 and serves as the output terminal of the enabling NAND gate, the gate of the transistor T7 is connected to the gate of the transistor T9 and serves as the second input terminal of the enabling NAND gate, the source of the transistor T8 is connected to the drain of the transistor T9, and the source of the transistor T9 is connected to the global low potential VGL.

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