Display device and pixel driving method thereof

Abstract

The invention discloses a display device and a pixel driving method thereof. The display device includes a pixel array, a timing controller, a gate driver, a source driver, and a light emitting driving circuit. The pixel array has a plurality of self-luminous pixel circuits. The time schedule controller provides pixel voltage data, at least two scanning starting signals and a light emitting starting signal. The gate driver divides a single picture period into a plurality of sub-picture periods based on a scan start signal to turn on the self-luminous pixel circuit column by column. The source driver provides a plurality of pixel voltages corresponding to the self-luminous pixel circuit in each sub-picture period based on the pixel voltage data so as to determine a driving current of a light-emitting element of the self-luminous pixel circuit. The light-emitting driving circuit provides a plurality of light-emitting signals to the self-light-emitting pixel circuit based on the light-emitting start signal.

Description

Technical Field

[0001] The present invention relates to a display device, and in particular to a display device and a pixel driving method thereof. Background Art

[0002] An LED display is a self-luminous display using light-emitting diodes, that is, self-luminous pixels with light-emitting diodes are arranged on the display panel. The driving methods of self-luminous pixels are roughly divided into pulse width modulation (PWM) circuit driving and pulse amplitude modulation (PAM) circuit driving.

[0003] In the pulse width modulation circuit driving mode, the current size is controlled by the pulse amplitude modulation area, and the on and off time of the driving transistor located in the current path is controlled by the pulse width modulation area to control the brightness and light-emitting time of the light-emitting diode. However, the above driving method may not reach the ideal value of the low grayscale current due to the resistance and capacitance (RC) delay and the insufficient carrier mobility of the driving transistor; and when the low grayscale current is too small, the efficiency of the light-emitting diode deteriorates and becomes sensitive to variations; furthermore, the transistor is also sensitive to variations in the low grayscale current operation range, and the current is easily affected by process variations.

[0004] On the other hand, in the pulse amplitude modulation circuit driving mode, the duty cycle of the fixed current is used for driving, so the pulse width of the current is not affected by the variation of the resistor, capacitor and transistor, and the magnitude of the current is controlled by the driving transistor located in the current path to determine the brightness of the light-emitting diode. However, in the above driving mode, the efficiency of the light-emitting diode will deteriorate due to the small current and it will be sensitive to the current variation; although the problem of small current can be solved by adjusting the duty cycle of the light-emitting diode as a whole, this will limit the brightness of the high gray scale. Summary of the invention

[0005] The present invention provides a display device and a pixel driving method thereof. By dividing a single frame period into a plurality of sub-frame periods, a pulse width modulation circuit architecture can be used to achieve the effect of a pulse width modulation light-emitting duty cycle without adding additional signals or circuits.

[0006] The display device of the present invention includes a pixel array, a timing controller, a gate driver, a source driver, and a light-emitting driving circuit. The pixel array has a plurality of self-luminous pixel circuits arranged in an array, wherein each of the self-luminous pixel circuits has a light-emitting element. The timing controller receives display data to provide a pixel voltage data, at least two scan start signals, and a light-emitting start signal in a single frame period. The gate driver receives at least two scan start signals and is coupled to the self-luminous pixel circuit to cut the single frame period into a plurality of sub-frame periods based on at least two scan start signals, and to turn on the self-luminous pixel circuit row by row in each of the sub-frame periods. The source driver receives pixel voltage data to provide a plurality of pixel voltages corresponding to the self-luminous pixel circuit in each of the sub-frame periods, wherein each of the light-emitting elements of the self-luminous pixel circuit determines a driving current flowing through the light-emitting element based on the received pixel voltage. The light-emitting driving circuit receives the light-emitting start signal to provide a plurality of light-emitting signals to the self-luminous pixel circuit to determine a plurality of light-emitting times of the self-luminous pixel circuit.

[0007] The pixel driving method of the display device of the present invention comprises the following steps. A single frame period is divided into a plurality of sub-frame periods by a timing controller. A plurality of self-luminous pixel circuits are turned on column by column in each of the sub-frame periods by a gate driver, wherein each of the self-luminous pixel circuits has a light-emitting element. A plurality of pixel voltages are provided to the corresponding self-luminous pixel circuits in each of the sub-frame periods based on display data by a source driver, wherein each of the light-emitting elements of the self-luminous pixel circuit determines a driving current flowing through the light-emitting element based on the received pixel voltage. A plurality of light-emitting signals are provided to the self-luminous pixel circuit by a light-emitting driving circuit to determine a plurality of light-emitting times of the self-luminous pixel circuit.

[0008] Based on the above, in the display device and pixel driving method thereof of the embodiment of the present invention, the timing controller divides a single frame period into multiple sub-frame periods, so that each self-luminous pixel circuit writes data once in each sub-frame period, that is, the brightness lit / illuminated / provided by each self-luminous pixel circuit in the sub-frame period is independent of each other, whereby the self-luminous pixel circuit can only use a pulse amplitude modulation circuit architecture, but still has the effect of a pulse width modulation light emission duty cycle.

[0009] In order to make the above features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 FIG. 4 is a system diagram of a display device according to an embodiment of the present invention.

[0011] Figure 2AFIG. 4 is a schematic diagram of a driving waveform of a display device at a low gray scale according to an embodiment of the present invention.

[0012] Figure 2B FIG. 4 is a schematic diagram of a driving waveform of a display device at a low gray scale according to an embodiment of the present invention.

[0013] Figure 3 FIG. 4 is a circuit diagram of a self-luminous pixel circuit of a display device according to an embodiment of the present invention.

[0014] Figures 4A to 4C FIG. 1 is a schematic diagram of characteristic curves of forward voltages of a red light emitting diode, a green light emitting diode, and a blue light emitting diode of a self-luminous pixel circuit according to an embodiment of the present invention.

[0015] Figure 4D FIG. 4 is a schematic diagram of a current-voltage characteristic curve of a transistor in a self-luminous pixel circuit according to an embodiment of the present invention.

[0016] Figure 5A FIG. 4 is a schematic diagram of scanning a pixel array of a display device according to an embodiment of the present invention.

[0017] Figure 5B FIG. 4 is a waveform diagram of a single horizontal scanning period of a pixel array of a display device according to an embodiment of the present invention.

[0018] Figures 6 to 11 FIG. 4 is a schematic diagram of driving waveforms of a display device according to an embodiment of the present invention.

[0019] Fig.12 FIG. 4 is a system diagram of a pixel driving method of a display device according to an embodiment of the present invention.

[0020] Description of reference numerals:

[0021] 100: Display device

[0022] 110: Timing controller

[0023] 120: Power controller

[0024] 130: Gate Driver

[0025] 140: Source driver

[0026] 150: Light-emitting drive circuit

[0027] 160: Pixel Array

[0028] 310: Light-emitting element driving circuit

[0029] 320: Data programming circuit

[0030] 330: Reset circuit

[0031] 340: Test Circuit

[0032] C1: First capacitor

[0033] C2: Second capacitor

[0034] CS: Scan compensation signal

[0035] CTDR: Driver Circuit

[0036] DATAex: Displaying Data

[0037] DATApxl: pixel voltage

[0038] DL1: Light Emitting Diode

[0039] EM: Luminescent signal

[0040] Frame, Frame1, Frame2, Frame3, Frame4, Frame5, Frame6, Frame7, Frame8: Single frame period

[0041] FS1, FS2, FS11, FS12, FS21, FS22, FS31 to FS34, FS41 to FS44, FS51 to FS5(m+2), FS61 to FS6(m+2), FS71, FS72, FS81, FS82: Sub-screen period

[0042] H[n]: Horizontal scanning period

[0043] Idr: driving current

[0044] L0: Grayscale value

[0045] PX, PXa: Self-luminous pixel circuit

[0046] Row[1]: first column

[0047] Row[n]: nth column

[0048] RS: reset signal

[0049] STVEM: luminescent start signal

[0050] STVG1, STVG2: Scan start signal

[0051] T1: First transistor

[0052] T10: The tenth transistor

[0053] T11: Eleventh transistor

[0054] T2: Second transistor

[0055] T3: The third transistor

[0056] T4: The fourth transistor

[0057] T5: The fifth transistor

[0058] T6: Sixth transistor

[0059] T7: Seventh transistor

[0060] T8: Eighth transistor

[0061] T9: Ninth Transistor

[0062] TDW1, TDW2: Scanning timing

[0063] Test: Test signal

[0064] VC: voltage control signal

[0065] VDD: system high voltage

[0066] Vgt: Gate control voltage

[0067] Vini: initial voltage

[0068] Vop: operating voltage

[0069] Vref: reference voltage

[0070] Vsig: pixel voltage

[0071] VSS: System low voltage

[0072] Vst: test result voltage

[0073] Vsync: vertical synchronization signal

[0074] W1, W2, W3, W4: Pulse width

[0075] WS1: First scanning signal

[0076] WS2: Second scanning signal

[0077] S110, S120, S130, S140: Steps DETAILED DESCRIPTION

[0078] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present invention, and will not be interpreted as an idealized or overly formal meaning unless explicitly defined as such herein.

[0079] It should be understood that although the terms "first", "second", "third", etc. can be used to describe various elements, components, regions, layers and / or parts in this article, these elements, components, regions, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the "first element", "component", "region", "layer" or "part" discussed below can be referred to as a second element, component, region, layer or part without departing from the teachings of this article.

[0080] The terms used herein are only for the purpose of describing specific embodiments and are not restrictive. As used herein, unless the content clearly indicates, the singular forms "one", "an" and "the" are intended to include plural forms, including "at least one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more related listed items. It should also be understood that when used in this specification, the terms "include" and / or "include" specify the presence and / or parts of the features, regions, entireties, steps, operations, elements, but do not exclude the presence or addition of one or more other features, regions, entireties, steps, operations, elements, parts and / or their combinations.

[0081] Figure 1 is a system diagram of a display device according to an embodiment of the present invention. Figure 1 In this embodiment, the display device 100 includes a timing controller 110 , a power controller 120 , a gate driver 130 , a source driver 140 , a light emitting driving circuit 150 and a pixel array 160 .

[0082] The pixel array 160 has a plurality of self-luminous pixel circuits PX arranged in an array, wherein each of the self-luminous pixel circuits PX has a light-emitting element (e.g., a light-emitting diode DL1) and a driving circuit CTDR for driving the light-emitting element. The power controller 120 is coupled to the timing controller 110 and the pixel array 160 to provide an operating voltage Vop required for the timing controller 110 to operate, and to provide a system high voltage VDD, a system low voltage VSS, an initial voltage Vini, and a reference voltage Vref required for the operation of the self-luminous pixel circuits PX.

[0083] The timing controller 110 is coupled to the gate driver 130, the source driver 140, and the light-emitting driving circuit 150, and receives display data DATAex and a vertical synchronization signal Vsync. The timing controller 110 defines a time interval of a single frame period Frame based on the vertical synchronization signal Vsync. In addition, in a single frame period Frame, the timing controller 110 provides a pixel voltage DATApx1 to the source driver 140 based on the display data DATAex, provides at least two scan start signals (such as STVG1 and STVG2) to the gate driver 130, and provides a light-emitting start signal STVEM to the light-emitting driving circuit 150.

[0084] The gate driver 130 receives a scan start signal (such as STVG1 and STVG2) from the timing controller 110, and is coupled to all the self-luminous pixel circuits PX in the pixel array 160. The gate driver 130 divides a single frame period into a plurality of sub-frame periods based on the received scan start signal (such as STVG1 and STVG2), and turns on the self-luminous pixel circuits PX row by row in each of the sub-frame periods.

[0085] The source driver 140 receives the pixel voltage DATApx1 from the timing controller 110 and is coupled to all the self-luminous pixel circuits PX in the pixel array 160. The source driver 140 provides a plurality of pixel voltages Vsig corresponding to the self-luminous pixel circuits PX in each of the sub-frame periods, wherein the driving circuit CTDR of each of the self-luminous pixel circuits PX determines the driving current Idr flowing through the light-emitting diode DL1 based on the received pixel voltage Vsig. Further, each self-luminous pixel circuit PX writes the pixel voltage Vsig to the driving circuit CTDR at least twice in a single frame period, that is, once in each sub-frame period.

[0086] The light-emitting driving circuit 150 receives a light-emitting start signal STVEM to provide a plurality of light-emitting signals EM to these self-luminous pixel circuits PX to control the driving circuit CTDR to light up the light-emitting diode DL1 in the self-luminous pixel circuit PX, thereby determining a plurality of light-emitting times of these self-luminous pixel circuits PX, wherein the light-emitting signals EM have a plurality of pulses, and the pulses of the light-emitting signals EM are used to control the number of times the light-emitting diode DL1 of the self-luminous pixel circuit PX is lit during a single frame period.

[0087] According to the above, the timing controller 110 divides a single frame period into multiple sub-frame periods, so that each self-luminous pixel circuit PX is written once in each sub-frame period, so that the brightness lit / illuminated / provided by each self-luminous pixel circuit PX in the sub-frame period is independent of each other, whereby the self-luminous pixel circuit PX can only use a pulse amplitude modulation circuit architecture, but still has the effect of a pulse width modulation light emission duty cycle.

[0088] In the embodiment of the present invention, the light emitting diode DL1 includes a micro light emitting diode, but the embodiment of the present invention is not limited thereto.

[0089] In the embodiment of the present invention, the self-luminous pixel circuit PX adjusts the light-emitting duty cycle not by changing the duration of each light emission, but by changing the number of times the light-emitting diode DL1 of the self-luminous pixel circuit PX is lit during a single frame period (ie, the number of times the light is emitted).

[0090] In the embodiment of the present invention, the gate driver 130 may not be limited to providing the first scanning signal WS1, the second scanning signal WS2, the reset signal RS, the scanning compensation signal CS, and the voltage control signal VC to the self-luminous pixel circuit PX.

[0091] Figure 2A FIG. 1 is a schematic diagram of a driving waveform of a display device at a low gray scale according to an embodiment of the present invention. Figure 1 and Figure 2A In the present embodiment, a single frame period Frame1 is, for example, divided into two sub-frame periods FS11 and FS12, wherein the time length of the sub-frame period FS11 is much longer than the time length of the sub-frame period FS12 (that is, the time lengths of the sub-frame periods FS11 and FS12 are not exactly the same), for example, the number of pulses of the light-emitting signal EM during the sub-frame period FS11 and the number of pulses of the light-emitting signal EM during the sub-frame period FS12 are 9:2 (that is, the proportions of the multiple light-emitting times of the sub-frame periods FS11 and FS12 are not exactly the same), but the embodiments of the present invention are not limited thereto.

[0092] In this embodiment, it is assumed that the self-luminous pixel circuit PX provides low grayscale brightness. At this time, the pixel voltage Vsig used to write the self-luminous pixel circuit PX in the sub-picture period FS11 can correspond to the grayscale value L0 (i.e., 0 grayscale value), so that the driving current Idr of the self-luminous pixel circuit PX is 0 in the sub-picture period FS11, that is, the light-emitting diode DL1 does not emit light. Then, the pixel voltage Vsig written into the self-luminous pixel circuit PX in the sub-picture period FS12 can be greater than the grayscale value L0, so that the driving current Idr of the self-luminous pixel circuit PX is not 0 in the sub-picture period FS12, that is, the light-emitting diode DL1 emits light in the sub-picture period FS12.

[0093] Since the pulse number of the luminous signal EM in the sub-picture period FS12 is much smaller than the pulse number of the luminous signal EM in the sub-picture period FS11 , the luminous effect of the self-luminous pixel circuit PX in the sub-picture period FS12 is limited, thereby achieving the effect of providing low grayscale brightness.

[0094] In the embodiment of the present invention, in each of the sub-picture periods FS11 and FS12 of the single picture period Frame1, the plurality of light emitting pulses of each of the light emitting signals EM have the same pulse width. Furthermore, the pulse width of the light emitting pulse of each of the light emitting signals EM in the sub-picture period FS11 (corresponding to the first sub-picture period) is the same as the pulse width of the light emitting pulse in the sub-picture period FS12 (corresponding to the second sub-picture period).

[0095] Figure 2B Schematic diagram of driving waveform of a display device at high gray scale according to an embodiment of the present invention. Figure 1 and Figure 2B In the present embodiment, a single frame period Frame2 is, for example, divided into two sub-frame periods FS21 and FS22, wherein the time length of the sub-frame period FS21 is much longer than the time length of the sub-frame period FS22, for example, the number of pulses of the light-emitting signal EM during the sub-frame period FS21 and the number of pulses of the light-emitting signal EM during the sub-frame period FS22 are 9:2, but the embodiments of the present invention are not limited thereto.

[0096] In this embodiment, it is assumed that the self-luminous pixel circuit PX provides high grayscale brightness. At this time, the pixel voltages Vsig used to write the self-luminous pixel circuit PX in the sub-picture periods FS21 and FS22 can be different from each other and greater than (or much greater than) the grayscale value L0 (i.e., 0 grayscale value), so that the driving current Idr of the self-luminous pixel circuit PX is not 0 in the sub-picture periods FS21 and FS22, that is, the light-emitting diode DL1 emits light in the sub-picture periods FS21 and FS22. Therefore, the self-luminous pixel circuit PX can achieve the effect of providing high grayscale brightness.

[0097] Figure 3 FIG. 1 is a circuit diagram of a self-luminous pixel circuit of a display device according to an embodiment of the present invention. Figure 1 and Figure 3 In the present embodiment, the self-luminous pixel circuit PX is, for example, a self-luminous pixel circuit PXa, and each of the self-luminous pixel circuits PXa includes a light-emitting diode DL1, a light-emitting element driving circuit 310, a data programming circuit 320, a reset circuit 330, and a test circuit 340, wherein the driving circuit CTDR includes at least one of the light-emitting element driving circuit 310, the data programming circuit 320, the reset circuit 330, and the test circuit 340.

[0098] The light emitting diode DL1 has an anode and a cathode coupled to the system low voltage VSS. The light emitting element driving circuit 310 receives the system high voltage VDD, one of the plurality of light emitting signals EM, and the gate control voltage Vgt, and is coupled to the anode of the light emitting diode DL1 to provide a driving current Idr to the light emitting diode DL1. The data programming circuit 320 is coupled to the gate driver 130 to receive the first scanning signal WS1 and the second scanning signal WS2, coupled to the light emitting driving circuit 310, and receives one of the pixel voltages Vsig to provide the gate control voltage Vgt.

[0099] The reset circuit 330 receives the gate control voltage Vgt and the reset signal RS to reset the gate control voltage Vgt based on the reset signal RS. The test circuit 340 is coupled to the anode of the light emitting diode DL1 and receives the test signal Test to provide a test result voltage Vst based on the test signal Test.

[0100] In the present embodiment, the light-emitting driving circuit 310 includes a first transistor T1, a second transistor T2, and a third transistor T3, wherein the first transistor T1, the second transistor T2, and the third transistor T3 are, for example, P-type transistors. The first transistor T1 has a first end receiving a system high voltage VDD, a control end receiving one of the light-emitting signals EM, and a second end. The second transistor T2 has a first end coupled to the second end of the first transistor T1, a control end receiving a gate control voltage Vgt, and a second end. The third transistor T3 has a first end coupled to the second end of the second transistor T2, a control end receiving one of the light-emitting signals EM, and a second end providing a driving current Idr.

[0101] In the present embodiment, the data programming circuit 320 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a first capacitor C1 and a second capacitor C2, wherein the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are, for example, P-type transistors. The fourth transistor T4 has a first end coupled to the control end of the second transistor T2, a control end receiving the scanning compensation signal CS, and a second end coupled to the second end of the second transistor T2. The fifth transistor T5 has a first end receiving a reference voltage Vref, a control end receiving a voltage control signal VC, and a second end coupled to the first end of the second transistor T2. The sixth transistor T6 has a first end receiving one of the pixel voltages Vsig, a control end receiving the first scanning signal WS1, and a second end.

[0102] The seventh transistor T7 has a first end for receiving one of the pixel voltages Vsig, a control end for receiving the second scanning signal WS2, and a second end coupled to the second end of the sixth transistor T6. The first capacitor C1 is coupled between the second end of the sixth transistor T6 and the control end of the second transistor T2, and provides a gate control voltage Vgt to the control end of the second transistor. The second capacitor C2 is coupled between the second end of the fifth transistor T5 and the second end of the sixth transistor T6. The eighth transistor T8 has a first end coupled to the second end of the sixth transistor T6, a control end for receiving the scanning compensation signal CS, and a second end for receiving the initial voltage Vini. The gate control voltage Vgt reflects the received pixel voltage Vsig.

[0103] In the present embodiment, the reset circuit 330 includes a ninth transistor T9 and a tenth transistor T10, wherein the ninth transistor T9 and the tenth transistor T10 are, for example, P-type transistors. The ninth transistor T9 has a first end coupled to the second end of the sixth transistor T6, a control end receiving the reset signal RS, and a second end receiving the initial voltage Vini. The tenth transistor T10 has a first end coupled to the control end of the second transistor T2, a control end receiving the reset signal RS, and a second end receiving the initial voltage Vini.

[0104] In this embodiment, the test circuit includes an eleventh transistor T11, wherein the eleventh transistor T11 is, for example, a P-type transistor and has a first terminal coupled to the anode of the light emitting diode DL1, a control terminal receiving a test signal Test, and a second terminal providing a test result voltage Vst.

[0105] Figures 4A to 4C FIG. 1 is a schematic diagram of characteristic curves of forward voltages of a red light emitting diode, a green light emitting diode, and a blue light emitting diode of a self-luminous pixel circuit according to an embodiment of the present invention.

[0106] Figure 4D FIG. 1 is a schematic diagram of a current-voltage characteristic curve of a transistor in a self-luminous pixel circuit according to an embodiment of the present invention. Figure 1 , Figure 3 and Figures 4A to 4D In the present embodiment, the minimum driving current Idr for lighting up the light emitting diode DL1 of each of these self-luminous pixel circuits PX is based on the characteristic curve of the forward voltage of the light emitting diode DL1 and the current-voltage characteristic curve of the driving transistor (i.e., the second transistor T2) of each of these self-luminous pixel circuits PX.

[0107] in, Figure 4A The characteristic curve of the forward voltage of a red light emitting diode is shown below. Figure 4B The characteristic curve of the forward voltage of a green light emitting diode is shown in FIG. Figure 4C The characteristic curve of the forward voltage of a blue light-emitting diode is shown. As shown in the figure, "X" indicates the conversion point of the best efficiency of high grayscale brightness, "▲" indicates the conversion point of the best efficiency of middle grayscale brightness, and "O" indicates the conversion point of the best efficiency of low grayscale brightness. If the high grayscale brightness is 2000 nits (nit), the middle grayscale brightness can be 250 nits, and the low grayscale brightness can be 10 nits, but the embodiment of the present invention is not limited to this. In addition, in the schematic diagram of the current-voltage characteristic curve of the transistor, "O" indicates the operating point where the transistor is least sensitive to temperature, that is, the variation amplitude and variation range of the transistor at this operating point are small.

[0108] After finding the characteristic curve of the forward voltage of the light emitting diode, the minimum operating current of the light emitting diode (that is, the minimum driving current Idr) is determined according to the current-voltage characteristic curve of the transistor and the light emitting efficiency of the light emitting diode. Figures 4A to 4C As shown, if the lowest acceptable current of the red LED is 40uA, the lowest acceptable current of the green LED is 10uA.

[0109] Next, the shortest duty cycle of the shortest sub-picture period among the sub-picture periods is determined. For example, the shortest duty cycle can be defined as 1%. In addition, the red light-emitting diode, the green light-emitting diode, and the blue light-emitting diode can have different duty cycle combinations, that is, the scanning signal for writing data into the self-luminous pixel circuit PX of the red light-emitting diode, the green light-emitting diode, and the blue light-emitting diode is split.

[0110] Then, according to the circuit architecture of the self-luminous pixel circuit PX, the channel size of the transistor and the size of the system high voltage VDD are determined. For example, if the maximum required current in the shortest working cycle is 180 microamperes (μA), the channel ratio of the driving transistor is 40 / 4.5 micrometers (μm), and the system high voltage VDD is 11 volts (V).

[0111] Furthermore, the duty cycle of the maximum sub-picture period is determined according to the maximum brightness specification. For example, assuming the maximum brightness specification is 2000 nits, that is, the sum of the duty cycles of the maximum sub-picture period and the minimum sub-picture period is 10%, the duty cycle of the maximum sub-picture period is 9%.

[0112] Finally, the combination of the working cycles of the sub-frame periods determines the combination of the pixel voltage Vsig data of each brightness. For example, the combination of the pixel voltage Vsig data of the working cycles of the maximum sub-frame period and the minimum sub-frame period of the full grayscale is established, as shown in Table 1.

[0113] Table 1

[0114]

[0115]

[0116] Figure 5A FIG. 1 is a schematic diagram of scanning a pixel array of a display device according to an embodiment of the present invention. Figure 1 , Figure 3 and Figure 5A In the present embodiment, a single frame period Frame is defined by, for example, a pulse of a vertical synchronization signal Vsync, and scan start signals STVG1 and STVG2 form pulses in turn to distinguish sub-frame periods FS1 and FS2. When the scan start signal STVG1 forms a pulse, the self-luminous pixel circuits PX of the pixel array 160 are turned on row by row starting from the first row Row[1], as shown in the scan timing TDW1, to perform the first data writing of the self-luminous pixel circuits PX; and when the scan start signal STVG2 forms a pulse, the self-luminous pixel circuits PX of the pixel array 160 are turned on row by row starting from the first row Row[1], as shown in the scan timing TDW2, to perform the second data writing of the self-luminous pixel circuits PX.

[0117] Figure 5B FIG. 1 is a waveform diagram of a single horizontal scanning period of a pixel array of a display device according to an embodiment of the present invention. Figure 1 , Figure 3 , Figure 5A as well as Figure 5B In this embodiment, when the self-luminous pixel circuit PX of the nth column Row[n] performs the first data writing, the self-luminous pixel circuit PX of the 1st column Row[1] performs the second data writing, as shown in the horizontal scanning period H[n], where n is a positive integer greater than 0.

[0118] At this time, the first scanning signal WS1[1] received by the self-luminous pixel circuit PX of the first column Row[1] remains in a disabled state (for example, a high voltage VH), and the second scanning signal WS2[1] received by the self-luminous pixel circuit PX of the first column Row[1] can be switched to an enabled state (for example, a low voltage VL), so that the self-luminous pixel circuit PX of the first column Row[1] can write data; and, the first scanning signal WS1[n] received by the self-luminous pixel circuit PX of the nth column Row[n] can be switched to an enabled state, and the second scanning signal WS2[n] received by the self-luminous pixel circuit PX of the nth column Row[n] remains in a disabled state, so that the self-luminous pixel circuit PX of the nth column Row[n] can write data.

[0119] In the present embodiment, the time when the first scanning signal WS1[n] switches to the enabled state is different from the time when the second scanning signal WS2[1] switches to the enabled state (i.e., they do not overlap in time), so that the first data writing and the second data writing actions do not interfere with each other, and the time length and sequence of the sub-screen periods FS1 and FS2 are not restricted, i.e., they can be allocated more freely.

[0120] Figures 6 to 11 Schematic diagram of driving waveforms of a display device according to an embodiment of the present invention. Figure 1 , Figure 2A , Figure 2B as well as Figure 6 In this embodiment, a single frame period Frame3 is divided into a plurality of sub-frame periods (such as FS31, FS32, FS33, FS34, etc.), and it is assumed that the pulse widths of the pulses of the luminous signal EM are the same. The time length of the second sub-frame period FS32 is much longer than the time lengths of the other sub-frame periods (such as FS31, FS33, FS34, etc.), that is, the number of pulses of the luminous signal EM in the second sub-frame period FS32 is much larger than the number of pulses of the luminous signal EM in the other sub-frame periods (such as FS31, FS33, FS34, etc.).

[0121] Please refer to Figure 1 , Figure 2A , Figure 2B as well as Figure 7 In this embodiment, a single frame period Frame4 is divided into a plurality of sub-frame periods (such as FS41, FS42, FS43, FS44, etc.), and it is assumed that the pulse widths of the pulses of the luminous signal EM are the same. The time length of the first sub-frame period FS41 is much longer than the time lengths of the other sub-frame periods (such as FS42, FS43, FS44, etc.), that is, the number of pulses of the luminous signal EM in the first sub-frame period FS41 is much larger than the number of pulses of the luminous signal EM in the other sub-frame periods (such as FS42, FS43, FS44, etc.).

[0122] Please refer to Figure 1 , Figure 2A , Figure 2B as well as Figure 8In this embodiment, a single frame period Frame5 is divided into a plurality of sub-frame periods (such as FS51, FS52 to FS5(m-1), FS5m, FS5(m+1), FS5(m+2), etc.), and it is assumed that the pulse widths of the pulses of the luminous signal EM are the same, where m is a positive integer greater than 0. As shown in the figure, the time length of the m-th sub-frame period FS5m is much longer than the time lengths of other sub-frame periods (such as FS51, FS52 to FS5(m-1), FS5(m+1), FS5(m+2), etc.), that is, the number of pulses of the luminous signal EM in the m-th sub-frame period FS5m is much larger than the number of pulses of the luminous signal EM in other sub-frame periods (such as FS51, FS52 to FS5(m-1), FS5(m+1), FS5(m+2), etc.).

[0123] Please refer to Figure 1 , Figure 2A , Figure 2B as well as Fig. 9 In this embodiment, a single frame period Frame6 is, for example, divided into a plurality of sub-frame periods (such as FS61, FS62, FS63-FS6m, FS6(m+1), FS6(m+2), etc.), and it is assumed that the pulse widths of the pulses of the luminous signal EM are the same, where m is a positive integer greater than 0. As shown in the figure, the time length of the second sub-frame period FS62 is much longer than the time lengths of the other sub-frame periods (such as FS61, FS63-FS6m, FS6(m+1), FS6(m+2), etc.), that is, the number of pulses of the luminous signal EM in the second sub-frame period FS62 is much larger than the number of pulses of the luminous signal EM in the other sub-frame periods (such as FS61, FS63-FS6m, FS6(m+1), FS6(m+2), etc.).

[0124] Please refer to Figure 1 , Figure 2A , Figure 2B as well as Fig.10 In this embodiment, a single frame period Frame7 is divided into two sub-frame periods FS71 and FS72, wherein the sub-frame periods FS71 and FS72 are single-shot light emission, that is, the light emission signal EM forms only a single pulse in the sub-frame periods FS71 and FS72. Here, the time length of the second sub-frame period FS72 is much longer than the time length of the first sub-frame period FS71, and the pulse width W2 of the light emission signal EM in the second sub-frame period FS72 is much longer than the pulse width W1 of the light emission signal EM in the first sub-frame period FS71.

[0125] Please refer to Figure 1 , Figure 2A , Figure 2B as well as Fig.11In this embodiment, a single frame period Frame8 is divided into two sub-frame periods FS81 and FS82, wherein the first sub-frame period FS81 is a single light emission, and the second sub-frame period FS82 is multiple light emission (e.g., two times), that is, the light emission signal EM forms only a single pulse in the first sub-frame period FS82, and the light emission signal EM forms at least two pulses in the second sub-frame period FS82. Here, the time length of the second sub-frame period FS82 is much longer than the time length of the first sub-frame period FS81, and the pulse width W4 of each pulse of the light emission signal EM in the second sub-frame period FS82 is greater than the pulse width W3 of the light emission signal EM in the first sub-frame period FS81.

[0126] in accordance with Fig.10 and Fig.11 In an embodiment, in a single frame period (such as Frame7 and Frame8), the pulse width of the light-emitting pulse of each of these light-emitting signals EM in one of the sub-frame periods (such as FS71, FS72, FS81, FS82) (corresponding to the third sub-frame period) may be different from the pulse width of the light-emitting pulse in another different sub-frame period (such as FS71, FS72, FS81, FS82) (corresponding to the fourth sub-frame period).

[0127] Fig.12 FIG. 1 is a system diagram of a pixel driving method for a display device according to an embodiment of the present invention. Fig.12 In this embodiment, the pixel driving method includes the following steps. In step S110, a single frame period is divided into a plurality of sub-frame periods by a timing controller. In step S120, a plurality of self-luminous pixel circuits are turned on row by row in each of the sub-frame periods by a gate driver, wherein each of the self-luminous pixel circuits has a light-emitting element.

[0128] In step S130, a plurality of pixel voltages are provided to the self-luminous pixel circuit corresponding to each of the display data in the sub-picture period via the source driver, wherein each of the light-emitting elements of these self-luminous pixel circuits determines the driving current flowing through the light-emitting element based on the received pixel voltage. In step S140, a plurality of light-emitting signals are provided to the self-luminous pixel circuit via the light-emitting driving circuit to determine the plurality of light-emitting times of these self-luminous pixel circuits. The order of steps S110, S120, S130 and S140 is for illustration only, and the embodiments of the present invention are not limited thereto; and the details of steps S110, S120, S130 and S140 can be referred to. Figures 1 to 11 The embodiments are shown in the embodiment, which will not be repeated here.

[0129] In summary, in the display device and pixel driving method thereof of the embodiments of the present invention, the timing controller divides a single frame period into multiple sub-frame periods, so that each self-luminous pixel circuit performs data writing once in each sub-frame period, that is, the brightness lit / illuminated / provided by each self-luminous pixel circuit in the sub-frame period is independent of each other, whereby the self-luminous pixel circuit can only use a pulse amplitude modulation circuit architecture, but still has the effect of a pulse width modulation light emission duty cycle.

[0130] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the concept and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the claims.

Claims

1. A display device, comprising: A pixel array having a plurality of self-luminous pixel circuits arranged in an array, wherein each of the self-luminous pixel circuits has a light-emitting element; A timing controller receives display data to provide a pixel voltage data, at least two scanning start signals, and a light-emitting start signal in a single frame period; a gate driver receiving the at least two scan start signals and coupled to the self-luminous pixel circuits to divide the single frame period into a plurality of sub-frame periods based on the at least two scan start signals and to turn on the self-luminous pixel circuits row by row in each of the sub-frame periods; a source driver receiving the pixel voltage data to provide a plurality of pixel voltages corresponding to the self-luminous pixel circuits during each of the sub-frame periods, wherein each of the self-luminous pixel circuits determines a driving current flowing through the light-emitting element based on the received pixel voltage; as well as A light-emitting driving circuit receives the light-emitting start signal to provide a plurality of light-emitting signals to the self-luminous pixel circuits to determine a plurality of light-emitting times of the self-luminous pixel circuits. 2 . The display device as claimed in claim 1 , wherein in the single frame period, the time lengths of the sub-frame periods are not completely the same. 3 . The display device as claimed in claim 1 , wherein in the single frame period, the light emitting time proportions of the sub-frame periods are not completely the same. 4 . The display device as claimed in claim 1 , wherein in each of the sub-frame periods in the single frame period, a plurality of light emitting pulses of each of the light emitting signals have the same pulse width.

5. A display device as described in claim 4, wherein in the single frame period, the pulse width of the light-emitting pulses of each of the light-emitting signals in a first sub-frame period among the sub-frame periods is the same as the pulse width of the light-emitting pulses in a second sub-frame period among the sub-frame periods that is different from the first sub-frame period.

6. A display device as described in claim 4, wherein during the single frame period, the pulse width of the light emitting pulses of each of the light emitting signals in a third sub-frame period among the sub-frame periods is different from the pulse width of the light emitting pulses in a fourth sub-frame period among the sub-frame periods that is different from the first sub-frame period.

7. The display device as claimed in claim 1, wherein each of the self-luminous pixel circuits comprises: The light emitting element has an anode and a cathode coupled to a system low voltage; a light emitting element driving circuit receiving a system high voltage, one of the light emitting signals, and a gate control voltage, and coupled to the anode of the light emitting element to provide the driving current to the light emitting element; as well as a data programming circuit coupled to the gate driver to receive a first scanning signal and a second scanning signal, coupled to the light-emitting driving circuit, and receiving one of the pixel voltages to provide the gate control voltage; and A reset circuit receives the gate control voltage and a reset signal to reset the gate control voltage based on the reset signal.

8. The display device as claimed in claim 7, wherein the light-emitting driving circuit comprises: a first transistor having a first terminal receiving the system high voltage, a control terminal receiving one of the light emitting signals, and a second terminal; a second transistor having a first terminal coupled to the second terminal of the first transistor, a control terminal receiving the gate control voltage, and a second terminal; and A third transistor has a first end coupled to the second end of the second transistor, a control end receiving one of the light emitting signals, and a second end providing the driving current.

9. The display device as claimed in claim 8, wherein the data programming circuit comprises: a fourth transistor having a first end coupled to the control end of the second transistor, a control end receiving a scan compensation signal, and a second end coupled to the second end of the second transistor; a fifth transistor having a first terminal receiving a reference voltage, a control terminal receiving a voltage control signal, and a second terminal coupled to the first terminal of the second transistor; a sixth transistor having a first terminal receiving one of the pixel voltages, a control terminal receiving the first scan signal, and a second terminal; a seventh transistor having a first end receiving one of the pixel voltages, a control end receiving the second scan signal, and a second end coupled to the second end of the sixth transistor; a first capacitor coupled between the second terminal of the sixth transistor and the control terminal of the second transistor to provide the gate control voltage; a second capacitor coupled between the second terminal of the fifth transistor and the second terminal of the sixth transistor; and An eighth transistor has a first end coupled to the second end of the sixth transistor, a control end receiving the scan compensation signal, and a second end receiving an initial voltage.

10. The display device as claimed in claim 9, wherein the reset circuit comprises: a ninth transistor having a first end coupled to the second end of the sixth transistor, a control end receiving the reset signal, and a second end receiving the initial voltage; as well as A tenth transistor has a first end coupled to the control end of the second transistor, a control end receiving the reset signal, and a second end receiving the initial voltage.

11. The display device as claimed in claim 1, wherein the light emitting element comprises a micro light emitting diode.

12. A pixel driving method for a display device, comprising: The single frame period is divided into a plurality of sub-frame periods by a timing controller; Turning on a plurality of self-luminous pixel circuits row by row during each of the sub-picture periods via a gate driver, wherein each of the self-luminous pixel circuits has a light-emitting element; Providing a plurality of pixel voltages corresponding to the self-luminous pixel circuits in each of the sub-frame periods based on display data via a source driver, wherein each of the light-emitting elements of the self-luminous pixel circuits determines a driving current flowing through the light-emitting element based on the received pixel voltage; and A plurality of light-emitting signals are provided to the self-luminous pixel circuits via a light-emitting driving circuit to determine a plurality of light-emitting times of the self-luminous pixel circuits. 13 . The pixel driving method as claimed in claim 12 , wherein in the single frame period, the time lengths of the sub-frame periods are not completely the same. 14 . The pixel driving method as claimed in claim 12 , wherein in the single frame period, the light emitting time proportions of the sub-frame periods are not completely the same. 15 . The pixel driving method as claimed in claim 12 , wherein in each of the sub-frame periods in the single frame period, a plurality of light emitting pulses of each of the light emitting signals have the same pulse width.

16. The pixel driving method as described in claim 15, wherein in the single frame period, the pulse width of the light emitting pulses of each of the light emitting signals in a first sub-frame period among the sub-frame periods is the same as the pulse width of the light emitting pulses in a second sub-frame period among the sub-frame periods which is different from the first sub-frame period.

17. A pixel driving method as described in claim 15, wherein in the single frame period, the pulse width of the light emitting pulses of each of the light emitting signals in a third sub-frame period among the sub-frame periods is different from the pulse width of the light emitting pulses in a fourth sub-frame period among the sub-frame periods that is different from the first sub-frame period.

18. The pixel driving method as claimed in claim 12, wherein the light emitting element comprises a micro light emitting diode.

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