Memory, memory system and operation method of memory

Abstract

The embodiment of the invention provides a memory, a memory system and an operation method of the memory. The memory comprises a plurality of storage planes and a peripheral circuit coupled to the storage planes, the peripheral circuit comprises a plurality of charge pumps, and each charge pump is provided with a clock signal end, an input end and an output end; the output end of each charge pump is coupled to one of the plurality of storage planes; the charge pump is configured to boost an input voltage of the input end according to a clock signal received by the clock signal end and then output the input voltage to the output end; wherein clock signals received by the clock signal ends of the plurality of charge pumps are different.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a memory, a storage system, and a memory operation method. Background Art

[0002] A three-dimensional memory generally includes a stacked memory array and a peripheral circuit, wherein the peripheral circuit can apply a programming voltage or a reading voltage to the memory array to realize reading and writing of stored information.

[0003] The peripheral circuit usually includes a charge pump, which can be used to increase or decrease the input power supply voltage or even generate a negative voltage by controlling the charging or discharging of the internal capacitor. Summary of the invention

[0004] In view of this, embodiments of the present disclosure provide a memory, a storage system, and a method for operating the memory.

[0005] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a memory, the memory comprising: a plurality of memory planes and a peripheral circuit coupled to the memory planes, the peripheral circuit comprising:

[0007] A plurality of charge pumps, each having a clock signal terminal, an input terminal and an output terminal; the output terminal of each of the charge pumps is coupled to one of the plurality of storage planes; the charge pump is configured to boost the input voltage of the input terminal according to the clock signal received by the clock signal terminal, and then output the boost voltage to the output terminal; wherein the clock signals received by the clock signal terminals of the plurality of charge pumps are different.

[0008] In some embodiments, there is a preset delay time between the clock signals received by the clock signal terminals of the plurality of charge pumps.

[0009] In some embodiments, the peripheral circuit further comprises: a clock signal generating circuit, the clock signal generating circuit comprising a clock generator and a clock processing circuit, an input end of the clock processing circuit being coupled to the clock generator;

[0010] The clock generator is configured to generate a first clock signal;

[0011] The clock processing circuit is configured to generate a second clock signal different from the first clock signal based on the first clock signal.

[0012] In some embodiments, the clock processing circuit is specifically configured to delay the first clock signal by a preset delay time to generate the second clock signal.

[0013] In some embodiments, the preset delay time is smaller than a clock period of the first clock signal.

[0014] In some embodiments, the preset delay time is half of a clock period of the first clock signal.

[0015] In some embodiments, the peripheral circuit also includes: a multiplexer, which is coupled between the multiple charge pumps and the multiple storage planes; wherein, in an asynchronous multi-plane independent read operation, each of the charge pumps is coupled to one of the multiple storage planes through the multiplexer; in a normal read operation, the multiple charge pumps are connected in parallel through the multiplexer and the output ends of the multiple charge pumps are commonly coupled to an output node.

[0016] In some embodiments, the plurality of charge pumps include:

[0017] a first charge pump group and a second charge pump group, the first charge pump group comprising at least one first charge pump; the second charge pump group comprising at least one second charge pump; wherein the number of the first charge pumps in the first charge pump group is the same as the number of the second charge pumps in the second charge pump group;

[0018] The clock signal generating circuit comprises a first output terminal and a second output terminal;

[0019] The clock signal generating circuit is configured to provide a clock signal to a first clock signal terminal of the first charge pump via the first output terminal;

[0020] The clock signal generating circuit is configured to provide a clock signal to a second clock signal terminal of the second charge pump via the second output terminal.

[0021] In some embodiments, the first charge pump group is configured to, during the ramp phase, boost an input voltage received at a first input terminal of the first charge pump and output the boosted voltage to an output node according to a first clock signal received at the first clock signal terminal;

[0022] The second charge pump group is configured to, during a ramping phase, boost an input voltage received at a second input terminal of the second charge pump according to a second clock signal received at the second clock signal terminal, and then output the boosted input voltage to the output node.

[0023] In some embodiments, any of the first charge pumps in the first charge pump group is configured to process an input voltage received at the first input terminal of the first charge pump and output the processed input voltage to the output node according to a third clock signal received at the first clock signal terminal during a stable phase;

[0024] Any second charge pump in the second charge pump group is configured to process an input voltage received at a second input terminal of the second charge pump according to a fourth clock signal received at the second clock signal terminal during a stable phase, and then output the processed input voltage to the output node.

[0025] In some embodiments, the clock signal generating circuit further includes: a first selection switch and a first clock divider; an input end of the first selection switch is coupled to the clock generator, an output end of the first selection switch is coupled to a first output end of the clock signal generating circuit or the first clock divider, and an output end of the first clock divider is coupled to a first output end of the clock signal generating circuit;

[0026] The first selection switch is configured such that during a ramping phase, an output terminal of the first selection switch is coupled to a first output terminal of the clock signal generating circuit to transmit the first clock signal generated by the clock generator to the first charge pump; and during a stabilization phase, an output terminal of the first selection switch is coupled to the first clock divider to transmit the first clock signal generated by the clock generator to the first clock divider;

[0027] The first clock divider is configured to perform a frequency division process on the first clock signal during the stable phase to generate the third clock signal, and transmit the third clock signal to the first charge pump.

[0028] In some embodiments, the clock signal generating circuit further includes: a second selection switch and a second clock divider; the input end of the second selection switch is coupled to the clock processing circuit, the output end of the second selection switch is coupled to the second output end of the clock signal generating circuit or the second clock divider, and the output end of the second clock divider is coupled to the second output end of the clock signal generating circuit;

[0029] The second selection switch is configured such that during a ramp phase, an output terminal of the second selection switch is coupled to a second output terminal of the clock signal generating circuit, so as to transmit the second clock signal generated by the clock processing circuit to the second charge pump; and during a stable phase, an output terminal of the second selection switch is coupled to the second clock divider, so as to transmit the second clock signal generated by the clock processing circuit to the second clock divider;

[0030] The second clock divider is configured to perform a frequency division process on the second clock signal during the stable phase to generate the fourth clock signal, and transmit the fourth clock signal to the second charge pump.

[0031] In some embodiments, the clock period of the first clock signal and the clock period of the second clock signal are both the first period;

[0032] The clock period of the third clock signal is the same as the clock period of the fourth clock signal, which is the second period; the second period is twice the first period.

[0033] In some embodiments, the clock processing circuit includes: an inverting circuit.

[0034] In some embodiments, the charge pump boosts the input voltage at the input end and then outputs the output voltage to the output end; wherein the absolute value of the output voltage is greater than the absolute value of the input voltage.

[0035] In a second aspect, an embodiment of the present disclosure provides a memory system, the memory system comprising:

[0036] The memory as described in the above technical solution; and

[0037] A controller is coupled to the memory and configured to control the memory.

[0038] In a third aspect, an embodiment of the present disclosure provides an operating method of a memory, wherein the memory comprises: a plurality of memory planes and a peripheral circuit coupled to the memory planes, wherein the peripheral circuit comprises: a plurality of charge pumps, wherein the charge pumps have a clock signal terminal, an input terminal, and an output terminal; and the output terminal of each of the charge pumps is coupled to one of the memory planes in the plurality of memory planes; and the operating method comprises:

[0039] The clock signal terminals of the plurality of charge pumps receive a clock signal;

[0040] In response to the clock signal received by the clock signal end, the input voltage of the input end is boosted and then output to the output end; wherein the clock signals received by the clock signal ends of the multiple charge pumps are different.

[0041] In some embodiments, there is a preset delay time between the clock signals received by the clock signal terminals of the plurality of charge pumps.

[0042] In some embodiments, the peripheral circuit further comprises: a clock signal generating circuit, the clock signal generating circuit comprising a clock generator and a clock processing circuit, an input end of the clock processing circuit being coupled to the clock generator;

[0043] The clock generator generates a first clock signal;

[0044] The clock processing circuit generates a second clock signal different from the first clock signal based on the first clock signal.

[0045] In some embodiments, the clock processing circuit generates a second clock signal different from the first clock signal according to the first clock signal, including:

[0046] The clock processing circuit delays the first clock signal by a preset delay time to generate the second clock signal.

[0047] In some embodiments, the preset delay time is smaller than a clock period of the first clock signal.

[0048] In some embodiments, the preset delay time is half of a clock period of the first clock signal.

[0049] In some embodiments, the peripheral circuit further comprises: a multiplexer coupled between the plurality of charge pumps and the plurality of memory planes;

[0050] In an asynchronous multi-plane independent read operation, each of the charge pumps outputs the boosted voltage to one of the multiple storage planes through the multiplexer; in a normal read operation, the multiple charge pumps are connected in parallel through the multiplexer and the multiple charge pumps output the boosted voltage together to an output node.

[0051] In some embodiments, the plurality of charge pumps include:

[0052] a first charge pump group and a second charge pump group, the first charge pump group comprising at least one first charge pump; the second charge pump group comprising at least one second charge pump; wherein the number of the first charge pumps in the first charge pump group is the same as the number of the second charge pumps in the second charge pump group;

[0053] The step of boosting the input voltage of the input terminal and outputting the voltage to the output terminal in response to the clock signal received by the clock signal terminal comprises:

[0054] During the ramp phase, the first charge pump group, in response to the first clock signal, boosts the input voltage received at the first input terminal of the first charge pump and outputs the boosted voltage to an output node;

[0055] During the ramp phase, the second charge pump group responds to the second clock signal to boost an input voltage received at a second input terminal of the second charge pump and output the boosted voltage to the output node.

[0056] In some embodiments, the plurality of charge pumps step up the input voltage of the input terminal and output the voltage to the output terminal in response to the clock signal received by the clock signal terminal, and further include:

[0057] During a stable phase, any of the first charge pumps in the first charge pump group processes an input voltage received at the first input terminal and outputs the processed input voltage to the output node in response to a third clock signal received at the first clock signal terminal;

[0058] During a stable phase, any second charge pump in the second charge pump group processes an input voltage received at the second input terminal in response to a fourth clock signal received at the second clock signal terminal, and then outputs the processed input voltage to the output node.

[0059] In some embodiments, the method further includes: during the stabilization phase, dividing the first clock signal to generate the third clock signal; and dividing the second clock signal to generate the fourth clock signal.

[0060] In some embodiments, the clock period of the first clock signal and the clock period of the second clock signal are both the first period;

[0061] The clock period of the third clock signal is the same as the clock period of the fourth clock signal, which is the second period; the second period is twice the first period.

[0062] In some embodiments, the step of boosting the input voltage at the input end and outputting it to the output end includes: the charge pump boosting the input voltage so that the absolute value of the boosted voltage is greater than the absolute value of the input voltage.

[0063] The embodiments of the present disclosure provide a memory, a memory system, and a memory operation method. The memory includes: a plurality of memory planes and a peripheral circuit coupled to the memory planes, the peripheral circuit includes: a plurality of charge pumps, the charge pumps having a clock signal terminal, an input terminal, and an output terminal; the output terminal of each of the charge pumps is coupled to one of the memory planes; the charge pump is configured to boost the input voltage of the input terminal and output it to the output terminal according to the clock signal received by the clock signal terminal; wherein the clock signals received by the clock signal terminals of the plurality of charge pumps are different. Compared with the clock signal terminals of the plurality of charge pumps receiving the same clock signal, in the embodiments of the present disclosure, the clock signal terminals of the plurality of charge pumps receive different clock signals, so that the times at which the plurality of charge pumps provide charge to the output terminal are different, thereby effectively reducing the voltage ripple and improving the stability of the read voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1 A diagram showing the connection status of a charge pump and a storage plane in an asynchronous multi-plane independent read operation and a normal read operation in one embodiment;

[0065] Figure 2 A waveform diagram of a clock signal received by a clock signal terminal of a charge pump and a read voltage outputted correspondingly by an output terminal in an embodiment;

[0066] Figure 3 An internal block diagram of a memory provided by an embodiment of the present disclosure;

[0067] Figure 4 A connection state diagram of the charge pump and the storage plane in an asynchronous multi-plane independent read operation and a normal read operation in an embodiment of the present disclosure;

[0068] Figure 5 A partial internal block diagram of a peripheral circuit provided by an embodiment of the present disclosure;

[0069] Figure 6 A waveform diagram of clock signals received by multiple charge pump clock signal terminals and a read voltage outputted corresponding to an output node in an embodiment of the present disclosure;

[0070] Figure 7 A circuit diagram of a charge pump provided in an embodiment of the present disclosure;

[0071] Figure 8 A block diagram of a storage system provided in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0072] The following will be combined with the embodiments of the present disclosure and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0073] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0074] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0075] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0076] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0077] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0078] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0079] As an indispensable part of the 3D memory circuit, the negative charge pump can boost the input lower power supply voltage and output a higher read voltage. However, as the number of stacked layers of the 3D memory increases, a higher read voltage needs to be applied when performing a read operation.

[0080] In one embodiment, for a three-dimensional memory with multiple storage planes, in order to avoid interference to the read voltage caused by operations between different storage planes during asynchronous multi-plane independent read (AMPI read) operations, the memory usually needs to use the same number of negative pressure charge pump basic units as the number of storage planes, so that each negative pressure charge pump basic unit provides a negative power supply for the read voltage of the corresponding storage plane during the asynchronous multi-plane independent read operation. In a normal read operation, in order to increase the ramp speed of the negative voltage, all charge pump basic units are usually turned on in the ramp phase (AC phase). When the negative voltage reaches a certain value, such as 98% of the target value, it enters a stable phase (DC phase). At this time, in order to reduce power consumption, only one charge pump is turned on and a frequency reduction operation is performed to provide a negative power supply for the read voltage of all storage planes.

[0081] refer to Figure 1 , Figure 1 FIG. 1 is a connection state diagram of a charge pump and a storage plane in an asynchronous multi-plane independent read operation and a normal read operation in an embodiment.

[0082] like Figure 1As shown, the peripheral circuit includes six negative voltage charge pump basic units, namely vneg_pl0, vneg_pl1, vneg_pl2, vneg_pl3, vneg_pl4 and vneg_pl5. The six negative voltage charge pump basic units correspond to the six storage planes load_pl0, load_pl1, load_pl2, load_pl3, load_pl4 and load_pl5 respectively. During the asynchronous multi-plane independent read operation, each negative voltage charge pump basic unit provides a negative power supply for the read voltage of a corresponding storage plane. For example, vneg_pl0 provides a negative power supply for the read voltage of load_pl0, and vneg_pl1 provides a negative power supply for the read voltage of load_pl1. In the AC stage, the six negative voltage charge pumps are turned on to provide a negative power supply for the read voltage of each storage plane in the six storage planes. In the DC stage, a negative voltage charge pump such as vneg_pl0 is turned on to provide a negative power supply for the read voltage of each storage plane in the six storage planes. At this time, the load current of the negative voltage charge pump is the largest.

[0083] refer to Figure 2 , Figure 2 1 is a waveform diagram of a clock signal received by a clock signal terminal of a charge pump and a read voltage outputted correspondingly by an output terminal in an embodiment.

[0084] In one embodiment, if Figure 2 As shown, in the AC stage, the negative voltage VNEG provided by the negative voltage charge pump for the read voltage of the storage plane gradually decreases. At this time, the clock signal clk connected to the clock signal end of the negative voltage charge pump is the initial clock signal clk_in0. For example, the frequency of the initial clock signal clk_in0 is 50MHz. In the DC stage, the negative power supply provided by the negative voltage charge pump for the read voltage of the storage plane tends to be stable. At this time, in order to reduce the power consumption after the negative voltage is stabilized, the initial clock signal clk_in0 connected to the clock signal end of the negative voltage charge pump is frequency-reduced. For example, the frequency of the clock signal clk_in1 after frequency reduction is 25MHz.

[0085] As the number of stacked layers increases, the voltage output by the negative charge pump becomes smaller and smaller, which will cause the ripple to increase. In three-dimensional memory, the accuracy and stability of the read voltage are very high. Since the ripple of the negative power supply voltage provided by the negative charge pump will affect the stability of the read voltage, the voltage ripple needs to be kept within a small range. It is known that the ripple of the charge pump is related to three parameters, as shown in the following formula:

[0086] V ripple ∝I load ÷(f clk ×C load )

[0087] The ripple of the charge pump is related to the load current (I load ) is proportional to the clock frequency (f clk ) and load end capacitance (C load ) is inversely proportional to the size of the charge pump. Therefore, in order to reduce the ripple of the charge pump, you can usually reduce the load current, increase the operating frequency or increase the load capacitance. However, in a given design, the total size of the load current cannot be adjusted, and increasing the frequency will increase the power consumption, while increasing the load capacitance will increase the area and reduce the ramp speed.

[0088] In a three-dimensional memory, as the number of stacked layers increases, the range of negative voltages required for the read voltage becomes larger, and a negative voltage charge pump is required to provide a more negative voltage, which will increase the area and increase the cost. In addition, in one embodiment, a linear regulator circuit can be connected to the output end of the negative voltage charge pump to provide a stable negative power supply through the linear regulator circuit, and the linear regulator circuit will also consume a certain voltage margin and circuit area, thereby increasing the cost.

[0089] In order to reduce the circuit area and reduce costs, the solution of removing the linear regulator circuit can be adopted. However, after removing the linear regulator circuit, the ripple of the voltage directly provided by the negative charge pump is large. And as the number of stacked layers increases, the voltage value output by the negative charge pump becomes smaller and smaller, which will also cause the ripple to become larger, thereby affecting the stability of the read voltage, making it difficult for the negative power supply provided by the negative charge pump to meet the design requirements. If you want to reduce the ripple while reducing the circuit area, you can increase the operating frequency of the negative charge pump while removing the linear regulator circuit. However, the increase in frequency will cause a decrease in current efficiency and an increase in power consumption.

[0090] Continue to refer Figure 2 In the actual simulation, if the linear regulator circuit connected to the output of the negative voltage charge pump is removed in order to save circuit area, the ripple of the output voltage of the charge pump exceeds the design requirement.

[0091] Therefore, reducing the circuit area to reduce costs while ensuring that the output voltage ripple of the negative charge pump meets the design requirements has become a common concern in the industry.

[0092] An embodiment of the present disclosure provides a memory, the memory comprising: a plurality of memory planes and a peripheral circuit coupled to the memory planes, the peripheral circuit comprising:

[0093] Multiple charge pumps, each charge pump having a clock signal terminal, an input terminal and an output terminal; the output terminal of each charge pump is coupled to a storage plane among multiple storage planes; the charge pump is configured to boost the input voltage of the input terminal according to the clock signal received by the clock signal terminal and then output it to the output terminal; wherein the clock signals received by the clock signal terminals of the multiple charge pumps are different.

[0094] refer to Figure 3 and Figure 4 , Figure 3 An internal block diagram of a memory provided in an embodiment of the present disclosure. Figure 4 1 is a connection state diagram between the charge pump and the storage plane in an asynchronous multi-plane independent read operation and a normal read operation in an embodiment of the present disclosure.

[0095] like Figure 3 As shown, the memory 300 includes a peripheral circuit 310 and a memory cell array 320 coupled to the peripheral circuit 310, the memory cell array includes a plurality of memory chips, and each of the plurality of memory chips includes a plurality of memory planes. The peripheral circuit 310 includes a charge pump circuit 311, the charge pump circuit 311 includes a plurality of charge pumps 312 and a clock signal generating circuit 313, and the clock signal generating circuit 313 is used to provide different clock signals for the clock signal terminals of the plurality of charge pumps 312. In some embodiments, as Figure 4 As shown, the memory includes six storage planes and peripheral circuits coupled to the six storage planes, wherein the peripheral circuit includes six charge pumps. The six charge pumps are vneg_pl0, vneg_pl1, vneg_pl2, vneg_pl3, vneg_pl4 and vneg_pl5, and the six storage planes are load_pl0, load_pl1, load_pl2, load_pl3, load_pl4 and load_pl5. The charge pump includes a clock signal terminal ( Figure 4 Not shown), input terminal ( Figure 4 The charge pump has a plurality of charge pumps, each of which ...

[0096] In the embodiment of the present disclosure, the peripheral circuit may further include a page buffer 314, a row decoder 315, a control logic circuit 316 and an I / O circuit 317. The peripheral circuit 310 is connected to the memory cell array 320 via a word line (WL).

[0097] The control logic circuit 316 is configured to receive a command (CMD) and an address (ADDR), and based on the command and the address, provide a control signal to the row decoder 315 and the charge pump circuit 311. Under the control of the control logic circuit 316, the charge pump circuit 311 generates a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, and a verification voltage, etc.) to be loaded into the memory cell array.

[0098] The page buffer 314 is coupled to the bit lines (BL) of the memory cell array 320, and is used to read data from the memory cell array 320 under the control of the control logic circuit 316. In one embodiment, the page buffer 314 can store data to be programmed into the memory cell array 320. In another embodiment, the page buffer 314 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell connected to the selected word line. The row decoder 315 is connected to the source selection line, the word line, and the ground selection line of the memory cell array 320. The row decoder 315 can be configured to be controlled by the control logic circuit 316, and select or deselect one or more word lines of the memory cell array 320, and drive the word line using the word line voltage generated from the charge pump circuit 311.

[0099] The I / O circuit 317 is coupled to the page buffer 314 via a data line, and is configured to receive data from an external circuit of the memory 300 and provide the received data to the memory cell array 320 via the page buffer 314 .

[0100] In the embodiment of the present disclosure, the peripheral circuit also includes: a multiplexer (MUX), which is coupled between multiple charge pumps and multiple storage planes; wherein, in an asynchronous multi-plane independent read operation, each charge pump is coupled to one storage plane among the multiple storage planes through the multiplexer; in a normal read operation, the multiple charge pumps are connected in parallel through the multiplexer and the output ends of the multiple charge pumps are commonly coupled to an output node.

[0101] Continue to refer Figure 4A multiplexer 400 is coupled between the multiple charge pumps and the multiple storage planes. The multiplexer 400 is coupled between the multiple charge pumps and the multiple storage planes. The multiplexer 400 includes multiple gate switches 401, and each gate switch 401 is coupled between the output terminals of two adjacent charge pumps. The multiplexer 400 includes multiple input terminals and multiple output terminals, each input terminal is coupled to a charge pump, each output terminal is coupled to a storage plane, and both ends of each gate switch 401 are respectively connected to an input terminal of the multiplexer 400 and an output terminal of the multiplexer 400. For example, a gate switch 401 of the multiplexer 400 is coupled between the output terminals of vneg_pl0 and vneg_pl1, and the two input terminals of the multiplexer connected to the gate switch 401 are respectively coupled to vneg_pl0 and vneg_pl1, and the two output terminals of the multiplexer are respectively coupled to load_pl0 and load_pl1. During the asynchronous multi-plane independent read operation, all the multiple selection switches 401 of the multiplexer 400 are disconnected, so that each charge pump provides a negative power supply for the read voltage of a corresponding storage plane, for example, vneg_pl0 provides a negative power supply for the read voltage of load_pl0, and vneg_pl1 provides a negative power supply for the read voltage of load_pl1. In the ramp phase (AC phase), all the multiple selection switches 401 of the multiplexer 400 are closed, and six negative voltage charge pumps are turned on at the same time. Since the selection switches 401 of the multiplexer 400 are closed, the six negative voltage charge pumps are connected in parallel, and the six negative voltage charge pumps can provide negative power supplies for the read voltage of each storage plane respectively. In the stable phase (DC phase), the multiple gating switches 401 of the multiplexer 400 are at least partially closed, and the two charge pumps are turned on to provide negative power for the read voltage of at least one storage plane. For example, the closed gating switch 401 at least includes the gating switch 401 located between vneg_pl0 and vneg_pl1, and the two turned on charge pumps can be vneg_pl0 and vneg_pl1, and vneg_pl0 and vneg_pl1 together provide negative power for the read voltage of the storage plane load_pl0. In the embodiment of the present disclosure, the positions of the two turned on charge pumps are not limited, that is, the two turned on charge pumps can be adjacent or not adjacent. Here, during the asynchronous multi-plane independent read operation, the clock signals received by the clock signal ends of the six turned on charge pumps are different. During the normal read operation, the clock signals received by the clock signal ends of the two turned on charge pumps are different.

[0102] It should be understood that in the embodiments of the present disclosure, the number of charge pumps and storage planes is not limited thereto, and this application does not make any specific limitation thereto.

[0103] In the embodiment of the present disclosure, the clock signals received by the clock signal ends of the multiple charge pumps are different in that there is a preset delay time between the clock signals received by the clock signal ends of the multiple charge pumps.

[0104] refer to Figure 5 , Figure 5 A partial internal block diagram of the peripheral circuit provided in an embodiment of the present disclosure.

[0105] In the embodiment of the present disclosure, the peripheral circuit further includes: a clock signal generating circuit 500, the clock signal generating circuit 500 includes a clock generator 501 and a clock processing circuit 502, the input end of the clock processing circuit 502 is coupled to the clock generator 501;

[0106] The clock generator 501 is configured to generate a first clock signal;

[0107] The clock processing circuit 502 is configured to generate a second clock signal different from the first clock signal according to the first clock signal.

[0108] like Figure 5 As shown, the clock signal generating circuit 500 includes a clock generator 501, and the clock generator 501 is used to generate a first clock signal clk_1. The clock signal generating circuit 500 also includes a clock processing circuit 502, the input end of the clock processing circuit 502 is coupled to the output end of the clock generator 501, and the clock processing circuit 502 can receive the first clock signal clk_1 generated by the clock generator 501, and output a second clock signal clk_2 different from the first clock signal clk_1 according to the input first clock signal clk_1.

[0109] In the disclosed embodiment, the first clock signal and the second clock signal have a fixed clock period and clock frequency, and can have two levels, namely a low level and a high level. The high level can be different according to the requirements of the circuit. In a specific embodiment, the clock generator can generate the first clock signal by an oscillator that provides a square wave output.

[0110] In the embodiment of the present disclosure, the clock processing circuit 502 is specifically configured to delay the first clock signal by a preset delay time to generate a second clock signal.

[0111] In the embodiment of the present disclosure, the preset delay time is smaller than the clock period of the first clock signal.

[0112] In the embodiment of the present disclosure, the preset delay time is half of the clock period of the first clock signal.

[0113] In the disclosed embodiment, the preset delay time of the second clock signal compared to the first clock signal is designed to be half of the first clock cycle. During the ramp phase, there is no difference in the working states of the multiple charge pumps. During the stable phase, since the clock signal is down-converted, the delay time between the clock signals received by the clock signal terminals of the multiple charge pumps is also half of the first clock cycle, but the working states of the multiple charge pumps at the same time are different, that is, the times when the multiple charge pumps replenish the charge to the output terminal are different, and the delay time does not change with the changes in the power supply voltage and PVT (Process, Voltage, Temperature).

[0114] refer to Figure 6 , Figure 6 The waveform diagram is a diagram of the clock signals received by the clock signal terminals of multiple charge pumps and the read voltages outputted by the output nodes in accordance with the embodiment of the present disclosure.

[0115] In the embodiment of the present disclosure, the plurality of charge pumps include:

[0116] a first charge pump group and a second charge pump group, the first charge pump group comprising at least one first charge pump; the second charge pump group comprising at least one second charge pump; wherein the number of the first charge pumps in the first charge pump group is the same as the number of the second charge pumps in the second charge pump group;

[0117] The clock signal generating circuit includes a first output terminal and a second output terminal;

[0118] The clock signal generating circuit is configured to provide a clock signal to a first clock signal terminal of the first charge pump via a first output terminal;

[0119] The clock signal generating circuit is configured to provide a clock signal to a second clock signal terminal of the second charge pump via a second output terminal.

[0120] refer to Figure 4 , the peripheral circuit includes six charge pumps, which can be divided into two groups, namely the first charge pump group and the second charge pump group, and the number of charge pumps included in the two charge pump groups is the same. That is, the first charge pump group includes three first charge pumps, for example, the three first charge pumps are vneg_pl0, vneg_pl2 and vneg_pl4, and the second charge pump group also includes three second charge pumps, for example, the three second charge pumps are vneg_pl1, vneg_pl3 and vneg_pl5. Continue to refer to Figure 5The clock signal generating circuit 500 further includes a first output terminal 503 and a second output terminal 504, wherein the first output terminal 503 and the second output terminal 504 are respectively coupled to a first clock signal terminal 507 of a first charge pump 505 in the first charge pump group and a second clock signal terminal 508 of a second charge pump 506 in the second charge pump group. Since the clock signals output by the first output terminal and the second output terminal are different, the clock signal clk_unit0 received by the clock signal terminal of the first charge pump is different from the clock signal clk_unit1 received by the clock signal terminal of the second charge pump. Figure 6 shown.

[0121] In the disclosed embodiment, the positional relationship between the first charge pump and the second charge pump is not limited, that is, the multiple first charge pumps in the first charge pump group may be adjacent or not adjacent, and the multiple second charge pumps in the second charge pump group may be adjacent or not adjacent.

[0122] In the embodiment of the present disclosure, the first charge pump group is configured to, during the ramping phase, boost the input voltage received by the first input terminal of the first charge pump according to the first clock signal received by the first clock signal terminal, and then output it to an output node;

[0123] The second charge pump group is configured to boost the input voltage received at the second input terminal of the second charge pump and output the boosted voltage to the output node according to the second clock signal received at the second clock signal terminal during the ramp phase.

[0124] In a specific embodiment, in combination Figure 4 and Figure 6 During the ramping phase (AC phase), all the multiple selection switches 401 of the multiplexer 400 are closed, all the first charge pumps and all the second charge pumps are turned on, and all the first charge pumps and the second charge pumps jointly provide a negative power supply for the read voltage of each storage plane, so that the negative voltage VNEG decreases rapidly. Figure 5 and Figure 6, clk_unit0 and clk_unit1 are clock signals input to the clock signal terminals of the first charge pump and the second charge pump, respectively. More specifically, the first output terminal 503 and the second output terminal 504 of the clock signal generating circuit 500 output the first clock signal clk_1 and the second clock signal clk_2, respectively. The first clock signal clk_1 is input to the first clock signal terminal 507 of the first charge pump 505, and the input voltage received by the first input terminal 509 of the first charge pump 505 is boosted and then output to an output node. The second clock signal clk_2 is input to the second clock signal terminal 508 of the second charge pump 506, and the input voltage received by the second input terminal 510 of the second charge pump 506 is boosted and then output to the output node. Here, since all the multiple selection switches 401 of the multiplexer 400 are closed, the closed selection switches 401 form a path at each location of the multiplexer 400, and the output node can be any output terminal of the multiplexer 400, providing the same node voltage for each storage plane. Figure 4 In the embodiment, the 6 turned-on charge pumps can jointly provide a negative power supply for the read voltage of each storage plane in the 6 storage planes.

[0125] In the embodiment of the present disclosure, any first charge pump in the first charge pump group is configured to process an input voltage received at a first input terminal of the first charge pump and output the processed input voltage to an output node according to a third clock signal received at a first clock signal terminal during a stable phase;

[0126] Any second charge pump in the second charge pump group is configured to process an input voltage received at a second input terminal of the second charge pump and output the processed input voltage to an output node according to a fourth clock signal received at a second clock signal terminal during a stable phase.

[0127] Combination Figure 4 and Figure 6During the stable phase (DC phase), at least part of the gate switches 401 of the multiplexer 400 are closed. For example, if the negative voltage charge pump is to provide a negative power supply for the read voltage of load_pl0, the gate switch 401 between vneg_pl0 and vneg_pl1 can be closed, and the other gate switches 401 are opened, and at the same time, a first charge pump vneg_pl0 and a second charge pump vneg_pl1 are turned on. At this time, the turned-on first charge pump vneg_pl0 and a second charge pump vneg_pl1 jointly provide a negative power supply for the read voltage of at least one storage plane including load_pl0 to maintain the negative voltage VNEG stable. Here, the output node is located at the output end of the multiplexer coupled to load_pl0, that is, the output node is located at the output end of the multiplexer 400 coupled to the target storage plane. In a specific embodiment, if the negative voltage charge pump is to provide a negative power supply for the read voltages of multiple adjacent storage planes including load_pl0, multiple adjacent selection switches 401 including at least the selection switch 401 located between vneg_pl0 and vneg_pl1 can be closed, and a first charge pump vneg_pl0 and a second charge pump vneg_pl1 can be turned on. If the negative voltage charge pump is to provide a negative power supply for the read voltages of all storage planes, all selection switches 401 can be closed, and a first charge pump vneg_pl0 and a second charge pump vneg_pl1 can be turned on. At this time, the turned-on first charge pump vneg_pl0 and the turned-on second charge pump vneg_pl1 jointly provide a negative power supply for the read voltages of all six storage planes. In the embodiment of the present disclosure, in a normal read operation, the negative voltage charge pump can also provide a negative power supply for the read voltages of any number of multiple storage planes in all storage planes, and the present disclosure does not limit this.

[0128] Combination Figure 5 and Figure 6 The first output terminal 503 and the second output terminal 504 of the clock signal generating circuit 500 output the third clock signal clk_3 and the fourth clock signal clk_4 respectively. The third clock signal clk_3 is input to the first clock signal terminal 507 of the first charge pump 505, and the input voltage received by the first input terminal 509 of the first charge pump 505 is boosted and then output to the output node. The fourth clock signal clk_4 is input to the second clock signal terminal 508 of the second charge pump 506, and the input voltage received by the second input terminal 510 of the second charge pump 506 is boosted and then output to the output node.

[0129] like Figure 5As shown, in the embodiment of the present disclosure, the clock signal generating circuit 500 further includes: a first selection switch 511 and a first clock divider 512; the input end of the first selection switch 511 is coupled to the clock generator 501, the output end of the first selection switch 511 is coupled to the first output end 503 of the clock signal generating circuit 500 or the first clock divider 512, and the output end of the first clock divider 512 is coupled to the first output end 503 of the clock signal generating circuit 500;

[0130] The first selection switch 511 is configured such that during the ramp phase, the output terminal of the first selection switch 511 is coupled to the first output terminal 503 of the clock signal generating circuit 500, and the first clock signal clk_1 generated by the clock generator 501 is transmitted to the first charge pump 505; and during the stable phase, the output terminal of the first selection switch 511 is coupled to the first clock divider 512, and the first clock signal clk_1 generated by the clock generator 501 is transmitted to the first clock divider 512;

[0131] The first clock divider 512 is configured to perform a frequency division process according to the first clock signal clk_1 to generate a third clock signal clk_3 during a stable phase, and transmit the third clock signal clk_3 to the first charge pump 505 .

[0132] like Figure 5 As shown, in the embodiment of the present disclosure, the clock signal generating circuit 500 further includes: a second selection switch 513 and a second clock divider 514; the input end of the second selection switch 513 is coupled to the clock processing circuit 502, the output end of the second selection switch 513 is coupled to the second output end 504 of the clock signal generating circuit 500 or the second clock divider 514, and the output end of the second clock divider 514 is coupled to the second output end 504 of the clock signal generating circuit 500;

[0133] The second selection switch 513 is configured such that during the ramp phase, the output terminal of the second selection switch 513 is coupled to the second output terminal 504 of the clock signal generating circuit 500, and the second clock signal clk_2 generated by the clock processing circuit 502 is transmitted to the second charge pump 506; and during the stable phase, the output terminal of the second selection switch 513 is coupled to the second clock divider 514, and the second clock signal clk_2 generated by the clock processing circuit 502 is transmitted to the second clock divider 514;

[0134] The second clock divider 514 is configured to perform a frequency division process according to the second clock signal clk_2 to generate a fourth clock signal clk_4 during a stable phase, and transmit the fourth clock signal clk_4 to the second charge pump 506 .

[0135] In the embodiment of the present disclosure, during the ramp phase, the clock signal generating circuit provides the first clock signal and the second clock signal to the first clock signal terminal of the first charge pump and the second clock signal terminal of the second charge pump respectively, and the working states of the first charge pump and the second charge pump are the same. During the stable phase, compared with the case where only one charge pump is turned on, the embodiment of the present disclosure turns on two charge pumps, which can reduce the current load on each charge pump basic unit by half, and at the same time, because the frequency of the clock signal connected to the charge pump clock signal terminal is reduced, the current efficiency is improved.

[0136] During the stable stage, compared with the situation where only two charge pumps are turned on and the clock signal terminals of the two charge pumps are connected to the same clock signal, the clock signal generating circuit of the embodiment of the present invention provides a third clock signal and a fourth clock signal to the first clock signal terminal of the first charge pump and the second clock signal terminal of the second charge pump, respectively, so that the timings for the first charge pump and the second charge pump to replenish the output terminals are staggered, thereby reducing the peak current.

[0137] refer to Figure 6 In the disclosed embodiment, the clock period of the first clock signal clk_1 and the clock period of the second clock signal clk_2 are both the first period; in a specific embodiment, the frequency corresponding to the first period is 50 MHz;

[0138] The clock period of the third clock signal clk_3 and the clock period of the fourth clock signal clk_4 are the same, both being the second period; the second period is twice the first period. In a specific embodiment, the frequency corresponding to the second period is 25 MHz.

[0139] In the disclosed embodiment, in order to reduce power consumption, the clock signal is frequency-reduced in the stable phase, and the clock delay of the frequency-reduced fourth clock signal clk_4 compared to the third clock signal clk_3 does not change with changes in the power supply voltage and PVT.

[0140] In the disclosed embodiment, the clock processing circuit includes: an inverting circuit.

[0141] In the embodiment of the present disclosure, the clock processing circuit may be an inverting circuit, which may generate a second clock signal clk_2 inverted from the first clock signal clk_1 according to the input first clock signal clk_1. The inverting circuit includes an inverter.

[0142] In one embodiment, an RC clock delay circuit is used to implement the time delay of the clock signal. However, the disclosed embodiment uses only one inverter (i.e., a clock processing circuit) to implement the time delay of the clock signal, thus avoiding the disadvantages of the RC clock delay circuit, such as complex control logic, large area, and clock delay changes with PVT.

[0143] In the disclosed embodiment, the charge pump boosts the input voltage at the input end and then outputs the output voltage to the output end; wherein the absolute value of the output voltage is greater than the absolute value of the input voltage.

[0144] refer to Figure 7 , Figure 7 A circuit diagram of a charge pump provided in accordance with an embodiment of the present disclosure.

[0145] like Figure 7 As shown, the charge pump provided in the embodiment of the present disclosure may be a cross-coupled charge pump 704. The cross-coupled charge pump 704 includes an input terminal 705, an output terminal 706, and two clock signal terminals 702 and 703. The cross-coupled charge pump 704 may include two N-type transistors, namely a first NMOS tube 710 and a second NMOS tube 711, and two P-type transistors, namely a first PMOS tube 708 and a second PMOS tube 709. Among them, the gate of the first NMOS tube 710, the gate of the first PMOS tube 708, the drain of the second NMOS tube 711, and the drain of the second PMOS tube 709 are connected; the gate of the second NMOS tube 711, the gate of the second PMOS tube 709, the drain of the first NMOS tube 710, and the drain of the first PMOS tube 708 are connected. The input terminal 705 of the charge pump is connected to the source of the first PMOS tube 708 and the source of the second PMOS tube 709; the output terminal 706 of the charge pump is connected to the source of the first NMOS tube 710 and the source of the second NMOS tube 711. The cross-coupled charge pump 704 also includes two capacitors, namely a first capacitor C1 and a second capacitor C2, wherein one end of the first capacitor C1 is connected to the gate of the second PMOS tube 709, and the other end of the first capacitor C1 is connected to one of the clock signal terminals 702; one end of the second capacitor C2 is connected to the gate of the first PMOS tube 708, and the other end of the second capacitor C2 is connected to another clock signal terminal 703.

[0146] like Figure 7 As shown, the charge pump provided by the embodiment of the present disclosure may also include two buffer circuits 701 to improve the driving of the charge pump. The two buffer circuits 701 are respectively coupled between any capacitor of the charge pump and the corresponding clock signal terminal. For example, one buffer circuit 701 is coupled between the first capacitor C1 and a clock signal terminal 702, and the other buffer circuit 701 is coupled between the second capacitor C2 and another clock signal terminal 703. In a specific embodiment, the buffer circuit can be an inverting circuit, such as Figure 7As shown, the inverting circuit can be composed of an NMOS tube and a PMOS tube, the gate of the NMOS tube is connected to the gate of the PMOS tube as an input end; the drain of the PMOS tube is connected to the drain of the NMOS tube as an output end, the source of the PMOS tube is connected to the power supply vsup, and the source of the NMOS tube is grounded.

[0147] Based on the working principle of the cross-coupled charge pump, the two clock signal terminals of a charge pump receive opposite clock signals, and half of the charge pump circuit works in each half clock cycle. That is, when the input terminal of the charge pump receives the input voltage Vin, if the clock signal terminal connected to the second capacitor C2 receives a high level V CLK , the clock signal end connected to the first capacitor C1 receives a low level V0 (V0=0), and the clock signal end receives the transient state of the rising edge of the clock signal, the second PMOS tube 709 and the first NMOS tube 710 are turned on, and the first PMOS tube 708 and the second NMOS tube 711 are turned off. The charge pump supplements the charge at the output end, so that the voltage at the output end increases to Vin+V CLK If the clock signal terminal connected to the first capacitor C1 receives a high level V CLK , the clock signal end connected to the second capacitor C2 receives a low level V0 (V0=0), and the clock signal end receives the transient state of the rising edge of the clock signal, the first PMOS tube 708 and the second NMOS tube 711 are turned on, and the second PMOS tube 709 and the first NMOS tube 710 are turned off. The charge pump supplements the charge at the output end, so that the voltage at the output end increases to Vin+V CLK As the levels of the two clock signal terminals of the charge pump change, the cross-coupled charge pump will alternately repeat the above-mentioned charge replenishment state so that the voltage at the output terminal of the charge pump always remains at Vin+V CLK . In the embodiment of the present disclosure, during the stable stage after the clock signal is frequency-reduced, since the fourth clock signal has a preset delay time compared to the third clock signal, while the first charge pump provides charge to the output end in each clock cycle, the clock delay allows the second charge pump basic unit to supplement the charge at the output end when the clock flips (i.e., the rising edge of the fourth clock signal). Compared to the situation where the clock signal ends of the two charge pumps receive the same clock signal and the clock signal is frequency-reduced, the time delay for the two charge pumps in the embodiment of the present disclosure to provide charge to the output node is halved, and this clock delay mechanism can effectively reduce the voltage ripple of the output node.

[0148] by Figure 4Take the six charge pumps in the example, assuming that the current load on each storage plane is 150uA. Set the simulation conditions as follows: normal read mode, VCC = 2.5V, temperature is 25°C, process corner is the center process corner (Typical Typical Corner, TT corner), and the negative voltage target value is -3V. For the output voltage ripple of the three different solutions, the power consumption on the VCC power supply voltage and the stabilized negative voltage value are shown in Table 1 below:

[0149]

[0150] In Table 1, the three schemes are all data measured during the stable phase. Among them, Scheme 1 is a case where only one charge pump is turned on, and the clock signal connected to the clock signal end of the charge pump is not frequency-reduced. Scheme 2 is a case where two charge pumps are turned on, and the clock signals connected to the clock signal ends of the two charge pumps are frequency-reduced, but the two clock signals connected to the clock signal ends of the two charge pumps are the same, that is, there is no clock delay between the two clock signals connected to the two charge pumps. Scheme 3 is a scheme provided by an embodiment of the present disclosure.

[0151] As can be seen from Table 1, the output voltage provided by the charge pump in Solution 1 cannot reach the target value. Solution 2 can effectively improve the current efficiency and driving capability by turning on two charge pumps. The increase in driving capability can recover faster when the read voltage is disturbed, and the improvement in current efficiency can effectively reduce the power consumption of the negative voltage charge pump. However, the negative voltage ripple provided by the two charge pumps in Solution 2 cannot meet the requirements. The solution provided by the embodiment of the present disclosure can effectively reduce the ripple of the voltage output to the output node on the basis of effectively improving the current efficiency and driving capability.

[0152] Under the premise of effectively combining and utilizing the existing circuit, the disclosed embodiment only adds two inverters to achieve a very small ripple in the output voltage of the negative charge pump under normal reading operation. It can be understood that the disclosed embodiment uses an inverter to generate a time delay between the second clock signal and the first clock signal, and the ripple size of the negative voltage provided is similar compared to the use of an RC clock delay circuit. However, the use of an RC clock delay circuit will increase more circuit area, add more control logic, and cause changes in delay due to PVT.

[0153] refer to Figure 8 , Figure 8 A block diagram of a storage system provided in an embodiment of the present disclosure. Figure 8 As shown, the embodiment of the present disclosure provides a memory system 801, and the memory system 801 includes:

[0154] The memory 802 in the above technical solution; and

[0155] A controller 803 is coupled to the memory 802 and configured to control the memory 802 .

[0156] In the disclosed embodiment, the memory system 801 can be integrated into various types of storage devices, for example, included in the same package (for example, a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the memory system 801 can be applied to and packaged into different types of electronic products, for example, mobile phones (such as mobile phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0157] In some embodiments, the controller 803 is configured to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0158] In other embodiments, the controller 803 is configured to operate in a high duty cycle environment (Solid State Drive, SSD) or an embedded Multi-Media Card (eMMC), where the SSD or eMMC is used for data storage in mobile devices such as smart phones, tablets, and laptops, as well as enterprise storage arrays.

[0159] The controller 803 may be configured to control the operation of the semiconductor device, such as read, erase, and program operations. The controller 803 may also be configured to manage various functions regarding data stored or to be stored in the semiconductor device, including but not limited to bad block management, garbage collection, logical address to physical address conversion, wear leveling, etc. In some embodiments, the controller 803 is also configured to process error correction codes (ECC) regarding data read from or written to the semiconductor device.

[0160] The controller 803 may also perform any other suitable functions, for example, formatting a semiconductor device. The controller 803 may communicate with an external device (e.g., a host) according to a specific communication protocol. For example, the controller 803 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0161] The present disclosure also provides an operating method of a memory, the memory comprising: a plurality of memory planes and a peripheral circuit coupled to the memory planes, the peripheral circuit comprising: a plurality of charge pumps, the charge pumps having a clock signal terminal, an input terminal and an output terminal; the output terminal of each charge pump is coupled to a memory plane in the plurality of memory planes; the operating method comprises:

[0162] The clock signal terminals of the plurality of charge pumps receive the clock signal;

[0163] In response to a clock signal received at a clock signal end, an input voltage at an input end is boosted and then output to an output end; wherein the clock signals received at the clock signal ends of the multiple charge pumps are different.

[0164] In the embodiment of the present disclosure, there is a preset delay time between the clock signals received by the clock signal terminals of the plurality of charge pumps.

[0165] In the disclosed embodiment, the peripheral circuit further includes: a clock signal generating circuit, the clock signal generating circuit including a clock generator and a clock processing circuit, the input end of the clock processing circuit being coupled to the clock generator;

[0166] The clock generator generates a first clock signal;

[0167] The clock processing circuit generates a second clock signal different from the first clock signal based on the first clock signal.

[0168] In the embodiment of the present disclosure, the clock processing circuit generates a second clock signal different from the first clock signal according to the first clock signal, including:

[0169] The clock processing circuit delays the first clock signal by a preset delay time to generate a second clock signal.

[0170] In the embodiment of the present disclosure, the preset delay time is smaller than the clock period of the first clock signal.

[0171] In the embodiment of the present disclosure, the preset delay time is half of the clock period of the first clock signal.

[0172] In the disclosed embodiment, the peripheral circuit further includes: a multiplexer, the multiplexer being coupled between the plurality of charge pumps and the plurality of storage planes;

[0173] In an asynchronous multi-plane independent read operation, each charge pump outputs a boosted voltage to one of the multiple storage planes through a multiplexer; in a normal read operation, multiple charge pumps are connected in parallel through the multiplexer and the multiple charge pumps output the boosted voltage to an output node together.

[0174] In the embodiment of the present disclosure, the plurality of charge pumps include:

[0175] a first charge pump group and a second charge pump group, the first charge pump group comprising at least one first charge pump; the second charge pump group comprising at least one second charge pump; wherein the number of the first charge pumps in the first charge pump group is the same as the number of the second charge pumps in the second charge pump group;

[0176] In response to a clock signal received at a clock signal terminal, an input voltage at an input terminal is boosted and then outputted to an output terminal, comprising:

[0177] During the ramp phase, the first charge pump group, in response to the first clock signal, boosts the input voltage received at the first input terminal of the first charge pump and outputs the voltage to an output node;

[0178] During the ramp phase, the second charge pump group responds to the second clock signal to boost the input voltage received at the second input terminal of the second charge pump and output the boosted voltage to the output node.

[0179] In the embodiment of the present disclosure, a plurality of charge pumps respond to a clock signal received at a clock signal terminal, boost an input voltage at an input terminal, and then output the voltage to an output terminal, and further include:

[0180] During the stable phase, any first charge pump in the first charge pump group processes the input voltage received at the first input terminal and outputs the processed input voltage to the output node in response to the third clock signal received at the first clock signal terminal;

[0181] During the stable phase, any second charge pump in the second charge pump group processes the input voltage received at the second input terminal and outputs the processed input voltage to the output node in response to the fourth clock signal received at the second clock signal terminal.

[0182] In the embodiment of the present disclosure, the memory operation method further includes: during the stable phase, dividing the first clock signal to generate a third clock signal; dividing the second clock signal to generate a fourth clock signal.

[0183] In the embodiment of the present disclosure, the clock period of the first clock signal and the clock period of the second clock signal are both the first period;

[0184] The clock period of the third clock signal is the same as the clock period of the fourth clock signal, which is the second period; the second period is twice the first period.

[0185] In the embodiment of the present disclosure, the input voltage at the input end is boosted and then output to the output end, including: a charge pump boosts the input voltage so that the absolute value of the boosted voltage is greater than the absolute value of the input voltage.

[0186] The embodiments of the present disclosure provide a memory, a memory system and a memory operation method. The memory includes: a plurality of memory planes and a peripheral circuit coupled to the memory plane, the peripheral circuit includes: a plurality of charge pumps, the charge pumps having a clock signal terminal, an input terminal and an output terminal; the output terminal of each charge pump is coupled to a memory plane in the plurality of memory planes; the charge pump is configured to boost the input voltage of the input terminal and output it to the output terminal according to the clock signal received by the clock signal terminal; wherein the clock signals received by the clock signal terminals of the plurality of charge pumps are different. Compared with the clock signal terminals of the plurality of charge pumps receiving the same clock signal, in the embodiments of the present disclosure, during the stable stage, since the clock signal terminals of the plurality of charge pumps receive different clock signals, the times at which the plurality of charge pumps provide charge to the output terminal are different, thereby effectively reducing the voltage ripple and improving the stability of the read voltage.

[0187] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0188] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A memory, characterized in that: The memory comprises: a plurality of memory planes and a peripheral circuit coupled to the memory planes, wherein the peripheral circuit comprises: A plurality of charge pumps, each having a clock signal terminal, an input terminal and an output terminal; the output terminal of each of the charge pumps is coupled to one of the plurality of storage planes; the charge pump is configured to boost the input voltage of the input terminal according to the clock signal received by the clock signal terminal, and then output the boost voltage to the output terminal; wherein the clock signals received by the clock signal terminals of the plurality of charge pumps are different.

2. The memory according to claim 1, characterized in that: There is a preset delay time between the clock signals received by the clock signal terminals of the plurality of charge pumps.

3. The memory according to claim 1, characterized in that: The peripheral circuit further comprises: a clock signal generating circuit, the clock signal generating circuit comprising a clock generator and a clock processing circuit, an input end of the clock processing circuit being coupled to the clock generator; The clock generator is configured to generate a first clock signal; The clock processing circuit is configured to generate a second clock signal different from the first clock signal based on the first clock signal.

4. The memory according to claim 3, characterized in that: The clock processing circuit is specifically configured to delay the first clock signal by a preset delay time to generate the second clock signal.

5. The memory according to claim 4, characterized in that: The preset delay time is smaller than a clock period of the first clock signal.

6. The memory according to claim 4, characterized in that: The preset delay time is half of a clock period of the first clock signal.

7. The memory according to claim 1, characterized in that: The peripheral circuit also includes: a multiplexer, which is coupled between the multiple charge pumps and the multiple storage planes; wherein, in an asynchronous multi-plane independent read operation, each of the charge pumps is coupled to one of the multiple storage planes through the multiplexer; in a normal read operation, the multiple charge pumps are connected in parallel through the multiplexer and the output ends of the multiple charge pumps are commonly coupled to an output node.

8. The memory according to claim 3, characterized in that: The plurality of charge pumps include: a first charge pump group and a second charge pump group, the first charge pump group comprising at least one first charge pump; the second charge pump group comprising at least one second charge pump; wherein the number of the first charge pumps in the first charge pump group is the same as the number of the second charge pumps in the second charge pump group; The clock signal generating circuit comprises a first output terminal and a second output terminal; The clock signal generating circuit is configured to provide a clock signal to a first clock signal terminal of the first charge pump via the first output terminal; The clock signal generating circuit is configured to provide a clock signal to a second clock signal terminal of the second charge pump via the second output terminal.

9. The memory according to claim 8, characterized in that: The first charge pump group is configured to, during the ramp phase, boost an input voltage received at a first input terminal of the first charge pump according to a first clock signal received at the first clock signal terminal, and then output the boosted input voltage to an output node; The second charge pump group is configured to, during a ramp phase, boost an input voltage received at a second input terminal of the second charge pump according to a second clock signal received at the second clock signal terminal, and then output the boosted input voltage to the output node.

10. The memory according to claim 9, characterized in that: Any of the first charge pumps in the first charge pump group is configured to process an input voltage received at a first input terminal of the first charge pump according to a third clock signal received at the first clock signal terminal during a stable phase, and then output the processed input voltage to the output node; Any second charge pump in the second charge pump group is configured to process an input voltage received at a second input terminal of the second charge pump according to a fourth clock signal received at the second clock signal terminal during a stable phase, and then output the processed input voltage to the output node.

11. The memory according to claim 10, characterized in that: The clock signal generating circuit further comprises: a first selection switch and a first clock divider; an input end of the first selection switch is coupled to the clock generator, an output end of the first selection switch is coupled to a first output end of the clock signal generating circuit or the first clock divider, and an output end of the first clock divider is coupled to a first output end of the clock signal generating circuit; The first selection switch is configured such that during a ramping phase, an output terminal of the first selection switch is coupled to a first output terminal of the clock signal generating circuit to transmit the first clock signal generated by the clock generator to the first charge pump; and during a stabilization phase, an output terminal of the first selection switch is coupled to the first clock divider to transmit the first clock signal generated by the clock generator to the first clock divider; The first clock divider is configured to perform a frequency division process on the first clock signal during the stable phase to generate the third clock signal, and transmit the third clock signal to the first charge pump.

12. The memory according to claim 10, characterized in that: The clock signal generating circuit further includes: a second selection switch and a second clock divider; an input end of the second selection switch is coupled to the clock processing circuit, an output end of the second selection switch is coupled to a second output end of the clock signal generating circuit or the second clock divider, and an output end of the second clock divider is coupled to a second output end of the clock signal generating circuit; The second selection switch is configured such that during a ramp phase, an output terminal of the second selection switch is coupled to a second output terminal of the clock signal generating circuit, so as to transmit the second clock signal generated by the clock processing circuit to the second charge pump; and during a stable phase, an output terminal of the second selection switch is coupled to the second clock divider, so as to transmit the second clock signal generated by the clock processing circuit to the second clock divider; The second clock divider is configured to perform a frequency division process on the second clock signal during the stable phase to generate the fourth clock signal, and transmit the fourth clock signal to the second charge pump.

13. The memory according to claim 10, characterized in that: A clock period of the first clock signal and a clock period of the second clock signal are both a first period; The clock period of the third clock signal is the same as the clock period of the fourth clock signal, which is the second period; the second period is twice the first period.

14. The memory according to claim 3, characterized in that: The clock processing circuit includes: an inverting circuit.

15. The memory according to claim 1, characterized in that: The charge pump boosts the input voltage at the input end and then outputs the output voltage to the output end; wherein the absolute value of the output voltage is greater than the absolute value of the input voltage.

16. A memory system, characterized in that: The memory system comprises: The memory as claimed in any one of claims 1 to 15; and A controller is coupled to the memory and configured to control the memory.

17. A method for operating a memory, characterized in that: The memory comprises: a plurality of storage planes and a peripheral circuit coupled to the storage planes, the peripheral circuit comprising: a plurality of charge pumps, the charge pumps having a clock signal terminal, an input terminal and an output terminal; the output terminal of each charge pump is coupled to one of the storage planes in the plurality of storage planes; the operation method comprises: The clock signal terminals of the plurality of charge pumps receive a clock signal; In response to the clock signal received by the clock signal end, the input voltage of the input end is boosted and then output to the output end; wherein the clock signals received by the clock signal ends of the multiple charge pumps are different.

18. The memory operation method according to claim 17, characterized in that: There is a preset delay time between the clock signals received by the clock signal terminals of the plurality of charge pumps.

19. The memory operation method according to claim 17, characterized in that: The peripheral circuit further comprises: a clock signal generating circuit, the clock signal generating circuit comprising a clock generator and a clock processing circuit, an input end of the clock processing circuit being coupled to the clock generator; The clock generator generates a first clock signal; The clock processing circuit generates a second clock signal different from the first clock signal based on the first clock signal.

20. The memory operating method according to claim 19, characterized in that: The clock processing circuit generates a second clock signal different from the first clock signal according to the first clock signal, comprising: The clock processing circuit delays the first clock signal by a preset delay time to generate the second clock signal.

21. The memory operation method according to claim 20, characterized in that: The preset delay time is smaller than a clock period of the first clock signal.

22. The memory operating method according to claim 20, characterized in that: The preset delay time is half of a clock period of the first clock signal.

23. The memory operation method according to claim 17, characterized in that: The peripheral circuit further includes: a multiplexer coupled between the plurality of charge pumps and the plurality of storage planes; In an asynchronous multi-plane independent read operation, each of the charge pumps outputs the boosted voltage to one of the multiple storage planes through the multiplexer; in a normal read operation, the multiple charge pumps are connected in parallel through the multiplexer and the multiple charge pumps output the boosted voltage together to an output node.

24. The memory operating method according to claim 19, characterized in that: The plurality of charge pumps include: a first charge pump group and a second charge pump group, the first charge pump group comprising at least one first charge pump; the second charge pump group comprising at least one second charge pump; wherein the number of the first charge pumps in the first charge pump group is the same as the number of the second charge pumps in the second charge pump group; The step of boosting the input voltage of the input terminal and outputting the voltage to the output terminal in response to the clock signal received by the clock signal terminal comprises: During the ramp phase, the first charge pump group, in response to the first clock signal, boosts the input voltage received at the first input terminal of the first charge pump and outputs the boosted voltage to an output node; During the ramp phase, the second charge pump group responds to the second clock signal to boost an input voltage received at a second input terminal of the second charge pump and output the boosted voltage to the output node.

25. The memory operating method according to claim 24, characterized in that: The plurality of charge pumps respond to the clock signal received by the clock signal end to boost the input voltage of the input end and output the voltage to the output end, and further include: During a stable phase, any of the first charge pumps in the first charge pump group processes an input voltage received at the first input terminal and outputs the processed input voltage to the output node in response to a third clock signal received at the first clock signal terminal; During a stable phase, any second charge pump in the second charge pump group processes an input voltage received at the second input terminal in response to a fourth clock signal received at the second clock signal terminal, and then outputs the processed input voltage to the output node.

26. The memory operating method according to claim 25, characterized in that: The method further includes: during the stable phase, dividing the first clock signal to generate the third clock signal; and dividing the second clock signal to generate the fourth clock signal.

27. The memory operating method according to claim 25, characterized in that: A clock period of the first clock signal and a clock period of the second clock signal are both a first period; The clock period of the third clock signal is the same as the clock period of the fourth clock signal, which is the second period; the second period is twice the first period.

28. The memory operating method according to claim 17, characterized in that: The step of boosting the input voltage at the input end and outputting it to the output end comprises: the charge pump boosts the input voltage so that the absolute value of the boosted voltage is greater than the absolute value of the input voltage.

Images