Method for strengthening tantalum nitride film
By forming and densely treating the tantalum nitride film on the surface of the semiconductor substrate, the problem of insufficient density of the tantalum nitride layer is solved, and the WAT parameters, yield rate and reliability of the product are significantly improved.
Patent Information
- Application Number
- CN202311543145.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-16
- Publication Date
- 2025-05-16
AI Technical Summary
The existing tantalum nitride layer has insufficient density, which leads to damage during the etching process, which in turn affects the WAT parameters, yield rate and reliability of the product.
The tantalum nitride film is formed by atomic layer deposition on the surface of the semiconductor substrate, and the tantalum nitride film is densely treated by physical vapor deposition method to form a dense tantalum nitride layer.
The density of the tantalum nitride layer is improved, its ions-blocking effect and etch resistance are enhanced, thereby improving the WAT parameters, yield and reliability of the product.
Smart Images
Figure CN120015609A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor integrated circuits, and in particular, to a method for strengthening a tantalum nitride film. Background Art
[0002] As the size of semiconductor integrated circuits continues to shrink to below 45nm, the thickness of the gate dielectric layer is also reduced to below 2nm, which will cause gate leakage current in the traditional transistor structure. In order to improve the above problems, high-K dielectric materials are often used to replace SiON as the gate oxide layer, and metal gates are used instead of polysilicon gates. This is called HKMG process technology.
[0003] In the existing HKMG process technology, a barrier layer is generally set above the gate oxide layer of the high-K dielectric. The barrier layer is composed of a titanium nitride layer and a tantalum nitride layer set above the titanium nitride layer. On the one hand, it can block the ions located above the tantalum nitride layer from entering the gate oxide layer of the high-K dielectric, and on the other hand, it can stop the subsequent etching process at the tantalum nitride layer. However, the existing tantalum nitride layer is not dense enough, resulting in damage during the etching process, which in turn causes the problem of reduced WAT parameters, yield and reliability of the product. Summary of the invention
[0004] The purpose of the present disclosure is to provide a method for strengthening a tantalum nitride film to solve the problem of insufficient density of the tantalum nitride layer in the prior art.
[0005] In order to achieve the above object, the present disclosure provides a method for strengthening a tantalum nitride film, the method comprising:
[0006] S1, providing a semiconductor substrate obtained after removing the pseudo polysilicon gate process;
[0007] S2. Forming a tantalum nitride film on the surface of the semiconductor substrate by atomic layer deposition, and densifying the tantalum nitride film by physical vapor deposition to obtain a dense tantalum nitride layer.
[0008] Optionally, the dense tantalum nitride layer has a thickness of 5 to 30 angstroms.
[0009] Optionally, the physical vapor deposition method includes any one of vacuum sputtering deposition and ion plating deposition.
[0010] Optionally, the reaction temperature of the atomic layer deposition is 250-350° C., and the reaction precursor is Ta[N(CH3)2]5.
[0011] Optionally, the reaction temperature of the physical vapor deposition is 25-300°C.
[0012] Optionally, step S1 includes:
[0013] S11, sequentially forming an oxide layer, a high-K dielectric layer and a transition layer on a silicon-based substrate including an N-type metal gate region and a P-type metal gate region;
[0014] S12, performing a pseudo polysilicon gate process on the N-type metal gate region and the P-type metal gate region to form a pseudo polysilicon gate;
[0015] S13, performing a pseudo polysilicon gate removal process on the pseudo polysilicon gate above the transition layer to form a groove for filling a metal gate above the transition layer; wherein the groove includes an N-type metal gate groove corresponding to the position of the N-type metal gate region and a P-type metal gate groove corresponding to the position of the P-type metal gate region;
[0016] Wherein, the tantalum nitride film is formed on the surface of the N-type metal gate trench and the P-type metal gate trench;
[0017] The material of the oxide layer is SiO2 and / or SiON; the material of the high-K dielectric layer is HfO2; the material of the transition layer is TiN; and the method for removing the pseudo-polysilicon gate is dry etching and / or wet etching.
[0018] Optionally, the method further comprises:
[0019] S3, forming a P-type functional layer on the surface of the dense tantalum nitride layer;
[0020] S4, performing a process of removing a P-type functional layer from the N-type metal gate trench;
[0021] S5. Forming an N-type functional layer, an anti-diffusion layer and a metal gate in sequence on the surface of the semiconductor element obtained in S4.
[0022] Optionally, the method for removing the dummy polysilicon gate is dry etching and / or wet etching; the method for removing the P-type functional layer is wet etching and / or dry etching; the etching solution used in the wet etching is SC1 etching solution and / or SC2 etching solution.
[0023] Optionally, the material of the P-type functional layer is TiN; the material of the N-type functional layer is TiAl.
[0024] Optionally, the anti-diffusion layer includes a first anti-diffusion layer and a second anti-diffusion layer; the second anti-diffusion layer is located above the first anti-diffusion layer; the material of the first anti-diffusion layer is TiN; and the material of the second anti-diffusion layer is Ti.
[0025] Optionally, the material of the metal gate is Al.
[0026] Optionally, the method is used in 28nm and 22nm HKMG processes.
[0027] Through the above technical scheme, an atomic layer deposition method is used to form a tantalum nitride film on the transition layer, and then the tantalum nitride film is densified by physical vapor deposition to form a dense tantalum nitride layer. The tantalum nitride layer, especially the density of the upper surface of the tantalum nitride layer, can be improved, which can not only improve the ion blocking effect of the tantalum nitride layer, but also improve the etching resistance of the tantalum nitride layer, thereby improving the WAT parameters, yield rate and reliability of the product.
[0028] Other features and advantages of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:
[0030] Figure 1 The present invention discloses a flow chart of a method for strengthening a tantalum nitride film.
[0031] Figure 2 Detailed description of the invention The figure is a flow chart of a HKMG process disclosed in the present invention.
[0032] Figure 3 It is a schematic diagram of a semiconductor substrate obtained after removing a pseudo polysilicon gate process disclosed in the present invention.
[0033] Figure 4 It is a schematic diagram of a metal gate structure made by the HKMG process disclosed in the present invention.
[0034] Description of Reference Numerals
[0035] 1. Silicon-based substrate; 2. Sidewall; 3. Oxide layer; 4. High-K dielectric layer; 5. Transition layer; 6. Dense tantalum nitride layer; 7. P-type functional layer; 8. N-type functional layer; 9. First anti-diffusion layer; 10. Second anti-diffusion layer; 11. Metal gate; 12. PMOS structure; 13. NMOS structure. DETAILED DESCRIPTION
[0036] The specific implementation of the present disclosure is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the present disclosure, and is not used to limit the present disclosure.
[0037] like Figure 1 As shown, the present disclosure provides a method for strengthening a tantalum nitride film, the method comprising:
[0038] S1, providing a semiconductor substrate obtained after removing the pseudo polysilicon gate process;
[0039] S2, forming a tantalum nitride film on the surface of the semiconductor substrate by atomic layer deposition, and densifying the tantalum nitride film by physical vapor deposition to obtain a dense tantalum nitride layer 6.
[0040] Through the above technical scheme, a tantalum nitride film is formed on the transition layer 5 by an atomic layer deposition method, and then the tantalum nitride film is densified by physical vapor deposition to form a dense tantalum nitride layer 6, which can improve the density of the tantalum nitride layer, especially the upper surface of the tantalum nitride layer, which can not only improve the ion blocking effect of the tantalum nitride layer, but also improve the etching resistance of the tantalum nitride layer, thereby improving the WAT parameters, yield rate and reliability of the product.
[0041] like Figure 2 As shown, in one implementation, step S1 includes:
[0042] S11, sequentially forming an oxide layer 3, a high-K dielectric layer 4 and a transition layer 5 on a silicon-based substrate 1 including an N-type metal gate region and a P-type metal gate region;
[0043] S12, performing a pseudo polysilicon gate process on the N-type metal gate region and the P-type metal gate region to form a pseudo polysilicon gate;
[0044] S13, removing the pseudo polysilicon gate above the transition layer 5 to form a groove for filling the metal gate above the transition layer 5; wherein the groove includes an N-type metal gate groove corresponding to the position of the N-type metal gate region and a P-type metal gate groove corresponding to the position of the P-type metal gate region;
[0045] Wherein, the tantalum nitride film is formed on the surface of the N-type metal gate trench and the P-type metal gate trench.
[0046] In one embodiment, the silicon-based substrate 1 used in the present disclosure is a conventional choice in the art, and the present application does not make any special requirements. For example, the silicon-based substrate 1 is an SOI substrate. The top silicon upper surface of the SOI substrate includes an N-type metal gate region and a P-type metal gate region.
[0047] In one embodiment, if Figure 3 As shown, the semiconductor substrate obtained after the process of removing the pseudo polysilicon gate comprises sidewall spacers 2 in both the N-type metal gate region and the P-type metal gate region, wherein the material of the sidewall spacers 2 is silicon nitride and / or silicon oxide.
[0048] A trench which can be filled with a metal gate is formed between the sidewall 2 of the N-type metal gate region and the sidewall 2 of the P-type metal gate region and the silicon-based substrate 1 .
[0049] In one embodiment, a stacked structure is provided at the bottom of the trench, and the stacked structure includes an oxide layer 3, a high-K dielectric layer 4 and a transition layer 5 from bottom to top.
[0050] In one embodiment, the material of the high-K dielectric layer 4 used in the present disclosure is a material with a relatively high dielectric constant, and the material of the high-K dielectric layer 4 can be selected from one or more of hafnium silicate oxide (HfSiO4), hafnium dioxide (HfO2), lanthanum oxide (La2O3), HfZrO2, zirconium dioxide (ZrO2), strontium titanate (SrTiO3) and zirconium silicate oxide (ZrSiO4). Preferably, the material of the high-K dielectric layer 4 used in the present disclosure is HfO2. In this embodiment, the dielectric constant of HfO2 is 25, which can increase the physical thickness of the gate dielectric layer under the same equivalent thickness and reduce the risk of high power consumption caused by gate leakage. However, if the high-K dielectric layer 4 is directly in contact with the silicon-based substrate 1, on the one hand, a rough interface will be formed between the high-K dielectric material and the substrate, which will cause carrier scattering and reduce the carrier mobility; on the other hand, the Hf atoms in the high-K dielectric material will chemically react with the silicon atoms of the polycrystalline silicon to form Hf-Si bonds, thereby forming defect centers, resulting in the inability to change the work function of the polycrystalline silicon by ion doping, causing the pinning phenomenon of the Fermi level; on the other hand, the dipoles near the lower surface of the gate dielectric layer will vibrate and be transmitted to the silicon atoms in the channel, causing lattice vibration, forming carrier phonon scattering, and reducing the speed of the device.
[0051] In one embodiment, the material of the oxide layer 3 used in the present disclosure is SiO2 and / or SiON. In this embodiment, in order to eliminate the problem caused by directly setting the high-K dielectric layer 4 on the silicon-based substrate 1, SiO2 and / or SiON can be set between the high-K dielectric layer 4 and the silicon-based substrate 1, and an ideal interface between SiON and Si and / or SiO2 and Si can be obtained, which can effectively improve the interface between the high-K dielectric material and the substrate, and can also improve the influence of the vibration of the dipole on the carrier mobility.
[0052] In one embodiment, the material of the transition layer 5 used in the present disclosure is TiN. In this embodiment, by providing the transition layer 5 above the high-K dielectric layer 4, the risk of ions from the functional function layer provided above entering the high-K dielectric layer 4 to react and affect the functional function value can be reduced.
[0053] In one embodiment, the method for removing the pseudo polysilicon gate is conventionally selected in the art, and this application does not make special requirements. For example, this application uses dry etching and / or wet etching to remove the pseudo polysilicon gate. In this embodiment, the pseudo polysilicon gate above the transition layer 5 in the N-type metal gate region and the P-type metal gate region is removed by dry etching and / or wet etching, so that the groove can be exposed again for subsequent processing.
[0054] In one embodiment, step S2 also includes performing a deposition process on the upper surface of the semiconductor substrate obtained after the pseudo polysilicon gate removal process to form a tantalum nitride film; and then performing a densification process on the tantalum nitride film to obtain the dense tantalum nitride layer 6, which covers the side and bottom surfaces of each groove and extends outside the groove.
[0055] In this embodiment, the method for obtaining the tantalum nitride film disclosed in the present invention is atomic layer deposition. This method can coat tantalum nitride on the surface of the substrate layer by layer in the form of a single atomic film. This method allows only one layer to be deposited each time the reaction occurs, and the bonding force between the layers is weak. Therefore, the prepared tantalum nitride film has a poor density between each atomic film. The inventors of the present invention use physical vapor deposition to densify the tantalum nitride film on the basis of atomic layer deposition. This method is to form the coating material into the form of atoms or ions, and to make the formed atoms or ions impact the substrate to achieve the purpose of coating the coating material on the surface of the substrate. In the process of performing the densification treatment, the tantalum nitride atoms or ions continuously impact the tantalum nitride film. Therefore, the method can, on the one hand, enable the tantalum nitride atoms or ions to be embedded in the gaps between molecules in the tantalum nitride film, thereby improving the density of the tantalum nitride film surface. On the other hand, the tantalum nitride atoms or ions, in the process of impacting the tantalum nitride film, transfer kinetic energy from the upper surface of the tantalum nitride film to the lower surface, thereby improving the density between each atomic film in the tantalum nitride film.
[0056] In one embodiment, the thickness of the formed dense tantalum nitride layer 6 is 5 to 30 angstroms, preferably 20 angstroms. In this embodiment, since the trajectory of the tantalum nitride molecules cannot be controlled during the physical vapor deposition process, the thickness may be uneven, but in the present application, the thickness of the dense tantalum nitride layer 6 is very small, so the thickness difference is very small and can be ignored.
[0057] In one embodiment, the reaction temperature of the atomic layer deposition is 250-350° C., preferably 275-300° C.; the reaction precursor of the atomic layer deposition is Ta[N(CH3)2]5.
[0058] In one embodiment, the conditions of the physical vapor deposition include: the reaction temperature is room temperature to 300°C.
[0059] In one embodiment, the physical vapor deposition includes any one of vacuum sputtering deposition and ion plating deposition.
[0060] like Figure 2 As shown, in one embodiment, the method further includes:
[0061] S3, forming a P-type functional layer 7 on the surface of the dense tantalum nitride layer 6;
[0062] S4, performing a process of removing a P-type functional layer from the N-type metal gate trench;
[0063] S5. An N-type functional layer 8, an anti-diffusion layer and a metal gate 11 are sequentially formed on the surface of the semiconductor element obtained in S4.
[0064] In one embodiment, step S3 further includes forming an atomic layer deposition on the upper surface of the semiconductor substrate obtained by the process of step S2 to form a P-type functional layer 7; the P-type functional layer 7 covers the side and bottom surfaces of each groove and extends outside the groove. In this embodiment, the P-type functional layer is first formed on the upper surface of the entire silicon-based substrate 1, and then only the N-type metal gate region is treated to remove the P-type functional layer, so that the P-type functional layer can be formed only in the groove of the P-type metal gate region.
[0065] In the above embodiment, since the dense tantalum nitride layer 6 in the N-type metal gate region has a good effect of blocking ions and improving the etching resistance of the tantalum nitride layer, it can not only prevent the ions of the P-type functional layer from entering the high-K dielectric layer 4, but also prevent the damage to the dense tantalum nitride layer 6 caused by the removal of the P-type functional layer, thereby improving the cleaning effect.
[0066] Among them, the material of the P-type functional layer is conventionally selected in the art, and this application does not make special requirements. For example, the material of the P-type functional layer used in this application is TiN.
[0067] Among them, the method of removing the P-type functional layer is a conventional choice in the art, and this application does not make special requirements. For example, this application uses wet etching and / or dry etching to remove the pseudo polysilicon gate. Preferably, this application uses wet etching. In this embodiment, the etching solution used for the wet etching can be SC1 etching solution and / or SC2 etching solution. Among them, SC1 etching solution and / or SC2 etching solution are conventional choices in the art, and this application does not make special requirements.
[0068] In one embodiment, step S5 further includes depositing an N-type functional layer 8 on the surface of the semiconductor element obtained after the processing in step S4, so that the N-type functional layer 8 covers the side and bottom surfaces of each groove and extends outside the groove.
[0069] The material of the N-type functional layer 8 is TiAl, and the N-type functional layer 8 can be formed by a physical vapor deposition method.
[0070] In one embodiment, step S5 further includes depositing a second anti-diffusion layer 10 after depositing the first anti-diffusion layer 9 on the silicon-based substrate 1 to form an anti-diffusion layer. In this embodiment, the anti-diffusion layer includes the first anti-diffusion layer 9 and the second anti-diffusion layer 10; the second anti-diffusion layer 10 is located above the first anti-diffusion layer 9;
[0071] The material of the first anti-diffusion layer 9 is TiN, and the material of the second anti-diffusion layer 10 is Ti; the first anti-diffusion layer 9 and the second anti-diffusion layer 10 can be formed by physical vapor deposition.
[0072] In one embodiment, step S5 also includes forming a metal gate layer on the upper surface of the silicon-based substrate 1, wherein the metal gate layer completely fills the grooves of the N-type metal gate area and the P-type metal gate area and extends outside the grooves; and then a chemical mechanical polishing process is used to remove the metal gate layer, anti-diffusion layer and N-type functional layer outside the grooves, and the upper surface of the silicon-based substrate 1 is polished to a position consistent with the height of the side wall 2.
[0073] In one embodiment, the method provided by the present disclosure is used in 28nm and 22nm HKMG processes.
[0074] In one embodiment, if Figure 4 As shown, the semiconductor element prepared by the method disclosed in the present invention includes a PMOS structure 12 and an NMOS structure 13; wherein, the structure in the NMOS structure 13 is an oxide layer 3, a high-K dielectric layer 4, a transition layer 5, a dense tantalum nitride layer 6, an N-type functional layer 8, a first anti-diffusion layer 9, a second anti-diffusion layer 10 and a metal gate 11 arranged in sequence from bottom to top; the structure in the PMOS structure 12 is an oxide layer 3, a high-K dielectric layer 4, a transition layer 5, a dense tantalum nitride layer 6, a P-type functional layer 7, an N-type functional layer 8, a first anti-diffusion layer 9, a second anti-diffusion layer 10 and a metal gate 11 arranged in sequence from bottom to top.
[0075] In this embodiment, since the tantalum nitride layer used in the present invention is a dense tantalum nitride layer, it has good ion blocking effect and etching resistance. Therefore, the method of the present invention can improve the WAT parameters, yield rate and reliability of the manufactured semiconductor.
[0076] The preferred embodiments of the present disclosure are described in detail above in conjunction with the accompanying drawings; however, the present disclosure is not limited to the specific details in the above embodiments. Within the technical concept of the present disclosure, a variety of simple modifications can be made to the technical solution of the present disclosure, and these simple modifications all fall within the protection scope of the present disclosure.
[0077] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present disclosure will not further describe various possible combinations.
[0078] In addition, various embodiments of the present disclosure may be arbitrarily combined, and as long as they do not violate the concept of the present disclosure, they should also be regarded as the contents disclosed by the present disclosure.
Claims
1. A method for strengthening a tantalum nitride film, characterized in that: The method includes: S1, providing a semiconductor substrate obtained after removing the pseudo polysilicon gate process; S2, forming a tantalum nitride film on the surface of the semiconductor substrate by atomic layer deposition, and densifying the tantalum nitride film by physical vapor deposition to obtain a dense tantalum nitride layer (6).
2. The method according to claim 1, characterized in that The thickness of the dense tantalum nitride layer (6) is 5 to 30 angstroms.
3. The method according to claim 1, characterized in that The physical vapor deposition includes any one of vacuum sputtering deposition and ion plating deposition.
4. The method according to claim 1, characterized in that: The reaction temperature of the atomic layer deposition is 250-350° C., and the reaction precursor is Ta[N(CH3)2]5.
5. The method according to claim 1, characterized in that The reaction temperature of the physical vapor deposition is 25-300°C.
6. The method according to claim 1, characterized in that Step S1 includes: S11, sequentially forming an oxide layer (3), a high-K dielectric layer (4) and a transition layer (5) on a silicon-based substrate (1) comprising an N-type metal gate region and a P-type metal gate region; S12, performing a pseudo polysilicon gate process on the N-type metal gate region and the P-type metal gate region to form a pseudo polysilicon gate; S13, performing a pseudo polysilicon gate removal process on the pseudo polysilicon gate above the transition layer (5) to form a groove for filling a metal gate above the transition layer (5); wherein the groove includes an N-type metal gate groove corresponding to the position of the N-type metal gate region and a P-type metal gate groove corresponding to the position of the P-type metal gate region; Wherein, the tantalum nitride film is formed on the surface of the N-type metal gate trench and the P-type metal gate trench; The material of the oxide layer (3) is SiO2 and / or SiON; the material of the high-K dielectric layer (4) is HfO2; the material of the transition layer (5) is TiN; and the method for removing the pseudo polysilicon gate is dry etching and / or wet etching.
7. The method according to claim 6, characterized in that The method further includes: S3, forming a P-type functional layer (7) on the surface of the dense tantalum nitride layer (6); S4, performing a process of removing a P-type functional layer from the N-type metal gate trench; S5. Forming an N-type functional layer (8), an anti-diffusion layer and a metal gate (11) in sequence on the surface of the semiconductor element obtained in S4.
8. The method according to claim 7, characterized in that The method for removing the P-type functional layer is wet etching and / or dry etching; the etching solution used in the wet etching is SC1 etching solution and / or SC2 etching solution.
9. The method according to claim 7, characterized in that: The material of the P-type functional layer (7) is TiN; the material of the N-type functional layer (8) is TiAl.
10. The method according to claim 7, characterized in that The anti-diffusion layer comprises a first anti-diffusion layer (9) and a second anti-diffusion layer (10); the second anti-diffusion layer (10) is located above the first anti-diffusion layer (9); The material of the first anti-diffusion layer (9) is TiN; The material of the second anti-diffusion layer (10) is Ti.
11. The method according to claim 7, characterized in that The material of the metal gate (11) is Al.
12. The method according to claim 1, characterized in that This method is used in the 28nm and 22nm HKMG processes.