SONOS flash memory tube and preparation method and application thereof

Abstract

The invention provides an SONOS flash memory tube and a preparation method and application thereof. The method comprises the following steps: forming a tunneling silicon dioxide layer on a semiconductor substrate; depositing on a semiconductor substrate with a tunneling silicon dioxide layer, so that a nitride layer is formed on the tunneling silicon dioxide layer; silicon ion implantation is carried out on the semiconductor substrate, so that the nitride layer becomes a silicon-rich nitride layer; depositing and forming a barrier silicon dioxide layer on the silicon-rich nitride layer; and forming a storage tube polysilicon gate on the barrier silicon dioxide layer. According to the method, the nitride layer in the ONO structure is prepared by adopting the atomic layer deposition method, the silicon ions are injected into the nitride layer at the same time, and the number of the silicon ions injected into the nitride layer can be quantified, so that the number of defects in the nitride layer can be quantified and increased, and the electron trapping capability of the nitride layer is improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductors, and in particular, relates to a SONOS flash memory storage tube and a preparation method and application thereof. Background Art

[0002] Flash memory includes floating gate memory, SONOS memory, nanocrystal memory and some new charge trapping memory. When this type of memory is working, the charge enters the gate dielectric from the substrate through the insulating layer by hot injection or tunneling to cause the threshold voltage to change. Flash memory has the characteristics of large storage capacity and long data retention time, many erase and write times, and can save data even in the case of power failure. However, as the size of floating gate memory devices decreases, problems such as over-erasure are becoming more and more serious, and there are also difficulties in integrating with CMOS devices. Therefore, SONOS (Silicon-Oxide-Nitirde-Oxide-Silicon) structure non-volatile memory devices have gradually attracted attention.

[0003] In the SONOS Flash Cell structure, the silicon nitride layer of the ONO structure is used as the storage layer. Studies have found that undoped amorphous silicon nitride has various defects, which have the ability to trap electrons. Therefore, it can be used as the electron storage layer of the SONOS device and is the core layer of the SONOS device. The silicon nitride layer contains H and is doped with O. It is a film layer with a complex structure and full of electron trapping sites. However, since the exact mechanism of electron trapping by the silicon nitride layer is still unclear, the trapping sites in the film layer cannot be accurately characterized. Therefore, the reliability of ONO storage is relatively weak, and the storage number cannot be quantified, which also increases the difficulty of ONO process maintenance and performance improvement. Summary of the invention

[0004] The object of the present invention is to provide a method for preparing a SONOS flash memory storage tube, which can improve the storable quantization performance of the nitride layer in the ONO structure. The present invention also provides a SONOS flash memory storage tube prepared by the method and a SONOS flash memory having the SONOS flash memory storage tube.

[0005] In order to achieve the above object, a first aspect of the present invention provides a method for preparing a SONOS flash memory storage tube, the method comprising the following steps:

[0006] forming a tunneling silicon dioxide layer on a semiconductor substrate;

[0007] Deposition is performed on a semiconductor substrate having a tunneling silicon dioxide layer, so that a nitride layer is formed on the tunneling silicon dioxide layer;

[0008] Performing silicon ion implantation on the semiconductor substrate so that the nitride layer becomes a silicon-rich nitride layer;

[0009] Depositing a barrier silicon dioxide layer on the silicon-rich nitride layer;

[0010] A storage tube polysilicon gate is formed on the barrier silicon dioxide layer.

[0011] Optionally, the conditions for silicon ion implantation include: implantation energy of 0.5-50 keV; implantation dose of 0-5×10 16 atoms / cm 2 ; The injection angle is 0°-35°.

[0012] Optionally, the doping concentration of silicon ions in the silicon-rich nitride layer is 0-5×10 16 atoms / cm 2 .

[0013] Optionally, the silicon-rich nitride layer includes Si x N y , the ratio of x to y is 1:(0.1-3).

[0014] Optionally, a method for depositing the nitride layer includes atomic layer deposition and low-pressure vapor deposition; the thickness of the nitride layer is 1-1000 angstroms.

[0015] Optionally, the conditions for forming a nitride layer by atomic layer deposition include: the reactants include SiH2Cl2 and NH3, the deposition temperature is 300-800°C; the deposition time is 10-120min; the flow ratio of SiH2Cl2 and NH3 is 1:(5-10); the flow rate of SiH2Cl2 is 0.2-1L / min, and the flow rate of NH3 is 1-5L / min.

[0016] Optionally, the method for forming a tunneling silicon dioxide layer comprises performing thermal oxidation treatment on the semiconductor substrate; the conditions of the thermal oxidation treatment comprise: a growth temperature of 0-1300° C.; an oxygen flow rate of 1-20 slm; and a thickness of the tunneling silicon dioxide layer of 1-900 angstroms.

[0017] Optionally, the barrier silicon dioxide layer is formed by atomic layer deposition, and the conditions for forming the barrier silicon dioxide layer include: the reactants include SiH2Cl2 and N2O, the deposition temperature is 400-1000°C; the deposition time is 10-120min; the flow ratio of SiH2Cl2 and N2O is 1:(5-10); the flow rate of SiH2Cl2 is 0.2-1L / min, and the flow rate of N2O is 1-5L / min; the thickness of the barrier silicon dioxide layer is 1-900 angstroms.

[0018] Optionally, the method for forming the polysilicon gate of the storage tube includes thermal growth or CVD deposition; preferably, the conditions for forming the polysilicon gate of the storage tube by CVD deposition include: the silicon source gas is selected from one or more of trimethylsilane, triethylsilane and tetrachlorosilane; preferably, the temperature of the reaction chamber is 400-1000°C; the pressure is 0-80Pa; the flow rate of the silicon source gas is 0.2-5L / min; preferably, the thickness of the polysilicon gate of the storage tube is 1-900 angstroms.

[0019] A second aspect of the present invention provides a SONOS flash memory storage tube, which includes an ONO layer and a polysilicon gate located on the ONO layer; the ONO layer includes a tunneling silicon dioxide layer, a nitride layer and a blocking silicon dioxide layer stacked in sequence; the nitride layer is a silicon nitride layer doped with silicon ions.

[0020] Optionally, the doping concentration of silicon ions in the nitride layer is 0-5×10 16 atoms / cm 2 .

[0021] Optionally, the nitride layer is Si x N y Layer, the ratio of x to y is 1:(0.1-3).

[0022] A third aspect of the present invention provides a SONOS flash memory, which includes the SONOS flash memory tube of the first aspect of the present invention.

[0023] Through the above technical scheme, the present invention prepares the nitride layer in the ONO structure by adopting the atomic layer deposition method, and the atomic stacking in the obtained nitride layer is denser and more uniform; at the same time, the injection of silicon ions into the nitride layer can quantify the number of silicon ions injected into the nitride layer, thereby quantifying and increasing the number of defects in the nitride layer, thereby improving the ability of the nitride layer to capture electrons.

[0024] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present invention but do not constitute a limitation of the present invention. In the accompanying drawings:

[0026] Figure 1 1 is a schematic diagram of the structure of a SONOS flash memory storage tube provided in some embodiments of the present invention.

[0027] Figure 2A schematic flow chart of a method provided for some embodiments of the present invention. DETAILED DESCRIPTION

[0028] The specific embodiments of the present invention are described in detail below. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0029] Research has found that the storage location of charges in the storage layer is mainly the interface state or defect state. The more defect states there are, the stronger the storage performance is. However, it is difficult to quantify the interface state or defect state. In view of this, the present invention is proposed.

[0030] The present invention provides a SONOS flash memory storage tube, referring to Figure 1 The structural schematic diagram of a SONOS flash memory storage tube is shown. The SONOS flash memory storage tube is formed on a substrate 100. The SONOS flash memory storage tube includes an ONO layer and a polysilicon gate 240 located on the ONO layer; the ONO layer includes a tunneling silicon dioxide layer 210, a nitride layer 220 and a blocking silicon dioxide layer 230 stacked in sequence; wherein the nitride layer 220 is a silicon nitride layer doped with silicon ions.

[0031] Combine the following Figure 1 and Figure 2 The SONOS flash memory storage tube provided by the present invention is introduced in detail.

[0032] A first aspect of the present invention provides a method for preparing a SONOS flash memory storage tube, the method 300 comprising the following steps:

[0033] Step 310, forming a tunneling silicon dioxide layer on a semiconductor substrate;

[0034] Step 320, depositing on the semiconductor substrate having the tunneling silicon dioxide layer so that a nitride layer is formed on the tunneling silicon dioxide layer;

[0035] Step 330, implanting silicon ions into the semiconductor substrate to make the nitride layer a silicon-rich nitride layer;

[0036] Step 340, depositing a barrier silicon dioxide layer on the silicon-rich nitride layer;

[0037] Step 350: forming a storage tube polysilicon gate on the blocking silicon dioxide layer.

[0038] In step 310, the semiconductor substrate 100 may be single crystal silicon, polycrystalline silicon, or silicon with an amorphous structure, or may be silicon germanium, silicon on insulator (SOI), or other materials.

[0039] In some embodiments of the present invention, the method for forming a tunneling silicon dioxide layer includes performing a thermal oxygen oxidation treatment on the semiconductor substrate; a tunneling silicon dioxide layer is grown on the semiconductor substrate 100 through a thermal oxygen oxidation process, and the obtained tunneling silicon dioxide layer has a dense structure and a small thickness, which is conducive to electron tunneling into the floating gate (nitride layer).

[0040] In some embodiments of the present invention, the conditions of the thermal oxygen oxidation treatment include: a growth temperature of 0-1300° C. and an oxygen flow rate of 1-20 slm.

[0041] Specifically, the thickness of the tunnel silicon dioxide layer 210 obtained by the thermal oxidation process is 1-900 angstroms.

[0042] In step 320, the method of forming a nitride layer on the tunneling silicon dioxide layer 210 includes atomic layer deposition (ALD) and low pressure chemical vapor deposition (LPCVD). Both methods can form a nitride layer on the tunneling silicon dioxide layer. Due to the difference between the two deposition methods, the nitride layer formed by atomic layer deposition is more dense and uniform. Therefore, as a preferred embodiment, the nitride layer is formed by atomic layer deposition.

[0043] In some embodiments of the present invention, the conditions for forming a nitride layer by atomic layer deposition include: the reactants include SiH2Cl2 and NH3, and the flow ratio of SiH2Cl2 and NH3 is 1:(5-10); preferably, the flow rate of SiH2Cl2 is 0.2-1L / min, and the flow rate of NH3 is 1-5L / min. In some embodiments of the present invention, the Si / N of the nitride layer is constant, and a nitride layer with non-constant Si / N can also be formed by changing the flow rates of SiH2Cl2 and NH3 during the preparation process. For example, a silicon-rich nitride layer that occupies a certain thickness ratio of the nitride layer is formed in some parts close to the tunneling silicon dioxide layer, and then a nitrogen-rich nitride layer is formed in the part close to the blocking silicon dioxide.

[0044] Specifically, the deposition temperature is 300-800°C and the deposition time is 10-120 minutes. Thus, a smooth atomic interface is formed between the tunneling silicon dioxide layer 210 and the nitride layer 220. Compared with the nitride layer prepared by the LPCVD method, the atomic stacking in the nitride layer obtained by atomic layer deposition is more dense, the quality and uniformity of the nitride layer are higher, and the quality of the ONO structure is improved.

[0045] In some specific embodiments of the present invention, the thickness of the nitride layer 220 is 1-1000 angstroms.

[0046] By injecting silicon ions into the nitride layer, the nitride layer is enriched with silicon ions, and the energy band for capturing electrons is reduced, thereby increasing the ability to capture electrons. In some embodiments of the present invention, the conditions for silicon ion implantation in step 330 include: an implantation energy of 0.5-50 keV; an implantation dose of 0-5×10 16 atoms / cm 2 .

[0047] The injection energy of silicon ions in the nitride layer needs to be appropriate. If the energy of silicon ion injection is too small, it will be difficult to inject silicon ions into the nitride layer, resulting in insufficient injection depth and failure to achieve the effect of increasing the trapped electron defects. If the injection energy is too large, the silicon ion injection depth will be too deep, which is not conducive to forming uniform capture sites in the nitride layer. Therefore, the injection energy is 0.5-50keV.

[0048] Similarly, a reasonable injection dose of silicon ions in the nitride layer needs to be set. Too low a dose will result in a low silicon ion content in the nitride layer and few additional capture sites; too high a dose may cause leakage problems in the nitride layer due to excessive silicon ion doping concentration.

[0049] In order to ensure that silicon ions can be implanted into the nitride layer, preferably, the implantation angle may be 0°-35°, that is, the angle between the implantation direction and the normal line of the semiconductor substrate is 0°-35°.

[0050] In the present invention, the nitride layer in the ONO structure is prepared by adopting the atomic layer deposition method, and the atomic stacking in the obtained nitride layer is denser and more uniform; at the same time, the injection of silicon ions into the nitride layer can quantify the number of silicon ions injected into the nitride layer, thereby quantifying and increasing the number of defects in the nitride layer, thereby improving the ability of the nitride layer to capture electrons.

[0051] Specifically, the silicon source used for silicon ion implantation may be silicon.

[0052] Specifically, by implanting silicon ions, the doping concentration of silicon ions in the silicon-rich nitride layer is 0-5×10 16 atoms / cm 2 .

[0053] Specifically, the silicon-rich nitride layer includes Si x N y , the ratio of x to y is 1:(0.1-3). Generally, the nitride layer formed by atomic layer deposition is silicon nitride (Si3N4). By injecting silicon ions into the nitride layer, the ratio of silicon and nitrogen in the silicon-rich nitride layer changes, with Si x N yRepresents the ratio of silicon to nitrogen in the silicon-rich nitride layer. Specifically, the ratio of x to y can be 1:0.1, 1:0.2, 1:0.4, 1:0.6, 1:0.8, 1:1, 1:1.33. At the same time, the ratio of x to y can also be changed by changing the doping concentration of silicon ions in the nitride layer. For example, when silicon ions are not injected, the ratio of x to y is 3:4. After silicon ions are injected into the nitride layer, the value of x gradually increases. For example, Si x N y It can be Si4N4, Si5N4, Si6N4. After silicon ions are injected into the nitride layer, the original stable structure of Si3N4 changes, thereby generating defects that can capture electrons, thereby improving the performance of the ONO layer.

[0054] In step 340, the blocking silicon dioxide layer is formed by atomic layer deposition, and the thickness of the blocking silicon dioxide layer is relatively large to prevent electrons from entering the floating gate and then tunneling to the polysilicon gate. Specifically, the conditions for forming the blocking silicon dioxide layer include: the reactants include SiH2Cl2 and N2O, the flow ratio of SiH2Cl2 and N2O is 1: (5-10); the flow rate of SiH2Cl2 is 0.2-1L / min, and the flow rate of N2O is 1-5L / min.

[0055] In some embodiments of the present invention, the deposition temperature for forming the barrier silicon dioxide layer is 400-1000° C. and the deposition time is 10-120 min.

[0056] In some specific embodiments of the present invention, the thickness of the barrier silicon dioxide layer is 1-900 angstroms.

[0057] In step 350, the method for forming the polysilicon gate of the storage tube includes thermal growth or CVD deposition; preferably, the conditions for CVD deposition to form the polysilicon gate of the storage tube include: the silicon source gas is selected from one or more of trimethylsilane, triethylsilane and tetrachlorosilane; the temperature of the reaction chamber is 400-1000°C; the pressure is 0-80Pa; the flow rate of the silicon source gas is 0.2-5L / min.

[0058] In some preferred embodiments of the present invention, the thickness of the polysilicon gate of the storage tube is 1-900 angstroms.

[0059] A third aspect of the present invention provides a SONOS flash memory, which includes the aforementioned SONOS flash memory tube.

[0060] Specifically, the SONOS flash memory further includes a selection tube, and the selection tube includes a medium-voltage oxide layer and a selection tube polysilicon gate.

[0061] Furthermore, an oxide layer and a silicon nitride layer are formed on the surfaces of the storage tube polysilicon gate and the selection tube polysilicon gate, and silicon nitride sidewalls are formed on both sides of the storage tube polysilicon gate and the selection tube polysilicon gate.

[0062] The present invention is further described in detail below by way of examples, but the present invention is not limited to the following examples.

[0063] Example 1

[0064] The method for preparing a SONOS flash memory storage tube in this embodiment includes the following steps:

[0065] (1) Cleaning the semiconductor substrate to remove impurities and organic matter; performing thermal oxidation treatment on the semiconductor substrate to form a tunneling silicon dioxide layer on the semiconductor substrate; wherein the semiconductor substrate is a p-type single crystal silicon substrate; the conditions of the thermal oxidation treatment include: a growth temperature of 1300° C., an oxygen flow rate of 20 slm, and a thickness of the tunneling silicon dioxide layer 210 of 600 angstroms.

[0066] (2) Atomic layer deposition is performed on a semiconductor substrate having a tunneling silicon dioxide layer, so that a nitride layer is formed on the tunneling silicon dioxide layer; wherein the conditions for the atomic layer deposition include: reactants include SiH2Cl2 and NH3, and the flow ratio of SiH2Cl2 to NH3 is 1:5; the flow rate of SiH2Cl2 is 0.2 L / min, and the flow rate of NH3 is 1 L / min; and the thickness of the nitride layer is 800 angstroms.

[0067] (3) implanting silicon ions into the semiconductor substrate so that the nitride layer becomes a silicon-rich nitride layer; wherein the silicon source for implanting silicon ions is silicon; the conditions for implanting silicon ions include: an implantation energy of 30 keV; an implantation dose of 2.5×10 16 atoms / cm 2 ; The implantation angle is 0°. The doping concentration of silicon ions in the nitride layer is 2.5×10 16 atoms / cm 2 .

[0068] (4) depositing a barrier silicon dioxide layer on the silicon-rich nitride layer; wherein the conditions for forming the barrier silicon dioxide layer by atomic layer deposition include: reactants include SiH2Cl2 and N2O, the flow ratio of SiH2Cl2 to N2O is 1:5; the flow rate of SiH2Cl2 is 0.2 L / min, and the flow rate of N2O is 1 L / min; the deposition temperature is 400°C; and the deposition time is 10 min. The thickness of the barrier silicon dioxide layer is 600 angstroms.

[0069] (5) forming a storage tube polysilicon gate on the barrier silicon dioxide layer; wherein the conditions include: the silicon source gas is trimethylsilane; the temperature of the reaction chamber is 600° C.; the pressure is 50 Pa; and the flow rate of the silicon source gas is 1 L / min.

[0070] After performing a read operation on the storage unit of the SONOS flash memory storage tube of the above embodiment, it is found that the storage unit has good stability; since the nitride layer of the ONO layer is doped with silicon ions, these silicon ions form a defect structure in the silicon nitride layer, forming a deep electron trap energy level, which can effectively capture electrons and improve the compilation and erasure speed of the SONOS device.

[0071] At the same time, by changing the conditions during silicon ion implantation, the doping concentration of silicon ions injected into the silicon nitride layer can be quantified, thereby quantifying the storage number in the ONO storage layer, thereby improving the storage quantification performance of the nitride layer in the ONO structure.

[0072] The preferred embodiments of the present invention are described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.

[0073] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

[0074] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims

1. A method for preparing a SONOS flash memory storage tube, characterized in that: The method comprises the following steps: forming a tunneling silicon dioxide layer on a semiconductor substrate; Deposition is performed on a semiconductor substrate having a tunneling silicon dioxide layer, so that a nitride layer is formed on the tunneling silicon dioxide layer; Performing silicon ion implantation on the semiconductor substrate so that the nitride layer becomes a silicon-rich nitride layer; Depositing a barrier silicon dioxide layer on the silicon-rich nitride layer; A storage tube polysilicon gate is formed on the barrier silicon dioxide layer.

2. The method according to claim 1, wherein: The conditions for silicon ion implantation include: implantation energy of 0.5-50keV; implantation dose of 0-5×10 16 atoms / cm 2 ; The injection angle is 0°-35°.

3. The method according to claim 1, wherein: The doping concentration of silicon ions in the silicon-rich nitride layer is 0-5×10 16 atoms / cm 2 .

4. The method according to claim 1, wherein: The silicon-rich nitride layer includes Si x N y , the ratio of x to y is 1:(0.1-3).

5. The method according to claim 1, wherein: The method of depositing the nitride layer includes atomic layer deposition and low pressure vapor deposition; The thickness of the nitride layer is 1-1000 angstroms.

6. The method according to claim 5, wherein: The conditions for forming a nitride layer by atomic layer deposition include: the reactants include SiH2Cl2 and NH3, the deposition temperature is 300-800°C; the deposition time is 10-120min; the flow ratio of SiH2Cl2 and NH3 is 1:(5-10); the flow rate of SiH2Cl2 is 0.2-1L / min, and the flow rate of NH3 is 1-5L / min.

7. The method according to claim 1, wherein: The method for forming a tunneling silicon dioxide layer comprises performing a thermal oxidation treatment on the semiconductor substrate; the conditions of the thermal oxidation treatment comprise: a growth temperature of 0-1300° C.; an oxygen flow rate of 1-20 slm; The thickness of the tunneling silicon dioxide layer is 1-900 angstroms.

8. The method according to claim 1, wherein: Forming the barrier silicon dioxide layer by atomic layer deposition; The conditions for forming the barrier silicon dioxide layer include: The reactants include SiH2Cl2 and N2O, the deposition temperature is 400-1000°C; the deposition time is 10-120min; the flow ratio of SiH2Cl2 and N2O is 1:(5-10); the flow rate of SiH2Cl2 is 0.2-1L / min, and the flow rate of N2O is 1-5L / min; The thickness of the barrier silicon dioxide layer is 1-900 angstroms.

9. The method according to claim 1, wherein: The method of forming the polysilicon gate of the storage tube includes thermal growth or CVD deposition; Preferably, the conditions for forming the polysilicon gate of the storage tube by CVD deposition include: the silicon source gas is selected from one or more of trimethylsilane, triethylsilane and tetrachlorosilane; Preferably, the temperature of the reaction chamber is 400-1000°C; the pressure is 0-80Pa; the flow rate of the silicon source gas is 0.2-5L / min; Preferably, the thickness of the polysilicon gate of the storage tube is 1-900 angstroms.

10. A SONOS flash memory storage tube, characterized in that: The SONOS flash memory storage tube comprises an ONO layer and a polysilicon gate located on the ONO layer; the ONO layer comprises a tunneling silicon dioxide layer, a nitride layer and a blocking silicon dioxide layer stacked in sequence; the nitride layer is a silicon nitride layer doped with silicon ions.

11. The SONOS flash memory storage tube according to claim 10, wherein: The doping concentration of silicon ions in the nitride layer is 0-5×10 16 atoms / cm 2 .

12. The SONOS flash memory storage tube according to claim 10, wherein: The nitride layer is Si x N y Layer, the ratio of x to y is 1:(0.1-3).

13. A SONOS flash memory, characterized in that: The SONOS flash memory comprises a SONOS flash memory tube prepared by the method according to any one of claims 1 to 9.

Images