A trench gate DMOS device with asymmetric channel

Abstract

This invention belongs to the field of power semiconductor technology and relates to a trench-gate DMOS device with an asymmetric channel. Its cell structure includes a metallized drain, a heavily doped first conductivity type semiconductor substrate above the metallized drain, a lightly doped first conductivity type semiconductor epitaxial layer above the first conductivity type semiconductor substrate, and a second conductivity type semiconductor body region above the lightly doped first conductivity type semiconductor epitaxial layer. By employing an asymmetric structure, this invention forms a vertical channel on one side of the polysilicon gate and an L-shaped channel on the other side, resulting in a longer channel region for carrier flow. This increases the influence of mobility on the drain current temperature coefficient, allowing the device to enter the negative temperature characteristic range of current earlier and lowering the zero-temperature point of the drain current. Furthermore, the channel resistance of the device can be changed by adjusting the ratio of the L-shaped channel to the vertical channel.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device technology, and specifically to a trench gate DMOS device with an asymmetric channel. Background Technology

[0002] Power semiconductor devices are semiconductor devices used for power processing. They combine microelectronics and power electronics technologies, forming the foundation and core of power electronics technology. Power DMOS devices play a crucial role in power conversion due to their advantages such as fast switching speed, high input impedance, low loss, simple driving, and good frequency characteristics. Their development has been a process of continuously improving voltage withstand and reducing losses while maintaining their inherent advantages. Traditional DMOS devices are planar structures using a double-diffusion process. This was the first commercially successful power DMOS, playing a key role in its development. However, the presence of the internal JFET region resulted in a relatively high on-resistance, which was undesirable for power device development. This provided an opportunity for the development of trench-gate power devices. Trench-gate DMOS devices employ a U-shaped trench structure with a longitudinal conductive channel, high cell density, and large current handling capacity. Because their structure eliminates the JFET region, resulting in lower on-resistance, they have been widely adopted in low-voltage applications.

[0003] In low-voltage and ultra-low-voltage applications, with the continuous development and optimization of processes in recent years, the problems caused by the low-current temperature instability of power DMOS have gradually become apparent. DMOS devices exhibit a negative temperature characteristic (TTC) under high current conditions and a positive TTC under low current conditions. This is because the temperature characteristic of mobility dominates under high current, while the temperature characteristic of threshold voltage dominates under low current. When the temperature characteristics of mobility and threshold voltage have opposite effects on the current, their effects cancel each other out, reaching a point where the current reaches zero temperature, i.e., the device's zero-temperature point. The DMOS exhibits a positive TTC when the drain current is below zero temperature and a negative TTC when it is above zero temperature. Since the positive TTC of the drain current can cause device failure or even burnout, it is desirable to minimize the zero-temperature point of the device to improve its thermal stability. Summary of the Invention

[0004] The purpose of this invention is to address the above-mentioned problems by providing a trench gate DMOS device that improves stability under low current conditions, achieves a lower zero temperature point, allows the device to enter the negative temperature characteristic region of current earlier, and improves the stability of low-voltage DMOS under low current conditions.

[0005] To achieve the above-mentioned objectives, the technical solution of this invention is as follows:

[0006] A trench gate DMOS device with an asymmetric channel has a cell structure comprising a metallized drain 1, a heavily doped first conductivity type semiconductor substrate 2 located above the metallized drain 1, a lightly doped first conductivity type semiconductor lightly doped epitaxial layer 3 located above the first conductivity type semiconductor substrate 2, and a second conductivity type semiconductor body region 4 located above the lightly doped first conductivity type semiconductor lightly doped epitaxial layer 3.

[0007] The top of the lightly doped first conductivity type semiconductor lightly doped epitaxial layer 3 has a trench, the lower surface of the trench is lower than the lower surface of the second conductivity type semiconductor body region 4, and the second conductivity type semiconductor body region 4 is provided with two polysilicon gate electrodes 13, which are L-shaped and include a vertical segment located on the side of the second conductivity type semiconductor body region 4 and a horizontal segment located above the second conductivity type semiconductor body region 4.

[0008] The polysilicon gate electrode 13 on the left is isolated from the second conductivity type semiconductor body region 4 through the second gate oxide layer 11; the polysilicon gate electrode 13 on the right is isolated from the second conductivity type semiconductor body region 4 through the first gate oxide layer 10.

[0009] The semiconductor region where the first gate oxide layer 10 contacts the right-side second conductivity type semiconductor body region 4 is the first channel region 5; the semiconductor region where the second gate oxide layer 11 contacts the left-side second conductivity type semiconductor body region 4 is the second channel region 6; the top of the second conductivity type semiconductor body region 4 has a first conductivity type semiconductor heavily doped source region I7, a first conductivity type semiconductor heavily doped source region II9, and a second conductivity type semiconductor heavily doped contact region 8 between the two polysilicon gate electrodes 13; the side of the first conductivity type semiconductor heavily doped source region I7 is in direct contact with the first channel region 5; the side of the first conductivity type semiconductor heavily doped source region II9 and the second channel region 5 are in direct contact. Channel 6 is in direct contact; metal via 14 is located above the second type of semiconductor heavily doped contact region 8 and the first type of semiconductor heavily doped source region II9. The second type of semiconductor heavily doped contact region 8, the first type of semiconductor heavily doped source region I7, and the first type of semiconductor heavily doped source region II9 are in contact with the metallized source 15 located on the upper surface of the device through the metal via 14 above; the polysilicon gate electrode 13 is isolated from the metallized source 15, the metal via 14, the first type of semiconductor heavily doped source region I7, the first type of semiconductor heavily doped source region II9, and the lightly doped first type of semiconductor lightly doped epitaxial layer 3 through the oxide layer 12;

[0010] As a preferred embodiment, the device consists of several cells with L-shaped polysilicon gate electrodes 13 and several conventional trench gate MOSFET cells, the proportion of which can be adjusted.

[0011] As a preferred method, the heavy doping concentration is 1E18cm⁻¹. -3 -1E19cm -3 The lightly doped concentration is 1E15cm. -3 -1E16cm -3 .

[0012] As a preferred approach, the silicon material in the device is replaced with silicon carbide, gallium arsenide, indium phosphide, or germanium silicon semiconductor material.

[0013] The beneficial effects of this invention are as follows: This invention adopts an asymmetric structure, forming a vertical channel on one side of the polysilicon gate and an L-shaped channel on the other side. The first channel region 5 of the L-shape consists of a lateral region and a longitudinal region, resulting in a longer channel region through which charge carriers flow. This increases the influence of mobility on the drain current temperature coefficient, thereby enabling the device to enter the negative temperature characteristic range of current earlier and reducing the drain current I corresponding to the zero temperature point of the device drain current. D * To improve the reliability of low-voltage DMOS under low current, such as Figure 2 and Figure 3 As shown. Simultaneously, the ratio of the L-shaped channel to the vertical channel can be adjusted to change the channel resistance of the device and thus adjust the on-resistance. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a trench gate DMOS device structure with an asymmetric channel according to Embodiment 1 of the present invention;

[0015] Figure 2 The transfer characteristic curves at different temperatures and the drain current I corresponding to the zero temperature point in Embodiment 1 of the present invention are shown. D * Indication;

[0016] Figure 3 The channel length of Embodiment 1 of the present invention is 1 / I D * The relationship.

[0017] 1 is a metallized drain, 2 is a heavily doped first conductivity type semiconductor substrate, 3 is a lightly doped first conductivity type semiconductor lightly doped epitaxial layer, 4 is a second conductivity type semiconductor body region, 5 is a first channel region, 6 is a second channel region, 7 is a first conductivity type semiconductor heavily doped source region I, 8 is a second conductivity type semiconductor heavily doped contact region, 9 is a first conductivity type semiconductor heavily doped source region II, 10 is a first gate oxide layer, 11 is a second gate oxide layer, 12 is an oxide layer, 13 is a polysilicon gate electrode, 14 is a metal via, and 15 is a metallized source. Detailed Implementation

[0018] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0019] Example 1

[0020] like Figure 1 As shown, this embodiment provides a trench gate DMOS device with an asymmetric channel, whose cell structure includes a metallized drain 1, a heavily doped first conductivity type semiconductor substrate 2 located on the metallized drain 1, a lightly doped first conductivity type semiconductor lightly doped epitaxial layer 3 located on the first conductivity type semiconductor substrate 2, and a second conductivity type semiconductor body region 4 located on the lightly doped first conductivity type semiconductor lightly doped epitaxial layer 3.

[0021] The top of the lightly doped first conductivity type semiconductor lightly doped epitaxial layer 3 has a trench, the lower surface of the trench is lower than the lower surface of the second conductivity type semiconductor body region 4, and the second conductivity type semiconductor body region 4 is provided with two polysilicon gate electrodes 13, which are L-shaped and include a vertical segment located on the side of the second conductivity type semiconductor body region 4 and a horizontal segment located above the second conductivity type semiconductor body region 4.

[0022] The polysilicon gate electrode 13 on the left is isolated from the second conductivity type semiconductor body region 4 through the second gate oxide layer 11; the polysilicon gate electrode 13 on the right is isolated from the second conductivity type semiconductor body region 4 through the first gate oxide layer 10.

[0023] The semiconductor region where the first gate oxide layer 10 contacts the right-side second conductivity type semiconductor body region 4 is the first channel region 5; the semiconductor region where the second gate oxide layer 11 contacts the left-side second conductivity type semiconductor body region 4 is the second channel region 6; the top of the second conductivity type semiconductor body region 4 has a first conductivity type semiconductor heavily doped source region I7, a first conductivity type semiconductor heavily doped source region II9, and a second conductivity type semiconductor heavily doped contact region 8 between the two polysilicon gate electrodes 13; the side of the first conductivity type semiconductor heavily doped source region I7 is in direct contact with the first channel region 5; the side of the first conductivity type semiconductor heavily doped source region II9 and the second channel region 5 are in direct contact. Channel 6 is in direct contact; metal via 14 is located above the second type of semiconductor heavily doped contact region 8 and the first type of semiconductor heavily doped source region II9. The second type of semiconductor heavily doped contact region 8, the first type of semiconductor heavily doped source region I7, and the first type of semiconductor heavily doped source region II9 are in contact with the metallized source 15 located on the upper surface of the device through the metal via 14 above; the polysilicon gate electrode 13 is isolated from the metallized source 15, the metal via 14, the first type of semiconductor heavily doped source region I7, the first type of semiconductor heavily doped source region II9, and the lightly doped first type of semiconductor lightly doped epitaxial layer 3 through the oxide layer 12;

[0024] The device consists of several cells with L-shaped polysilicon gate electrodes 13 and several conventional trench gate MOSFET cells, the ratio of which can be adjusted.

[0025] The heavy doping concentration is 1E18cm. -3 -1E19cm -3 The lightly doped concentration is 1E15cm. -3 -1E16cm -3 .

[0026] The silicon material in the device is replaced with silicon carbide, gallium arsenide, indium phosphide, or germanium silicon semiconductor materials.

[0027] The working principle of the present invention will be explained using Example 1 as an example.

[0028] DMOS devices exhibit a negative temperature characteristic (TTC) under high current conditions and a positive TTC under low current conditions. This is because the temperature characteristic of mobility dominates at high currents, while the temperature characteristic of the threshold voltage dominates at low currents. When the temperature characteristics of mobility and threshold voltage have opposite effects on the current, their effects cancel each other out, reaching a point where the current reaches zero temperature, i.e., the device's zero-temperature point. A DMOS device exhibits a positive TTC when its drain current is below zero temperature and a negative TTC when it is above zero temperature. Since a positive TTC of drain current can cause device failure or even burnout, a lower zero-temperature point is desirable for better thermal stability.

[0029] Taking an N-type semiconductor as an example, in this invention, when the polysilicon gate electrode 13 is at a high potential, a first channel region 5 is formed below the first gate oxide layer 10 and on the sidewall. The "L"-shaped first channel region 5 consists of a lateral region and a longitudinal region, and the channel region through which the charge carriers flow is longer. Therefore, the influence of mobility on the drain current will be significantly increased, thereby lowering the zero-temperature point. The device can enter the negative current temperature characteristic region earlier, improving the stability of the DMOS under low current. Figure 2 and Figure 3 As shown. Simultaneously, the ratio of the first channel region 5 and the second channel region 6 of the "L" shape can be adjusted to change the channel resistance of the device and thus adjust the on-resistance.

[0030] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A trench-gate DMOS device with an asymmetric channel, characterized in that: Its cell structure includes a metallized drain (1), a heavily doped first conductivity type semiconductor substrate (2) located above the metallized drain (1), a lightly doped first conductivity type semiconductor lightly doped epitaxial layer (3) located above the first conductivity type semiconductor substrate (2), and a second conductivity type semiconductor body region (4) located above the lightly doped first conductivity type semiconductor lightly doped epitaxial layer (3); The top of the lightly doped first conductivity type semiconductor lightly doped epitaxial layer (3) has a trench, the lower surface of the trench is lower than the lower surface of the second conductivity type semiconductor body region (4), and the second conductivity type semiconductor body region (4) is provided with two polysilicon gate electrodes (13) on the left and right sides. The polysilicon gate electrodes (13) are L-shaped and include a vertical segment located on the side of the second conductivity type semiconductor body region (4) and a horizontal segment located above the second conductivity type semiconductor body region (4). The polysilicon gate electrode (13) on the left is isolated from the second conductivity type semiconductor body region (4) through the second gate oxide layer (11); the polysilicon gate electrode (13) on the right is isolated from the second conductivity type semiconductor body region (4) through the first gate oxide layer (10); The semiconductor region in contact between the first gate oxide layer (10) and the second conductivity type semiconductor body region (4) on the right is the first channel region (5); the semiconductor region in contact between the second gate oxide layer (11) and the second conductivity type semiconductor body region (4) on the left is the second channel region (6); the top of the second conductivity type semiconductor body region (4) has a first conductivity type semiconductor heavily doped source region I (7), a first conductivity type semiconductor heavily doped source region II (9), and a second conductivity type semiconductor heavily doped contact region (8) between the two polysilicon gate electrodes (13); the side of the first conductivity type semiconductor heavily doped source region I (7) is in direct contact with the first channel region (5); the first conductivity type semiconductor heavily doped source region II (9) is in direct contact with the side and the second channel region (6); the metal via (14) is located above the second conductivity type semiconductor heavily doped contact region (8) and the first conductivity type semiconductor heavily doped source region II (9), and the second conductivity type semiconductor heavily doped contact region (8), the first conductivity type semiconductor heavily doped source region I (7), and the first conductivity type semiconductor heavily doped source region II (9) are in contact with the metallized source electrode (15) located on the upper surface of the device through the metal via (14); the polysilicon gate electrode (13) is isolated from the metallized source electrode (15), the metal via (14), the first conductivity type semiconductor heavily doped source region I (7), the first conductivity type semiconductor heavily doped source region II (9), and the lightly doped first conductivity type semiconductor lightly doped epitaxial layer (3) through the oxide layer (12).

2. A trench-gate DMOS device with an asymmetric channel according to claim 1, characterized in that: The device consists of several cells with L-shaped polysilicon gate electrodes (13) and several conventional trench gate MOSFET cells, the proportion of which can be adjusted.

3. A trench-gate DMOS device with an asymmetric channel according to claim 1, characterized in that: The heavy doping concentration is 1E18cm. -3 -1E19cm -3 The lightly doped concentration is 1E15cm. -3 -1E16cm -3 .

4. A trench-gate DMOS device with an asymmetric channel according to claim 1, characterized in that: The polycrystalline silicon material in the device is replaced with silicon carbide, gallium arsenide, indium phosphide, or germanium silicon semiconductor materials.

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