Groove etching method
By forming grooves in overlapping areas on the substrate, the problem of low applicability of the negative development process in the prior art is solved, and precise lithography of small-sized grooves is achieved and manufacturing costs are reduced.
Patent Information
- Application Number
- CN202510213962.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-25
- Publication Date
- 2025-05-16
AI Technical Summary
In the prior art, the application of forming dark field patterns through negative development processes is low and the manufacturing cost is high.
By sequentially forming the first hard mask layer and the second hard mask layer on the substrate, two lithography processes are performed to form grooves in overlapping areas, thereby achieving accurate lithography of small-sized grooves.
The problem of low applicability of the formation of small-sized patterns in negative development processes is solved, which reduces manufacturing costs and realizes accurate lithography of small-sized grooves.
Smart Images
Figure CN120015617A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor devices and integrated circuits, and in particular to a groove etching method. Background Art
[0002] In the semiconductor manufacturing industry, when the area occupied by the pattern that needs to be transferred from the mask to the substrate during exposure is relatively small in the entire region (that is, most of the area in this exposure is non-exposure area, and the pattern that needs to be exposed is an isolated pattern, and its actual area ratio is defined according to the process conditions in the actual implementation. For example, it can be a pattern with an area ratio of less than 20%), the pattern is called a dark field pattern.
[0003] Since the effective amount of light entering the dark field pattern is low, its formation is severely restricted by the amount of light entering the pattern. In view of this, in the related art, the dark field pattern can be formed by a negative tone development (NTD) process. That is, the other areas of the non-dark field pattern in this exposure are exposed, and the dark field pattern that is not exposed is developed and removed in the negative development process, and the other exposed areas are retained, thereby achieving precise lithography of the dark field pattern. However, since the mainstream developing machine in the current semiconductor manufacturing process is a positive developing machine, the applicability of using the negative development process to form a dark field pattern is low, and the manufacturing cost is high. Summary of the invention
[0004] The present application provides a groove etching method, which can solve the problems of low applicability and high manufacturing cost caused by etching dark field patterns through negative development process provided in the related art. The method comprises:
[0005] Providing a substrate, wherein a first hard mask layer is formed on the substrate, a second hard mask layer is formed on the first hard mask layer, and the first hard mask layer and the second hard mask layer are formed of different materials;
[0006] Covering the second hard mask layer with photoresist, exposing through the first mask, and removing the photoresist in the first target area after development;
[0007] Performing etching until the first hard mask layer in the first target area is exposed, forming a first groove in the second hard mask layer, and then removing the photoresist;
[0008] Covering the second hard mask layer with a photoresist, exposing through the second hard mask layer, and removing the photoresist in the second target area after development, wherein the second target area and the first target area have an overlapping area when viewed from a top view;
[0009] Performing etching until the substrate in the overlapping area is exposed, and forming a second groove in the first hard mask layer, wherein the second groove is located below the first groove and has a width smaller than that of the first groove;
[0010] Etching is performed to form a third groove in the substrate below the second groove.
[0011] In some embodiments, a ratio of an area of the overlapping region to an area of the substrate is less than 20%.
[0012] In some embodiments, the first target area and the second target area are the same shape and size.
[0013] In some embodiments, the second target area is offset relative to the first target area by less than 40 nanometers.
[0014] In some embodiments, a ratio of the depth to the width of the third groove is greater than 10.
[0015] In some embodiments, the etching is performed until the substrate in the overlapping region is exposed to form a second groove in the first hard mask layer, comprising:
[0016] The second groove is formed in the first hard mask layer by etching through a wet etching process.
[0017] In some embodiments, the first hard mask layer includes a silicon dioxide layer, and the second hard mask layer includes a silicon nitride layer.
[0018] The technical solution of this application has at least the following advantages:
[0019] A first hard mask layer and a second hard mask layer are formed on a substrate in sequence, a first groove is formed in the second hard mask layer by a first photolithography, and a second groove is formed in the first hard mask layer by a second photolithography, wherein the second groove is located below the first groove and the width of the second groove is smaller than the width of the first groove, and then a third groove is formed by etching in the substrate below the second groove. Since the second groove and the third groove are overlapping areas of the exposure areas in the two photolithography processes, precise photolithography for small-sized grooves is achieved, thereby solving the problem of low applicability caused by the need to form small-sized graphics through a negative development process in the related technology, and reducing the manufacturing cost to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0021] Figure 1 is a flow chart of a groove etching method provided by an exemplary embodiment of the present application;
[0022] Figures 2 to 7 It is a schematic diagram of the etching process of a groove etching method provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION
[0023] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0024] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0025] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0026] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0027] refer to Figure 1, which shows a flow chart of a groove etching method provided by an exemplary embodiment of the present application, such as Figure 1 As shown, the method includes:
[0028] Step S1, providing a substrate, a first hard mask layer is formed on the substrate, a second hard mask layer is formed on the first hard mask layer, and the first hard mask layer and the second hard mask layer are made of different materials.
[0029] refer to Figure 2 , which shows a cross-sectional schematic diagram of a substrate having a first hard mask layer and a second hard mask layer formed thereon. Figure 2 As shown, a first hard mask (HM) layer 221 is formed on the substrate 210, and a second hard mask layer 222 is formed on the first hard mask layer 221. The first hard mask layer 221 and the second hard mask layer 222 are made of different materials. For example, the first hard mask layer 221 may include a silicon dioxide (SiO2) layer, and the second hard mask layer 222 may include a silicon nitride (Si3N4) layer.
[0030] Step S2, covering the second hard mask layer with photoresist, exposing through the first mask plate, and removing the photoresist in the first target area after development.
[0031] refer to Figure 3 , which shows a cross-sectional schematic diagram after the first photolithography. Figure 3 As shown, the photoresist 301 is covered on the second hard mask layer 222 , and is exposed through a first mask plate, and the photoresist 301 in the first target area 401 is removed after development.
[0032] Step S3, performing etching until the first hard mask layer in the first target area is exposed, forming a first groove in the second hard mask layer, and then removing the photoresist.
[0033] refer to Figure 4 , which shows a cross-sectional schematic diagram after etching to form a first groove. Figure 4 As shown, a dry etching process may be used to form a first groove 501 in the first groove 222 in the second hard mask layer, and then the photoresist 301 may be removed.
[0034] Step S4, covering the second hard mask layer with photoresist, exposing through the second hard mask layer, and removing the photoresist in the second target area after development. When viewed from a top view, the second target area has an overlapping area with the first target area.
[0035] refer to Figure 5 , which shows a cross-sectional schematic diagram after the second photolithography. Figure 5As shown, the photoresist 302 is covered on the second hard mask layer 222 , and exposure is performed through the second hard mask layer. After development, the photoresist 302 in the second target area 402 is removed.
[0036] When designing the first mask and the second mask, the first light-transmitting pattern on the first mask (the pattern corresponding to the first target area 401) and the second light-transmitting pattern on the second mask (the pattern corresponding to the second target area 402) can be patterns with the same shape and size (i.e., when viewed from a top view, the first target area 401 and the second target area 402 have the same shape and size), except that the second light-transmitting pattern has a certain offset relative to the first light-transmitting pattern, and the offset is less than 40 nanometers (i.e., when viewed from a top view, the offset of the second target area 402 relative to the first target area 401 is less than 40 nanometers), so that the first target area 401 and the second target area 402 have an overlapping area, which is the area corresponding to the groove that needs to be etched in the embodiment of the present application. Therefore, the width of the first light-transmitting pattern and the second light-transmitting pattern can be designed to be greater than the target width (the width of the groove that needs to be etched), and the ratio of the area of the overlapping area to the area of the substrate 210 is less than 20%, that is, the pattern corresponding to the overlapping area is a dark field pattern.
[0037] Step S5, performing etching until the substrate in the overlapping area is exposed, and forming a second groove in the first hard mask layer, wherein the second groove is located below the first groove and the width of the second groove is smaller than the width of the first groove.
[0038] refer to Figure 6 , which shows a cross-sectional schematic diagram after etching to form the second groove. Figure 6 As shown, a wet etching process can be used to form a second groove 502 in the first hard mask layer 221, thereby removing the photoresist 302. The area occupied by the second groove 502 is the overlapping area of the first target area 401 and the second target area 402.
[0039] Step S6, performing etching to form a third groove in the substrate below the second groove.
[0040] refer to Figure 7 , which shows a cross-sectional schematic diagram after the third groove is formed. Figure 7 As shown, the first hard mask layer 221 can be used as a mask and a dry etching process can be used to form a third groove 503 in the substrate 210. The third groove 503 is the groove that needs to be etched in the embodiment of the present application. The ratio of the depth H to the width W of the third groove 503 is greater than 10.
[0041] To summarize, in the embodiments of the present application, a first hard mask layer and a second hard mask layer are sequentially formed on a substrate, a first groove is formed in the second hard mask layer by a first photolithography, and a second groove is formed in the first hard mask layer by a second photolithography, the second groove is located below the first groove and the width of the second groove is smaller than the width of the first groove, and then a third groove is formed by etching in the substrate below the second groove. Since the second groove and the third groove are overlapping areas of the exposure areas in the two photolithography processes, precise photolithography of small-sized grooves is achieved, thereby solving the problem of low applicability caused by the need to form small-sized graphics through a negative development process in the related technology, and reducing the manufacturing cost to a certain extent.
[0042] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.
Claims
1. A groove etching method, characterized in that: The method is applied to a manufacturing process of a semiconductor device, and the method comprises: Providing a substrate, a first hard mask layer formed on the substrate, a second hard mask layer formed on the first hard mask layer, and the first hard mask layer and the second hard mask layer are made of different materials; Covering the second hard mask layer with a photoresist, exposing it through a first mask, and removing the photoresist in the first target area after developing; Performing etching until the first hard mask layer in the first target area is exposed, forming a first groove in the second hard mask layer, and then removing the photoresist; Covering the second hard mask layer with a photoresist, exposing through the second hard mask layer, and removing the photoresist in the second target area after development, wherein the second target area has an overlapping area with the first target area when viewed from a top view; Performing etching until the substrate in the overlapping area is exposed, and forming a second groove in the first hard mask layer, wherein the second groove is located below the first groove and has a width smaller than that of the first groove; Etching is performed to form a third groove in the substrate below the second groove.
2. The method according to claim 1, characterized in that A ratio of an area of the overlapping region to an area of the substrate is less than 20%.
3. The method according to claim 2, characterized in that The first target area and the second target area have the same shape and size.
4. The method according to claim 3, characterized in that The second target area is offset relative to the first target area by less than 40 nanometers.
5. The method according to claim 4, characterized in that A ratio of the depth to the width of the third groove is greater than 10.
6. The method according to any one of claims 1 to 5, characterized in that: The etching is performed until the substrate in the overlapping area is exposed, and a second groove is formed in the first hard mask layer, comprising: The second groove is formed in the first hard mask layer by etching through a wet etching process.
7. The method according to claim 6, characterized in that The first hard mask layer includes a silicon dioxide layer, and the second hard mask layer includes a silicon nitride layer.