Wafer acceptance test method with low test escape rate

Abstract

The invention discloses a wafer acceptance test method with a low test escape rate. The method specifically comprises the following steps: (1) finding out key WAT electrical parameters which have great influence on the test escape rate in a current batch from WAT electrical parameters; and (2) when wafer acceptance testing is carried out on the current batch of test wafers, testing the key WAT electrical parameters of each crystal grain on the to-be-tested wafer, and carrying out abnormal crystal grain detection based on the key WAT electrical parameters. According to the method, the importance of the WAT electrical parameter characteristics on the escape rate is evaluated firstly, the key WAT electrical parameters which have great influence on the escape rate are determined in a carry mode, only the key WAT electrical parameters are tested for the to-be-detected wafers of the current batch, and the detection task load of the to-be-detected wafers is greatly reduced while the escape rate of wafer detection is not influenced.

Description

Technical Field

[0001] The present invention belongs to the technical field of wafer acceptance testing, and more specifically, the present invention relates to a wafer acceptance testing method with a low test escape rate. Background Art

[0002] In the production process of wafers, Wafer Acceptance Test (WAT) is a pre-step to Circuit Probe (CP). Its main purpose is to evaluate the quality and stability of the semiconductor chip manufacturing process by testing the electrical parameters of specific structures on the wafer and detecting the process conditions of each wafer product. In the wafer testing process, the automated test equipment (ATE) uses the probe card in the wafer probe test to detect the die in each wafer to identify and remove defects or abnormal die that are not suitable for packaging, which requires a lot of time and expensive device costs. Since WAT can predict wafer yield, experienced engineers use WAT predictions to reduce production time and production costs in the CP process. Pre-processing of abnormal die in WAT data is the key to increasing wafer yield.

[0003] During the wafer manufacturing process, since ATE generates WAT electrical parameters for various test items during wafer production, such as output current, logic signal, power supply voltage and operating voltage, when the collected WAT electrical parameters exceed the reasonable parameter range given by the type of detection equipment, the detection point corresponding to the corresponding grain is determined to be abnormal, and the rest are normal grains. After the above-mentioned abnormal grain identification method is used to detect the wafer to be tested, there are still some defective grains that are not captured during the test process and are determined to be qualified grains (normal detection points), which are escape detection points, and thus directly enter chip packaging and functional testing. Some defective grains escape test screening until they are packaged as chip products. During use, more failures occur, resulting in a decline in quality. Summary of the invention

[0004] The present invention provides a wafer acceptance test method with low test escape rate, aiming to improve the above problems.

[0005] The present invention is implemented as follows: a wafer acceptance test method with a low test escape rate, the method is specifically as follows:

[0006] (1) Find out the key WAT electrical parameters that have a great impact on the test escape rate in the current batch from the WAT electrical parameters;

[0007] (2) When performing wafer acceptance testing (WAT) on the test wafers of the current batch, key WAT electrical parameters of each die on the wafer to be tested are tested, and abnormal die are detected based on the key WAT electrical parameters.

[0008] Furthermore, the process of obtaining key WAT electrical parameters is as follows:

[0009] (11) Testing the WAT electrical parameters of multiple wafers to be tested in the current batch and identifying abnormal detection points;

[0010] (12) Determine the escape detection point in the normal detection point, and determine the key WAT electrical parameters that have a great impact on the escape based on the abnormal detection point and the abnormal WAT electrical parameters in the escape detection point.

[0011] Furthermore, the identification process of the escape detection point is as follows:

[0012] (121) Detect escape detection points among normal detection points based on dynamic partial average test and interquartile range test;

[0013] (122) Calculate the abnormality level of each current escape detection point, determine the neighborhood range affected by the escape detection point based on the abnormality level, test the WAT electrical parameters of the detection point within the neighborhood range, and re-detect the escape detection point based on step (121).

[0014] Furthermore, the identification process of the escape detection point based on the dynamic partial average test is as follows:

[0015] First determine the upper limit UCL and lower limit LCL of each WAT electrical parameter. If the WAT electrical parameter exceeds the upper limit UCL or the lower limit LCL, it is considered as an abnormal WAT electrical parameter, and the corresponding die is considered as an escape detection point. The upper limit UCL of the i-th WAT electrical parameter is i , lower limit LCL i The calculation formula is as follows:

[0016] UCL i =μ i +Kσ i ;

[0017] LCL i =μ i -Kσ i ;

[0018] Among them, μ i represents the mean value of the electrical parameters of the i-th WAT, σ i represents the standard deviation of the electrical parameters of the i-th type WAT, K represents the robustness constant, K=3.

[0019] Furthermore, the identification method of the escape detection point based on the interquartile range detection is as follows:

[0020] Calculate the interquartile range (IQR) of the electrical parameters of the i-th category of WAT i, represents the upper quartile of the electrical parameters of the i-th WAT, represents the lower quartile of the electrical parameters of the i-th category WAT;

[0021] Based on the interquartile range (IQR) i Determine the boundary of the abnormal value of the i-th WAT electrical parameter. If the i-th WAT electrical parameter of the normal detection point is lower than or higher The corresponding WAT electrical parameters are identified as abnormal WAT electrical parameters, and the corresponding grains are identified as escape detection points.

[0022] Furthermore, the number of abnormal WAT electrical parameters in each escape detection point is counted. The more the number of abnormal WAT electrical parameters is, the higher the abnormality is, and the larger the neighborhood range affected is; the lower the abnormality is, the smaller the neighborhood range affected is.

[0023] Furthermore, the abnormality degree is divided into four levels, with the first level having the lowest abnormality degree and the fourth level having the highest abnormality degree.

[0024] Furthermore, the proportion of abnormal WAT electrical parameters in the escape detection point is greater than or equal to b 1 , it is determined to be the fourth level of abnormality, and a 7x7 neighborhood is formed with the escape detection point as the center; the proportion of abnormal WAT electrical parameters in the escape detection point is (b 1 ,b 2 ], it is determined as the third level of abnormality, and a 5x5 neighborhood is formed with the escape detection point as the center; the proportion of abnormal WAT electrical parameters in the escape detection point is (b 2 ,b 3 ], it is determined as the second level of abnormality, and a 3x3 neighborhood is formed with the escape detection point as the center; the proportion of abnormal WAT electrical parameters in the escape detection point is lower than b 3 , identified as the first level of abnormality, the escape detection point itself is used as the neighborhood range, where b 1 >b 2 >b 3 .

[0025] Furthermore, the determination process of key WAT electrical parameters is as follows:

[0026] (123) extracting abnormal WAT electrical parameters from all abnormal detection points, classifying the extracted abnormal WAT electrical parameters, and normalizing each type of abnormal WAT electrical parameters;

[0027] (124) inputting each type of abnormal WAT electrical parameter processed in step (123) into the NSGA-II algorithm, and determining the Shapely value of each type of WAT electrical parameter based on the NSGA-II algorithm, wherein the Shapely value reflects the influence of each type of WAT electrical parameter on the escape rate;

[0028] (125) Based on the Shapely values ​​of various WAT electrical parameters, several WAT electrical parameters that have a great impact on the escape rate are selected as the key WAT electrical parameters of the current batch of wafers.

[0029] The wafer acceptance test method with low test escape rate proposed by the present invention has the following beneficial technical effects:

[0030] (1) Dynamic average test and interquartile range are used to detect abnormalities in the WAT electrical data of the generated die, which is beneficial to reduce the escape rate of wafer inspection;

[0031] (2) Based on the abnormality of the escaped grains, the affected neighborhood range is determined. The higher the abnormality, the larger the affected range. By retesting the local area, the escape rate of wafer inspection is further reduced.

[0032] (3) Shapely values ​​are used to evaluate the importance of WAT electrical parameter characteristics to the escape rate, and the key WAT electrical parameters that have a greater impact on the escape rate are determined. Only the key WAT electrical parameters are tested for the current batch of wafers to be tested. This does not affect the escape rate of wafer detection and greatly reduces the detection task volume of the wafers to be tested. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A flow chart of a wafer acceptance test method with a low test escape rate provided by an embodiment of the present invention. Implementation

[0035] The specific implementation modes of the present invention are further explained in detail below by describing the embodiments with reference to the accompanying drawings, so as to help those skilled in the art to have a more complete, accurate and in-depth understanding of the inventive concept and technical solution of the present invention.

[0036] Figure 1 A flowchart of a wafer acceptance test method with a low test escape rate provided by an embodiment of the present invention, the method is specifically as follows:

[0037] (1) Find out the key WAT electrical parameters that have a great impact on the test escape rate in the current batch from the WAT electrical parameters;

[0038] (2) When performing wafer acceptance testing (WAT) on the test wafers of the current batch, key WAT electrical parameters of each die on the wafer to be tested are tested, and abnormal die are detected based on the key WAT electrical parameters.

[0039] Since there are large differences in the WAT electrical parameters of wafers prepared from different batches of wafers to be tested, it is necessary to determine the key WAT electrical parameters of each batch of wafers to be tested, eliminate the WAT electrical parameters that have a small impact on the test escape rate, and only test the key WAT electrical parameters of each grain on the test wafer, thereby reducing the test cost and the test escape rate. Abnormal grains are detected based on steps (121) and (122). If an abnormal grain is determined to be normal, it is an escaped grain or an escape detection point in the present invention.

[0040] The following is a detailed description of the process of obtaining key WAT electrical parameters. The process of obtaining key WAT electrical parameters is as follows:

[0041] (11) Testing the WAT electrical parameters of multiple wafers to be tested in the current batch and identifying abnormal detection points;

[0042] Since the abnormal detection point is identified based on a reasonable parameter range given by the detection device, the identification process is already known and will not be described in detail in the present invention.

[0043] (12) Determine the escape detection point in the normal detection point, and determine the key WAT electrical parameters that have a great impact on the escape based on the abnormal detection point and the abnormal WAT electrical parameters in the escape detection point.

[0044] In the embodiment of the present invention, the escape detection point refers to an abnormal detection point determined as a normal detection point. The detection process of the escape detection point is as follows:

[0045] (121) Detect escape detection points among normal detection points based on dynamic partial average test and interquartile range test;

[0046] In the embodiment of the present invention, if a normal detection point is identified as an abnormal detection point in the dynamic partial average test or the interquartile range test, the corresponding detection points are all escape detection points.

[0047] The dynamic partial average test process needs to first determine the upper limit UCL and lower limit LCL of each WAT electrical parameter. If the WAT electrical parameter exceeds the upper limit UCL or lower limit LCL, it is identified as an escape detection point. The upper limit UCL of the i-th WAT electrical parameter i , lower limit LCL i The determination is based on formula (1) and formula (2), and formula (1) and formula (2) are specifically as follows:

[0048] UCLi =μ i +Kσ i (1)

[0049] LCL i =μ i -Kσ i (2)

[0050] Among them, μ i represents the mean value of the electrical parameters of the i-th WAT, σ i represents the standard deviation of the electrical parameters of the i-th WAT, K represents the robustness constant, and usually K = 3. If the i-th WAT electrical parameter of a detection point exceeds the range corresponding to the lower limit and the upper limit, the detection point is an escape detection point.

[0051] In the embodiment of the present invention, the mean value μ of the electrical parameter of the i-th WAT is calculated using formula (3) and formula (4) respectively. i and standard deviation σ i , formula (3) and formula (4) are as follows:

[0052]

[0053] Where n represents the total number of WAT electrical parameter types, X i Indicates the test value of the electrical parameter of the i-th type WAT.

[0054] Dynamic Part Average Testing (DPAT) is a quality control method used to detect outliers in product parameters during the manufacturing process, identify and exclude abnormal products in production to ensure overall product quality. However, since DPAT can only detect a limited number of outliers, some biased erroneous data may not be detected. Therefore, it is necessary to add interquartile range (IQR) detection to the technology of dynamic partial average testing to identify escaped detection points in normal production detection points. The interquartile range is more robust when dealing with non-normal or skewed distributed data and provides a more reliable discrete measure. It reduces the impact of extreme values ​​(outliers) and more accurately reflects the central tendency and degree of dispersion of the data.

[0055] In the embodiment of the present invention, the interquartile range IQR of the electrical parameters of the i-th WAT is calculated. i , based on the interquartile range (IQR) i Determine the boundaries of outliers for the i-th category of WAT electrical parameters, represents the upper quartile of the electrical parameters of the i-th WAT, represents the lower quartile of the electrical parameters of the i-th WAT, then If the i-th type WAT electrical parameter of the normal detection point is lower than or higher The corresponding normal detection point is identified as an escape detection point.

[0056] (122) Calculate the abnormality level of each current escape detection point, determine the scope of the area affected by the escape detection point based on the abnormality level, test the WAT electrical parameters of the detection points within the neighborhood, and perform escape detection again based on step (121).

[0057] In the embodiment of the present invention, the number of abnormal WAT electrical parameters in each escape detection point is counted. The more the number of abnormal WAT electrical parameters is, the higher the abnormality is, and the larger the neighborhood range affected is; the lower the abnormality is, the smaller the neighborhood range affected is. The detection points within the neighborhood range are affected by the escape detection points and may also show abnormalities. Therefore, the detection points within the neighborhood range have a relatively high risk of escape. Performing escape detection on the detection points within the neighborhood range again can greatly reduce the risk of escape.

[0058] In the embodiment of the present invention, the abnormality degree is divided into four levels, the first level has the lowest abnormality degree, and the fourth level has the highest abnormality degree. The number of abnormal WAT electrical parameters in the escape detection point accounts for greater than or equal to b 1 , it is determined to be the fourth level of abnormality, and a 7x7 neighborhood is formed with the escape detection point as the center; the proportion of abnormal WAT electrical parameters in the escape detection point is (b 1 ,b 2 ], it is determined as the third level of abnormality, and a 5x5 neighborhood is formed with the escape detection point as the center; the proportion of abnormal WAT electrical parameters in the escape detection point is (b 2 ,b 3 ], it is determined as the second level of abnormality, and a 3x3 neighborhood is formed with the escape detection point as the center; the proportion of abnormal WAT electrical parameters in the escape detection point is lower than b 3 , identified as the first level of abnormality, the escape detection point itself is used as the neighborhood range, where b 1 >b 2 >b 3 .

[0059] In the present invention, n=6, that is, each detection point has 6 types of WAT electrical parameters. When six WAT electrical parameter anomalies exist at the escape detection point, a neighborhood range of 7x7 is formed with the escape detection point as the center. When four or five WAT electrical parameter anomalies exist at the escape detection point, a neighborhood range of 5x5 is formed with the escape detection point as the center. When two or three WAT electrical parameters are abnormal at the escape detection point, a neighborhood range of 3x3 is formed with the escape detection point as the center. When only one WAT electrical parameter anomaly exists at the escape detection point, the neighborhood range only includes the escape detection point itself. The above method not only reduces the risk of over-testing, but also reduces the cost of WAT, while reducing the risk of escape.

[0060] In the embodiment of the present invention, the process of determining the key WAT electrical parameters is as follows:

[0061] (123) extracting abnormal WAT electrical parameters from all abnormal detection points, classifying the extracted abnormal WAT electrical parameters, and normalizing each type of abnormal WAT electrical parameters;

[0062] (124) inputting each type of abnormal WAT electrical parameter processed in step (123) into the NSGA-II algorithm, and determining the Shapely value of each type of WAT electrical parameter within the boundary range based on the NSGA-II algorithm, wherein the Shapely value reflects the influence of each type of WAT electrical parameter on the escape rate;

[0063] In the embodiment of the present invention, based on the boundary range: g(X i )=φ(X i )*l i , g(X i )≤0, where φ(X i ) is the Shapely value calculation model for the electrical parameters of the i-th abnormal WAT, l i is the contribution coefficient, which is determined based on the number of abnormal WAT electrical parameters of the i-th type. The greater the number, the greater the contribution coefficient. i The larger the value, the value is between 0 and 1.

[0064] (125) Based on the Shapely values ​​of various WAT electrical parameters, several WAT electrical parameters that have a great impact on the escape rate are selected as the key WAT electrical parameters of the current batch of wafers. Subsequent wafers to be tested only need to detect the key WAT electrical parameters to identify abnormal detection points, which greatly reduces the test volume and reduces the escape rate during the test process.

[0065] The wafer acceptance test method with low test escape rate proposed by the present invention has the following beneficial technical effects:

[0066] (1) Dynamic average test and interquartile range are used to detect abnormalities in the WAT electrical data of the generated die, which is beneficial to reduce the escape rate of wafer inspection;

[0067] (2) Based on the abnormality of the escaped grains, the affected neighborhood range is determined. The higher the abnormality, the larger the affected range. By retesting the local area, the escape rate of wafer inspection is further reduced.

[0068] (3) Shapely values ​​are used to evaluate the importance of WAT electrical parameter characteristics to the escape rate, and the key WAT electrical parameters that have a greater impact on the escape rate are determined. Only the key WAT electrical parameters are tested for the current batch of wafers to be tested. This does not affect the escape rate of wafer detection and greatly reduces the detection task volume of the wafers to be tested.

[0069] The present invention has been described exemplarily. Obviously, the specific implementation of the present invention is not limited to the above-mentioned method. As long as various non-substantial improvements are made using the method concept and technical solution of the present invention, or the concept and technical solution of the present invention are directly applied to other occasions without improvement, they are all within the protection scope of the present invention.

Claims

1. A wafer acceptance test method with low test escape rate, characterized in that: The method is specifically as follows: (1) Find out the key WAT electrical parameters that have a great impact on the test escape rate in the current batch from the WAT electrical parameters; (2) When performing wafer acceptance testing on the test wafers of the current batch, key WAT electrical parameters of each die on the wafer to be tested are tested, and abnormal die are detected based on the key WAT electrical parameters.

2. The wafer acceptance test method with low test escape rate as claimed in claim 1, characterized in that: The process of obtaining key WAT electrical parameters is as follows: (11) Testing the WAT electrical parameters of multiple wafers to be tested in the current batch and identifying abnormal detection points; (12) Determine the escape detection point in the normal detection point, and determine the key WAT electrical parameters that have a great impact on the escape based on the abnormal detection point and the abnormal WAT electrical parameters in the escape detection point.

3. The wafer acceptance test method with low test escape rate as claimed in claim 2, characterized in that: The identification process of the escape detection point is as follows: (121) Detect escape detection points among normal detection points based on dynamic partial average test and interquartile range test; (122) Calculate the abnormality level of each current escape detection point, determine the neighborhood range affected by the escape detection point based on the abnormality level, test the WAT electrical parameters of the detection point within the neighborhood range, and re-detect the escape detection point based on step (121).

4. The wafer acceptance test method with low test escape rate as claimed in claim 3, characterized in that: The identification process of escape detection points based on dynamic partial average test is as follows: First determine the upper limit UCL and lower limit LCL of each WAT electrical parameter. If the WAT electrical parameter exceeds the upper limit UCL or the lower limit LCL, it is considered as an abnormal WAT electrical parameter, and the corresponding die is considered as an escape detection point. The upper limit UCL of the i-th WAT electrical parameter is i , lower limit LCL i The calculation formula is as follows: UCL i =μ i +Kσ i ; LCL i =μ i -Kσ i ; Among them, μ i represents the mean value of the electrical parameters of the i-th WAT, σ i represents the standard deviation of the electrical parameters of the i-th type WAT, K represents the robustness constant, K=3.

5. The wafer acceptance test method with low test escape rate as claimed in claim 3, characterized in that: The identification method of escape detection points based on interquartile range detection is as follows: Calculate the interquartile range (IQR) of the electrical parameters of the i-th category of WAT i , represents the upper quartile of the electrical parameters of the i-th WAT, represents the lower quartile of the electrical parameters of the i-th category WAT; Based on the interquartile range (IQR) i Determine the boundary of the abnormal value of the i-th WAT electrical parameter. If the i-th WAT electrical parameter of the normal detection point is lower than or higher The corresponding WAT electrical parameters are identified as abnormal WAT electrical parameters, and the corresponding grains are identified as escape detection points.

6. The wafer acceptance test method with low test escape rate as claimed in claim 3, characterized in that: The number of abnormal WAT electrical parameters in each escape detection point is counted. The more the number of abnormal WAT electrical parameters is, the higher the abnormality is, and the larger the affected neighborhood range is; the lower the abnormality is, the smaller the affected neighborhood range is.

7. The wafer acceptance test method with low test escape rate as claimed in claim 6, characterized in that: The abnormality degree is divided into four levels, with the first level having the lowest abnormality and the fourth level having the highest abnormality.

8. The wafer acceptance test method with low test escape rate as claimed in claim 7, characterized in that: If the proportion of abnormal WAT electrical parameters in the escape detection point is greater than or equal to b1, it is determined to be the fourth level of abnormality, and a 7x7 neighborhood range is formed with the escape detection point as the center; if the proportion of abnormal WAT electrical parameters in the escape detection point is between (b1, b2], it is determined to be the third level of abnormality, and a 5x5 neighborhood range is formed with the escape detection point as the center; if the proportion of abnormal WAT electrical parameters in the escape detection point is between (b2, b3], it is determined to be the second level of abnormality, and a 3x3 neighborhood range is formed with the escape detection point as the center; if the proportion of abnormal WAT electrical parameters in the escape detection point is less than b3, it is determined to be the first level of abnormality, and the escape detection point itself is used as the neighborhood range, where b1>b2>b3.

9. The wafer acceptance test method with low test escape rate as claimed in claim 2, characterized in that: The process of determining the key WAT electrical parameters is as follows: (123) extracting abnormal WAT electrical parameters from all abnormal detection points, classifying the extracted abnormal WAT electrical parameters, and normalizing each type of abnormal WAT electrical parameters; (124) inputting each type of abnormal WAT electrical parameter processed in step (123) into the NSGA-II algorithm, and determining the Shapely value of each type of WAT electrical parameter based on the NSGA-II algorithm, wherein the Shapely value reflects the influence of each type of WAT electrical parameter on the escape rate; (125) Based on the Shapely values ​​of various WAT electrical parameters, several WAT electrical parameters that have a great impact on the escape rate are selected as the key WAT electrical parameters of the current batch of wafers.

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