Chip pickup method and chip pickup equipment

Abstract

The invention discloses a method for picking up a chip and chip picking up equipment. The method for picking up the chip comprises the following steps: acquiring a first image of a first wafer placed on the chip picking up equipment; selecting M reference chips from the chips of the first image, and determining first position information of each reference chip; determining first relative position information of a first reference chip and a reference chip of the first wafer according to the first position information; acquiring a second image of a second wafer placed on the chip pickup device; the structure of the second wafer is the same as that of the first wafer; m target chips are determined in the second image, the arrangement of the M target chips is the same as the arrangement of the M reference chips, and the state information of the adjacent areas of the M target chips is the same as the state information of the adjacent areas of the M reference chips; determining second position information of a second reference chip of the second wafer in a second image; and third position information of the qualified chip in the second image is determined, and control information for picking up the chip is generated.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for picking up a chip and a chip picking device. Background Art

[0002] In the chip packaging process, the chip is first picked up from the wafer, mounted on the carrier, and then the plastic sealing and rewiring steps are performed. The process of picking up the chip from the wafer is as follows: first obtain the layout file of the chip, and the identification of the qualified chip in the chip layout file is different from the identification of the bad chip; then the operator determines the position of the starting chip to be picked up in the wafer, and starts the qualified chip according to the relative position of the qualified chip and the starting chip in the chip layout file.

[0003] In the above-mentioned method for picking up chips, if the initial position for picking up the chips is not determined accurately, defective chips may be picked up, thus affecting the yield of the packaged products. Summary of the invention

[0004] The embodiments of the present application provide a method for picking up a chip and a chip picking device.

[0005] According to a first aspect of an embodiment of the present application, a method for picking up a chip is provided, which is applied to a chip picking device. The method for picking up a chip includes:

[0006] Acquire a first image of a first wafer placed on the chip pickup device; the first wafer includes a plurality of chips arranged in an array, and adjacent chips are spaced apart;

[0007] M reference chips are selected from the chips in the first image, and first position information of each of the reference chips in the first image is determined; wherein state information of adjacent areas of the M reference chips is not completely the same as state information of adjacent areas of any M chips in the first image that are not completely the same as the M reference chips and are arranged in the same manner; the state information includes whether a chip is provided and whether the chip is complete when a chip is provided; M is an integer greater than or equal to 2;

[0008] Determine first relative position information between a first reference chip of the first wafer and the reference chip in the first image according to the first position information;

[0009] Acquire a second image of a second wafer placed on the chip pickup device; the structure of the second wafer is the same as that of the first wafer;

[0010] Determine M target chips in the second image according to the state information of each reference chip and the state information of an adjacent region of each reference chip, wherein the arrangement of the M target chips is the same as the arrangement of the M reference chips, and the state information of the adjacent regions of the M target chips is the same as the state information of the adjacent regions of the M reference chips;

[0011] Determining second position information of a second reference chip of the second wafer in the second image according to the position information of the target chip in the second image and the first relative position information;

[0012] The third position information of the qualified chip in the second image is determined according to the second position information and the second relative position information between the qualified chip of the second wafer and the second reference chip, and control information for picking up the chip is generated according to the third position information.

[0013] In one embodiment, at least two of the M reference chips are located in different rows, and at least two of the reference chips are located in different columns; status information of areas adjacent to two sides of at least one reference chip is that there is no chip or there is an incomplete chip.

[0014] In one embodiment, the at least two first chips located in the same row are adjacent to each other, and the at least two first chips located in the same column are adjacent to each other.

[0015] In one embodiment, M is equal to three; and / or, the reference chip is a complete chip.

[0016] In one embodiment, determining first relative position information of the first reference chip and the reference chip of the first wafer in the first image according to the first position information includes:

[0017] Determining third relative position information of the reference chip and the center of the first wafer in the first image according to the first position information;

[0018] The first relative position information is determined according to the relative position information between the first reference chip and the center of the first wafer and the third relative position information.

[0019] In one embodiment, determining the second position information of the second reference chip of the second wafer in the second image according to the position information of the target chip in the second image and the first relative position information includes:

[0020] Using the first relative position information as fourth relative position information between the target chip and the second reference chip;

[0021] The second position information of the second reference chip in the image is determined according to the position information of the target chip in the second image and the fourth relative position information.

[0022] In one embodiment, before determining the third position information of the qualified chip in the second image according to the second position information and the second relative position information of the qualified chip of the second wafer and the second reference chip, and generating the control information for picking up the chip according to the third position information, the method for picking up the chip further includes:

[0023] Obtaining a layout drawing of the second wafer; wherein the identification of the qualified chip in the layout drawing is different from the identification of the defective chip;

[0024] A second relative position relationship between the qualified chip and the second reference chip is determined according to the layout drawing.

[0025] In one embodiment, the second wafer includes a plurality of the qualified chips;

[0026] The method of determining the third position information of the qualified chip in the second image according to the second position information and the second relative position information of the qualified chip of the second wafer and the second reference chip, and generating control information for picking up the chip according to the third position information, comprises:

[0027] For each of the qualified chips, the third position information of the qualified chip in the second image is determined according to the second position information and the second relative position information between the qualified chip and the second reference chip, and control information for picking up the qualified chip is generated according to the third position information.

[0028] In one embodiment, the first image includes a plurality of first image regions, and after selecting M reference chips from the chips in the first image, the chip picking method further includes: determining the first image regions where the M reference chips are located;

[0029] The second image includes a plurality of second image areas, and a position of an area of ​​the second wafer corresponding to each of the second image areas on the chip pickup device is the same as a position of an area of ​​the second wafer corresponding to one of the first image areas on the chip pickup device;

[0030] Determining M target chips in the second image according to the status information of each reference chip and the status information of an adjacent area of ​​each reference chip includes:

[0031] Determine a second image area corresponding to the first image area where the reference chip is located;

[0032] The target chip is searched for in the determined second image area according to the status information of each reference chip and the status information of an adjacent area of ​​each reference chip.

[0033] In one embodiment, searching for the target chip in the determined second image area according to the state of each reference chip and the state of the area adjacent to the side of each reference chip includes:

[0034] If the target chip does not exist in the determined second image area, generating control information for adjusting the position of the second wafer on the chip pickup device, and reacquiring the second image after the position of the second wafer is adjusted;

[0035] The target chip is searched for in a second image area corresponding to the first image area where the reference chip is located in the re-acquired second image.

[0036] According to the second aspect of an embodiment of the present application, a chip picking device is provided, which includes a carrier, a camera, a manipulator and a processor, the carrier is used to place a wafer, the camera is used to obtain an image of the wafer placed on the carrier, the manipulator is used to pick up a qualified chip from the wafer, and the processor is used to execute the above-mentioned method of picking up chips.

[0037] The main technical effects achieved by the embodiments of the present application are:

[0038] The method for picking up chips and the chip picking device provided in the embodiment of the present application first determine the position information of M reference chips and the state information of the adjacent areas of the M reference chips, and the first relative position information of the first reference chip and the reference chip in the first image of the first wafer. Since the state information of the adjacent areas of the M reference chips is not completely the same as the state information of the adjacent areas of any M chips in the first image that are not completely the same as the M reference chips and arranged in the same manner, the M target chips determined in the second image of the second wafer that are the same as the state information of the M reference chips and the state information of the adjacent areas are unique, and then the second position information of the second reference chip determined according to the position information of the target chip in the second image and the first relative position information is also unique, which can ensure that the second position information of the second reference chip is accurate. Therefore, the position of the qualified chip determined according to the second position information and the second relative position information of the qualified chip of the second wafer and the second reference chip is accurate, which can ensure that the chip picked up by the chip picking device according to the control information of the picked-up chip is a qualified chip, avoiding the situation of picking up a bad chip. The method for picking up chips provided in the embodiment of the present application can be executed by a processor of the chip picking device without manual operation, which can improve the efficiency of picking up the chip picking device. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 is a flow chart of a method for picking up a chip provided by an exemplary embodiment of the present application;

[0040] Figure 2 is a schematic diagram of a partial area of ​​a first image of a first wafer provided by an exemplary embodiment of the present application;

[0041] Figure 3 is a side view of a first wafer provided by an exemplary embodiment of the present application;

[0042] Figure 4 is a schematic diagram of a partial area of ​​a second image of a second wafer provided by an exemplary embodiment of the present application;

[0043] Figure 5 It is a hardware structure diagram of a chip picking device provided by an exemplary embodiment of the present application. Specific embodiments

[0044] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0045] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0046] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0047] Some embodiments of the present application are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0048] The present application embodiment provides a method for picking up a chip. The method for picking up a chip is applied to a chip picking device. Figure 1 As shown, the method for picking up a chip includes the following steps 110 to 170 .

[0049] In step 110, a first image of a first wafer placed on the chip pickup device is acquired; the first wafer includes a plurality of chips arranged in an array, and adjacent chips are spaced apart.

[0050] In step 120, M reference chips are selected from the chips in the first image, and the first position information of each reference chip in the first image is determined; wherein the status information of adjacent areas of the M reference chips is not completely the same as the status information of adjacent areas of any M chips in the first image that are not completely identical to the M reference chips and have the same arrangement; the status information includes whether a chip is provided and whether the chip is complete when a chip is provided; M is an integer greater than or equal to 2.

[0051] In step 130 , first relative position information between a first benchmark chip and the reference chip of the first wafer in the first image is determined according to the first position information.

[0052] In step 140, a second image of a second wafer placed on the stage is acquired; the structure of the second wafer is the same as that of the first wafer.

[0053] In step 150, based on the status information of each of the reference chips and the status information of the adjacent areas of each of the reference chips, M target chips are determined in the second image, the arrangement of the M target chips is the same as the arrangement of the M reference chips, and the status information of the adjacent areas of the M target chips is the same as the status information of the adjacent areas of the M reference chips.

[0054] In step 160, second position information of a second reference chip of the second wafer in the second image is determined according to the position information of the target chip in the second image and the first relative position information.

[0055] In step 170, third position information of the qualified chip in the second image is determined according to the second position information and second relative position information between the qualified chip of the second wafer and the second reference chip, and control information for picking up the chip is generated according to the third position information.

[0056] The method for picking up chips provided in the embodiment of the present application first determines the position information of M reference chips and the state information of adjacent areas of the M reference chips, and the first relative position information of the first reference chip and the reference chip in the first image of the first wafer. Since the state information of the adjacent areas of the M reference chips is not completely the same as the state information of the adjacent areas of any M chips in the first image that are not completely the same as the M reference chips and are arranged in the same manner, the M target chips determined in the second image of the second wafer that are the same as the state information of the M reference chips and the state information of the adjacent areas are unique, and then the second position information of the second reference chip determined according to the position information of the target chip in the second image and the first relative position information is also unique, which can ensure that the second position information of the second reference chip is accurate. Therefore, the position of the qualified chip determined according to the second position information and the second relative position information of the qualified chip of the second wafer and the second reference chip is accurate, which can ensure that the chip picked up by the chip picking device according to the control information of the chip picking is a qualified chip, avoiding the situation of picking up a bad chip. The method for picking up chips provided in the embodiment of the present application can be executed by a processor of the chip picking device without manual operation, which can improve the efficiency of picking up the chip picking device.

[0057] The following is a detailed introduction to each step of the method for picking up a chip provided in an embodiment of the present application.

[0058] In step 110, a first image of a first wafer placed on the chip pickup device is acquired; the first wafer includes a plurality of chips arranged in an array, and adjacent chips are spaced apart.

[0059] In one embodiment, Figure 2 and Figure 3 As shown, the first wafer 10 includes a plurality of chips 11, and the plurality of chips 11 are arranged in a plurality of rows and columns, with the row direction being the X direction and the column direction being the Y direction. There is a gap between adjacent chips 11 in the first wafer 10, and the first wafer 10 also includes a bonding layer 12 located on one side of the chip 11, and all the chips 11 in the first wafer 10 are bonded to the bonding layer 12, and the chips 11 in the first wafer 10 will not move relative to the bonding layer 12.

[0060] In one embodiment, Figure 2 As shown, the chips 11 in the first wafer 10 include complete chips 111 and incomplete chips 112 , and the incomplete chips 112 are located in the edge area of ​​the wafer 10 .

[0061] In one embodiment, the chip picking device includes a stage, a camera, a manipulator and a processor. The stage is used to place a wafer. The camera is used to obtain an image of the wafer placed on the stage. The manipulator is used to pick up a chip from the wafer. The manipulator can also place the picked-up chip on a carrier for mounting the chip. The processor is used to execute the method for picking up the chip, and the processor is also used to control the camera and the manipulator.

[0062] In one embodiment, the step of acquiring a first image of a first wafer placed on the chip pickup device includes the following process: controlling an imaging device to acquire a first image of the first wafer placed on the stage.

[0063] In step 120, M reference chips are selected from the chips in the first image, and the first position information of each reference chip in the first image is determined; wherein the status information of adjacent areas of the M reference chips is not completely the same as the status information of adjacent areas of any M chips in the first image that are not completely identical to the M reference chips and have the same arrangement; the status information includes whether a chip is provided and whether the chip is complete when a chip is provided; M is an integer greater than or equal to 2.

[0064] In one embodiment, the adjacent region of the chip refers to the region adjacent to each side of the chip, for example Figure 2 The chip shown in FIG. 1 includes four sides, and the adjacent area of ​​the chip refers to the area adjacent to each side of the chip. Figure 2 As shown, the status information of the adjacent areas of chip 113 is: the upper area is provided with an incomplete chip, the left area is provided with an incomplete chip, the right area is provided with a complete chip, and the lower area is provided with a complete chip; the status information of the adjacent areas of chip 114 is: the upper area is provided with an incomplete chip, the left area is provided with a complete chip, the right area is provided with a complete chip, and the lower area is provided with a complete chip; the status information of the adjacent areas of chip 115 is: the upper area is provided with a complete chip, the left area is provided with a complete chip, the right area is provided with a complete chip, and the lower area is provided with a complete chip.

[0065] In one embodiment, the arrangement of M chips includes the relative position information of any two adjacent chips among the M chips. For example, when M is three, the arrangement of three chips includes the relative position information of any two chips among the three chips. Figure 2 As shown, the arrangement of the three chips 113, 114 and 115 includes: chip 114 is adjacent to chip 113, the two are located in the same row and chip 114 is located on the right side of chip 113; chip 115 is adjacent to chip 114, the two are located in the same column and chip 115 is located on the lower side of chip 114. The arrangement of chips 116, 117 and 118 is the same as that of chips 113, 114 and 115.

[0066] In one embodiment, the M reference chips are adjacent, and at least two of the M reference chips are located in different rows, and at least two of the reference chips are located in different columns; the state information of the area adjacent to two sides of at least one reference chip is no chip or an incomplete chip is provided. In this way, the uniqueness of the state information of the adjacent areas of the M reference chips can be guaranteed.

[0067] Furthermore, M is equal to three. When M is less than three, the probability that the state information of the adjacent areas of the M chips selected at random is unique is small, which will make the process of determining the reference chip take a long time. When M is equal to three, the probability that the state information of the adjacent areas of two chips selected at random is unique is large, which helps to shorten the duration of the process of determining the reference chip. If M is greater than three, the number of chips increases, and the state information data of the adjacent areas of the chips is more, which will increase the time required to determine the reference chip.

[0068] Furthermore, the reference chip is a complete chip. When the chip is an incomplete chip, the processor may not be able to identify it, resulting in the situation that the target chip cannot be determined in the second image in the subsequent steps. By setting the reference chip to a complete chip, this problem can be avoided.

[0069] In one embodiment, the step of selecting M reference chips from the chips in the first image may include the following process:

[0070] First, M first chips are selected in the first image, and state information of the M first chips and state information of adjacent areas of the M first chips are determined;

[0071] Then, all chipsets are determined in the first image, each chipset includes M second chips, each second chip has the same state information as the corresponding first chip, and the M second chips are arranged in the same manner as the M first chips, but are not completely the same as the M first chips;

[0072] Then, determining the state information of the adjacent areas of the M second chips;

[0073] Then, for each chip group, determining whether the state information of the adjacent regions of the M first chips is the same as the state information of the adjacent regions of the M second chips;

[0074] If the judgment result for each chipset is negative, the M first chips are used as M reference chips; if the judgment result for at least one chipset is positive, the above steps are repeated.

[0075] In one embodiment, the step of selecting M first chips in the first image may include the following steps: selecting M first chips in the first image, at least two of the M first chips are located in different rows, at least two chips are located in different columns, and the state of the area adjacent to two sides of at least one first chip is that there is no chip or the chip is incomplete. This arrangement makes it easier to determine the reference chip and can shorten the time required to determine the reference chip.

[0076] Furthermore, the at least two first chips located in the same row are adjacent to each other, and the at least two first chips located in the same column are adjacent to each other. In this way, the time required for determining the reference chip can be further shortened.

[0077] Furthermore, the step of determining all the chipsets in the first image may include the following process: determining all the chipsets in the chips located in the edge area in the first image. Since only the adjacent areas on the two sides of the chips located in the edge area of ​​the wafer are in the state of no chips or incomplete chips, and the adjacent areas on the sides of the chips located in the central area of ​​the wafer are in the state of complete chips, there will be no chipsets in the chips located in the central area of ​​the wafer that have the same status information as the adjacent areas of the M first chips. By determining the chipsets in the chips located in the edge area, the time required to determine the reference chip can be effectively shortened.

[0078] In step 130 , first relative position information between a first reference chip and the reference chip of the first wafer in the first image is determined according to the first position information.

[0079] The first reference chip is a determined chip in the first wafer, and the position of the qualified chip can be determined by the relative position relationship between the first reference chip and the qualified chip and the first reference chip.

[0080] In one embodiment, determining first relative position information of a first reference chip on the first wafer and the reference chip in the first image according to the first position information includes the following process:

[0081] First, determining third relative position information of the reference chip and the center of the first wafer in the first image according to the first position information;

[0082] Subsequently, the first relative position information is determined according to the relative position information between the first reference chip and the center of the first wafer and the third relative position information.

[0083] In one embodiment, the cross section of the first wafer is circular, and the processor may determine position information of the center of the first wafer in the first image, and then determine third relative position information between the first position information and the center of the first wafer according to the first position information.

[0084] In one embodiment, the first position information of the reference chip may include the position information of all reference chips, and the third relative position information may include the relative position information of each reference chip and the center of the first wafer, or may include only the relative position information of one reference chip and the center of the first wafer. The third relative position information may include only the relative position information of the reference chip 115 and the center 101 of the first wafer, such as Figure 2 As shown, the third relative position information is: in the X direction, the center of the first wafer 101 is located between two adjacent chips, the reference chip 115 is located above the center 101 of the first wafer, and is spaced six rows of chips from a row of chips where the center 101 of the first wafer is located in the Y direction; the reference chip 115 is located on the left side of the center 101 of the first wafer, and is spaced one column of chips from the center 101 of the first wafer in the X direction.

[0085] In one embodiment, the relative position information of the first reference chip and the center of the first wafer in the first image is pre-stored in the chip picking device, and the processor can directly call it in the above steps. Figure 2 As shown, the relative position information of the first reference chip and the center of the first wafer is: the center of the first wafer 101 is located between two adjacent chips in the X direction, the first reference chip 119 is located below the center of the first wafer 10, and is adjacent to a row of chips where the center of the first wafer 10 is located in the Y direction; the first reference chip 119 is located to the left of the center of the first wafer 10, and is separated from the center of the first wafer 10 by eight columns of chips in the X direction. According to the above third relative position information and the relative position information of the first reference chip and the center of the first wafer, the first relative position information determined is: the first reference chip 119 is located above the reference chip 115, and is separated from the reference chip 115 by seven rows of chips in the Y direction; the first reference chip 119 is located to the left of the reference chip 115, and is separated from the reference chip 115 by six columns of chips in the X direction.

[0086] In step 140, a second image of a second wafer placed on the stage is acquired; the structure of the second wafer is the same as that of the first wafer.

[0087] like Figure 2 and Figure 4 As shown, the structure of the second wafer 20 is the same as that of the first wafer 10 ; the second wafer 20 includes an adhesive layer 22 and a plurality of chips 21 located on the adhesive layer 22 , and adjacent chips 21 are arranged at intervals.

[0088] The structure of the second wafer is the same as that of the first wafer, which means that the status information of each position in the second wafer is completely the same as the status information of the corresponding position in the first wafer.

[0089] In this step, the processor controls the camera to acquire a second image of the second wafer placed on the stage.

[0090] In step 150, based on the status information of each of the reference chips and the status information of the adjacent areas of each of the reference chips, M target chips are determined in the second image, the arrangement of the M target chips is the same as the arrangement of the M reference chips, and the status information of the adjacent areas of the M target chips is the same as the status information of the adjacent areas of the M reference chips.

[0091] like Figure 4 As shown, the M target chips in the second image are respectively: target chip 211, target chip 212 and target chip 213. The arrangement of target chips 211, 212 and 213 is the same as the arrangement of reference chips 113, 114 and 115, and the state information of the adjacent area of ​​target chip 211 is the same as the state information of the adjacent area of ​​reference chip 113, the state information of the adjacent area of ​​target chip 212 is the same as the state information of the adjacent area of ​​reference chip 114, and the state information of the adjacent area of ​​target chip 213 is the same as the state information of the adjacent area of ​​reference chip 115.

[0092] Since the state information of the adjacent areas of the M reference chips in the first image is unique, and the structure of the first wafer is the same as that of the second wafer, the M target chips determined in the second image are unique.

[0093] In one embodiment, the first image includes a plurality of first image regions, and after selecting M reference chips from the chips in the first image, the chip picking method further includes: determining the first image region where the M reference chips are located. That is, the M reference chips are all located in the same first image region.

[0094] The sizes of the first image regions may be the same, for example, the first image includes four first image regions, and the area of ​​each first image region is one quarter of the total area of ​​the first image. Alternatively, the areas of the first image regions are not all the same.

[0095] Furthermore, the second image includes a plurality of second image areas, and the position of the area of ​​the second wafer corresponding to each second image area on the chip pickup device is the same as the position of the area of ​​the second wafer corresponding to one first image area on the chip pickup device. Determining M target chips in the second image according to the status information of each reference chip and the status information of the adjacent area of ​​each reference chip includes the following process:

[0096] First, determining a second image region corresponding to the first image region where the reference chip is located;

[0097] Then, the target chip is searched for in the determined second image area according to the status information of each reference chip and the status information of the adjacent area of ​​each reference chip.

[0098] When placing the wafer on the carrier, the orientation of the wafer is fixed, that is, the position of the first wafer on the carrier when it is placed on the carrier is basically the same as the position of the second wafer on the carrier when it is placed on the carrier, or the second wafer is deflected at a very small angle relative to the first wafer. Then, when the position of the area of ​​the second wafer corresponding to the second image area on the carrier is the same as the position of the area of ​​the second wafer corresponding to the first image area on the carrier, the second image area is basically the same as or most of its area is the same as the first image area. Therefore, the probability of finding the target chip in the second image area corresponding to the first image area where the reference chip is located is very high. Compared with the solution of searching for the target chip in the entire second image area, the time required to determine the target chip can be greatly shortened.

[0099] Further, searching for the target chip in the determined second image area according to the status information of each reference chip and the status information of the area adjacent to the side of each reference chip includes the following process:

[0100] If the target chip does not exist in the determined second image area, generating control information for adjusting the position of the second wafer on the chip pickup device, and reacquiring the second image after the position of the second wafer is adjusted;

[0101] The target chip is searched for in a second image area corresponding to the first image area where the reference chip is located in the re-acquired second image.

[0102] If the target area does not exist in the determined second image area, it can be determined that the position of the second wafer on the carrier has been deflected relative to the position of the first wafer on the carrier, and the target chip can be found in the second image area corresponding to the first image area where the reference chip is located in the re-acquired second image by adjusting the position of the second wafer on the carrier.

[0103] In one embodiment, after the processor generates control information for adjusting the position of the second wafer on the chip picking device, it can notify the operator to adjust the position of the second wafer by issuing a prompt sound, or it can also control the robot to adjust the position of the second wafer.

[0104] In step 160, second position information of a second reference chip of the second wafer in the second image is determined according to the position information of the target chip in the second image and the first relative position information.

[0105] In one embodiment, the position information of the reference chips in each wafer is the same, that is, the position information of the first reference chip in the first wafer is the same as the position information of the second reference chip in the second wafer.

[0106] In one embodiment, step 160 may include the following process:

[0107] First, the first relative position information is used as fourth relative position information between the target chip and the second reference chip;

[0108] Subsequently, second position information of the second reference chip in the image is determined according to the position information of the target chip in the second image and the fourth relative position information.

[0109] See also Figure 2 and Figure 4 , the relative position information between the first reference chip 119 and the reference chip 115 is the same as the relative position information between the second reference chip 114 and the target chip 213. The first relative position information is: the first reference chip 119 is located above the reference chip 115, and is separated from the reference chip 115 by seven rows of chips in the Y direction; the first reference chip 119 is located on the left side of the reference chip 115, and is separated from the reference chip 115 by six columns of chips in the X direction. The fourth relative position information is: the second reference chip is located above the target chip 213, and is separated from the target chip 213 by seven rows of chips in the Y direction; the second reference chip is located on the left side of the target chip 213, and is separated from the target chip 213 by six columns of chips in the X direction. According to the fourth relative position information and the position information of the target chip 213, it can be determined that the second reference chip is the chip 214.

[0110] In step 170, third position information of the qualified chip in the second image is determined according to the second position information and second relative position information between the qualified chip of the second wafer and the second reference chip, and control information for picking up the chip is generated according to the third position information.

[0111] In one embodiment, the processor may control the robot to obtain a qualified chip at the third position information according to control information for picking up the chip.

[0112] In one embodiment, before step 170, the method for picking up a chip further includes the following steps:

[0113] First, a layout drawing of the second wafer is obtained, wherein the identification of the qualified chip in the layout drawing is different from the identification of the defective chip;

[0114] Then, a second relative position relationship between the qualified chip and the second reference chip is determined according to the layout drawing.

[0115] The layout image of the second wafer can be pre-stored in the chip picking device, and each chip in the second wafer can be tested to determine whether each chip is a qualified chip or a defective chip, and each chip can be marked in the image of the second wafer to obtain the layout image of the second wafer. In the layout image of the second wafer, the mark of the qualified chip can be, for example, G, and the mark of the defective chip can be, for example, N. The processor can identify the mark of the chip in the layout image to determine whether each chip is a qualified chip or a defective chip.

[0116] The position information of the second reference chip in the layout file is known, and the second relative position relationship between the qualified chip and the second reference chip can be determined according to the identifier of the qualified chip.

[0117] In one embodiment, the second wafer includes a plurality of the qualified chips;

[0118] In one embodiment, the second wafer 20 includes a plurality of the qualified chips, and the step 170 may include the following process: for each of the qualified chips, according to the second position information and the second relative position information of the qualified chips of the second wafer and the second reference chip, determine the third position information of the qualified chip in the second image, and generate control information for picking up the qualified chip according to the third position information. In this way, the processor may control the robot to pick up all the qualified chips in the second wafer 20 according to the control information.

[0119] The embodiment of the present application also provides a chip picking device. Figure 5 is a hardware structure diagram of a chip pickup device provided by an exemplary embodiment of the present application, such as Figure 5 As shown, the chip picking device includes a stage (not shown), a camera 40, a manipulator 50 and a processor 60. The stage is used to place a wafer, the camera 40 is used to obtain an image of the wafer placed on the stage, the manipulator 50 is used to pick up a qualified chip from the wafer, and the processor 60 is used to execute the method for picking up a chip described in any of the above embodiments. The processor 60 is signal-connected to the camera 40 and the manipulator 50 respectively to send control signals to the camera 40 and the manipulator 50.

[0120] In one embodiment, Figure 5As shown, the chip picking device may also include a memory 70; the memory 70 stores a program that can be called by the processor 60; wherein when the processor 60 executes the program, the chip picking method described in any one of the above embodiments is implemented. Figure 5 In addition to the hardware structure shown, the chip pickup device in the embodiment may also include other structures according to its actual functions, which will not be described in detail.

[0121] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0122] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the disclosure disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0123] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for picking up a chip, characterized in that: Applied to a chip picking device, the method for picking up a chip comprises: Acquire a first image of a first wafer placed on the chip pickup device; the first wafer includes a plurality of chips arranged in an array, and adjacent chips are spaced apart; M reference chips are selected from the chips in the first image, and first position information of each of the reference chips in the first image is determined; wherein state information of adjacent areas of the M reference chips is not completely the same as state information of adjacent areas of any M chips in the first image that are not completely the same as the M reference chips and are arranged in the same manner; the state information includes whether a chip is provided and whether the chip is complete when a chip is provided; M is an integer greater than or equal to 2; Determine first relative position information between a first reference chip of the first wafer and the reference chip in the first image according to the first position information; Acquire a second image of a second wafer placed on the chip pickup device; the structure of the second wafer is the same as that of the first wafer; Determine M target chips in the second image according to the state information of each reference chip and the state information of an adjacent region of each reference chip, wherein the arrangement of the M target chips is the same as the arrangement of the M reference chips, and the state information of the adjacent regions of the M target chips is the same as the state information of the adjacent regions of the M reference chips; Determining second position information of a second reference chip of the second wafer in the second image according to the position information of the target chip in the second image and the first relative position information; The third position information of the qualified chip in the second image is determined according to the second position information and the second relative position information between the qualified chip of the second wafer and the second reference chip, and control information for picking up the chip is generated according to the third position information.

2. The method for picking up a chip according to claim 1, characterized in that: At least two of the M reference chips are located in different rows, and at least two of the reference chips are located in different columns; status information of areas adjacent to two sides of at least one reference chip is that there is no chip or there is an incomplete chip.

3. The method for picking up a chip according to claim 2, characterized in that: The at least two first chips located in the same row are adjacent to each other, and the at least two first chips located in the same column are adjacent to each other.

4. The method for picking up a chip according to claim 2, characterized in that: M is equal to three; and / or, the reference chip is a complete chip.

5. The method for picking up a chip according to claim 1, characterized in that: The determining, according to the first position information, first relative position information of the first reference chip of the first wafer and the reference chip in the first image includes: Determining third relative position information of the reference chip and the center of the first wafer in the first image according to the first position information; The first relative position information is determined according to the relative position information between the first reference chip and the center of the first wafer and the third relative position information.

6. The method for picking up a chip according to claim 1, characterized in that: The determining, according to the position information of the target chip in the second image and the first relative position information, second position information of the second reference chip of the second wafer in the second image comprises: Using the first relative position information as fourth relative position information between the target chip and the second reference chip; The second position information of the second reference chip in the image is determined according to the position information of the target chip in the second image and the fourth relative position information.

7. The method for picking up a chip according to claim 1, characterized in that: Before determining the third position information of the qualified chip in the second image according to the second position information and the second relative position information of the qualified chip of the second wafer and the second reference chip, and generating the control information for picking up the chip according to the third position information, the method for picking up the chip further includes: Obtaining a layout drawing of the second wafer; wherein the identification of the qualified chip in the layout drawing is different from the identification of the defective chip; A second relative position relationship between the qualified chip and the second reference chip is determined according to the layout drawing.

8. The method for picking up a chip according to claim 1, characterized in that: The second wafer includes a plurality of the qualified chips; The method of determining the third position information of the qualified chip in the second image according to the second position information and the second relative position information of the qualified chip of the second wafer and the second reference chip, and generating control information for picking up the chip according to the third position information, comprises: For each of the qualified chips, the third position information of the qualified chip in the second image is determined according to the second position information and the second relative position information between the qualified chip and the second reference chip, and control information for picking up the qualified chip is generated according to the third position information.

9. The method for picking up a chip according to claim 1, characterized in that: The first image includes a plurality of first image areas, and after selecting M reference chips from the chips in the first image, the chip picking method further includes: determining the first image areas where the M reference chips are located; The second image includes a plurality of second image areas, and a position of an area of ​​the second wafer corresponding to each of the second image areas on the chip pickup device is the same as a position of an area of ​​the second wafer corresponding to one of the first image areas on the chip pickup device; The determining M target chips in the second image according to the state information of each reference chip and the state information of the adjacent area of ​​each reference chip comprises: Determine a second image area corresponding to the first image area where the reference chip is located; The target chip is searched for in the determined second image area according to the status information of each reference chip and the status information of an adjacent area of ​​each reference chip.

10. The method for picking up a chip according to claim 9, characterized in that: The step of searching for the target chip in the determined second image area according to the state of each reference chip and the state of the area adjacent to the side of each reference chip comprises: If the target chip does not exist in the determined second image area, generating control information for adjusting the position of the second wafer on the chip pickup device, and reacquiring the second image after the position of the second wafer is adjusted; The target chip is searched for in a second image area corresponding to the first image area where the reference chip is located in the re-acquired second image.

11. A chip picking device, characterized in that: The chip picking device includes a carrier, a camera, a manipulator and a processor. The carrier is used to place a wafer, the camera is used to obtain an image of the wafer placed on the carrier, the manipulator is used to pick up a qualified chip from the wafer, and the processor is used to execute the chip picking method described in any one of claims 1 to 10.

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