Manufacturing method of deep groove isolation structure

Abstract

The invention discloses a manufacturing method of a deep trench isolation structure, which comprises the steps of providing a substrate, forming an STI structure in the substrate, forming a buried layer doped region below the STI structure in the substrate, observing from an overlook angle, enabling the STI structure to be of a net structure, enabling a region corresponding to each grid in the net structure to be an active region of a semiconductor device, and enabling the region corresponding to each grid in the net structure to be an active region of the semiconductor device; a semiconductor device is formed in the active region, the surface of the substrate, the surface of the STI structure and the surface of the semiconductor device are covered with a dielectric layer, an interlayer dielectric layer is formed on the dielectric layer, an etching stop layer is formed on the interlayer dielectric layer, and a hard mask layer is formed on the etching stop layer; etching is carried out through a photoetching process to form a deep groove, the bottom of the deep groove is lower than the buried layer doping region, and the deep groove is located in the STI structure and the width of the deep groove is smaller than the width of the STI structure when viewed from an overlook angle; forming a doped region in the substrate at the bottom of the deep trench; forming an oxide layer on the side wall of the region, located in the substrate, of the deep groove; and filling a metal layer in the deep groove.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices and integrated circuits, and in particular to a method for manufacturing a deep trench isolation structure. Background Art

[0002] As the critical dimension (CD) of semiconductor integrated circuit devices continues to shrink, deep trench isolation (DTI) structures (isolation structures with a depth-to-width ratio greater than 10) have been more widely used due to their more advanced isolation performance. Compared with PN junction (positive-negative junction) isolation, deep trench isolation structures have the advantages of higher breakdown voltage, higher reliability, and easier chip size reduction to increase the density of integrated circuits.

[0003] Generally, the manufacturing method of the deep trench isolation structure is: a deep trench is formed by etching in a substrate through a photolithography process, and then an oxide layer is formed on the surface of the deep trench through a thermal oxidation process, and then a silicon dioxide (SiO2) layer or a polysilicon layer is filled in the deep trench, and finally, the excess filling material is removed through a planarization process to form an isolation structure. However, since the deep trench isolation structure is manufactured in a shallow trench isolation (STI) structure, the process window for forming the deep trench isolation structure is small, and it is difficult to improve the yield; at the same time, due to the spacing between the deep trench isolation structures, it is difficult to reduce the size of the chip. Summary of the invention

[0004] The present application provides a method for manufacturing a deep trench isolation structure, which can solve the problem that the deep trench isolation structure provided in the related art is difficult to reduce the chip size. The method comprises:

[0005] A substrate is provided, wherein an STI structure is formed in the substrate, a buried doped region is formed below the STI structure in the substrate, the STI structure is a mesh structure when viewed from a top view, the region corresponding to each grid in the mesh structure is an active region of a semiconductor device, a semiconductor device is formed in the active region, a dielectric layer is covered on the surfaces of the substrate, an interlayer dielectric layer is formed on the dielectric layer, an etch stop layer is formed on the interlayer dielectric layer, and a hard mask layer is formed on the etch stop layer;

[0006] Etching is performed by a photolithography process to form a deep trench, wherein the bottom of the deep trench is lower than the buried layer doping region, and when viewed from a top view, the deep trench is located within the STI structure and the width of the deep trench is smaller than the width of the STI structure;

[0007] forming a doped region in the substrate at the bottom of the deep trench;

[0008] forming an oxide layer on the sidewalls of the deep trench in the substrate;

[0009] A metal layer is filled in the deep trench.

[0010] In some embodiments, etching by photolithography to form a deep trench includes:

[0011] covering the hard mask layer with a photoresist;

[0012] Removing the photoresist in the area corresponding to the deep groove by sequentially exposing and developing;

[0013] Performing a first etching until the substrate below the STI structure is exposed;

[0014] The photoresist is removed, and a second etching is performed to etch to a predetermined depth in the substrate to form the deep trench.

[0015] In some embodiments, forming an oxide layer on the sidewall of the deep trench in the substrate includes:

[0016] forming an oxide layer on the surface of the deep trench in the substrate;

[0017] The oxide layer at the bottom of the deep trench is removed by a dry etching process.

[0018] In some embodiments, filling the deep trench with a metal layer includes:

[0019] forming a metal layer, wherein the metal layer fills the deep trench;

[0020] A planarization process is performed to remove the metal layer outside the deep trench, the hard mask layer and the etch stop layer until the interlayer dielectric layer is exposed.

[0021] In some embodiments, the metal layer includes a tungsten layer.

[0022] In some embodiments, the interlayer dielectric layer and the hard mask layer include oxide layers.

[0023] In some embodiments, the etch stop layer and the dielectric layer include silicon nitride layers.

[0024] The technical solution of this application has at least the following advantages:

[0025] By setting the STI structure as an interconnected mesh structure, forming deep trenches in the STI structure to divide the pre-formed buried doped region, forming a doped region in the substrate at the bottom of the deep trench, forming an oxide layer on the peripheral side of the deep trench to achieve deep trench isolation, and then filling a metal layer in the deep trench to contact the doped region at the bottom of the device to lead out a ground electrode, since the deep trench isolation structures between adjacent active areas are shared for isolation, there is no spacing between the deep trench isolation structures, so that the size of the chip can be reduced; at the same time, since the buried doped region between each active area is divided by forming a deep trench isolation structure, there is no need to set up an additional photolithography process for ion implantation, thereby reducing the manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0027] Figure 1 is a cross-sectional schematic diagram of a deep trench isolation structure provided in the related art;

[0028] Figure 2 is a top view schematic diagram of a deep trench isolation structure provided in the related art;

[0029] Figure 3 is a flow chart of a method for manufacturing a deep trench isolation structure provided by an exemplary embodiment of the present application;

[0030] Figures 4 to 12 is a schematic diagram of a manufacturing process of a deep trench isolation structure provided by an exemplary embodiment of the present application;

[0031] Fig.13 1 is a schematic top view of a deep trench isolation structure provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0032] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0033] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0034] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0035] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0036] refer to Figure 1 , which shows a cross-sectional schematic diagram of a deep trench isolation structure provided in the related art; Figure 2 , which shows a top view of a deep trench isolation structure provided in the related art. Figure 1 and Figure 2 As shown, a STI structure 111 is formed in the substrate 110. When viewed from a top view, the STI structure 111 is annular, and the area 101 surrounded by it is the active area (AA) of the semiconductor device. A deep trench isolation structure 121 is formed in the STI structure 111. The depth of the deep trench isolation structure 121 is deeper than the STI structure 111 and the buried doped region 112. There is a gap between the STI structures 111. A doped region 113 is formed in the substrate 110 between the STI structures 111 for contacting with a contact hole formed subsequently for grounding. The buried doped region 112 in each active area 101 needs to be formed by ion implantation through a photolithography process. Since there is a gap between each STI structure 111 and the deep trench structure 121, it is difficult to reduce the size of the semiconductor device. At the same time, since the buried doped region 112 in each active area 101 needs to be formed by ion implantation through an additional photolithography process, its manufacturing cost is relatively high. In view of the above problems, the present application provides a method for manufacturing a deep trench structure, which is convenient for reducing the size of semiconductor devices and does not require additional photolithography processes to form buried doped regions, as follows:

[0037] refer to Figure 3 , which shows a flow chart of a method for manufacturing a deep trench isolation structure provided by an exemplary embodiment of the present application, such as Figure 3 As shown, the method includes:

[0038] Step S1, providing a substrate, in which an STI structure is formed, a buried doped region is formed below the STI structure in the substrate, the STI structure is a mesh structure when viewed from a top view, the region corresponding to each grid in the mesh structure is an active region of the semiconductor device, a semiconductor device is formed in the active region, the substrate, the STI structure and the semiconductor device are covered with a dielectric layer, an interlayer dielectric layer is formed on the dielectric layer, an etch stop layer is formed on the interlayer dielectric layer, and a hard mask layer is formed on the etch stop layer.

[0039] refer to Figure 4 , which shows a cross-sectional schematic diagram before forming a deep trench. Figure 4 As shown, an STI structure 211 is formed in the substrate 210, and a buried doped region 212 is formed below the STI structure 211 in the substrate 210. When viewed from a top view, the STI structure 211 is a mesh structure (i.e., the STI structures 211 are not independent ring structures, but are interconnected ring structures without spacing, and each active region uses the STI structure for isolation). The area corresponding to each grid in the mesh structure is the active region of the semiconductor device, and a semiconductor device (including a gate 230, a gate dielectric layer 221 between the gate 230 and the substrate 210, and a sidewall 222 around the gate 230) is formed in the active region. The surfaces of the substrate 210, the STI structure 211, and the semiconductor device are covered with a dielectric layer 241, an interlayer dielectric layer 251 is formed on the dielectric layer 241, an etch stop layer 242 is formed on the interlayer dielectric layer 251, and a hard mask layer 252 is formed on the etch stop layer 242.

[0040] Among them, the buried doped region 212 is formed by general ion implantation without the need for additional photolithography process for ion implantation; the STI structure 211, the gate dielectric layer 211, the sidewall 222, the interlayer dielectric layer 251 and the hard mask layer 252 include an oxide layer (for example, a silicon dioxide (SiO2) layer); the dielectric layer 241 and the etch stop layer 242 include a silicon nitride (Si3N4) layer.

[0041] Step S2, etching is performed by photolithography to form a deep trench, the bottom of which is lower than the buried layer doping region. From a top view, the deep trench is located in the STI structure and the width of the deep trench is smaller than the width of the STI structure.

[0042] Exemplarily, step S2 includes but is not limited to: covering the hard mask layer with photoresist; removing the photoresist in the area corresponding to the deep groove by sequentially exposing and developing; performing a first etching until the substrate under the STI structure is exposed; removing the photoresist, performing a second etching, etching to a predetermined depth in the substrate, and forming a deep groove.

[0043] refer to Figure 5 , which shows a cross-sectional schematic diagram after exposure and development. Figure 5 As shown, the hard mask layer 252 may be covered with a photoresist, and the photoresist in the region corresponding to the deep trench (the region is located within the STI structure 211 when viewed from a top view) may be removed through exposure and development in sequence.

[0044] refer to Figure 6 , which shows a cross-sectional schematic diagram after the first etching. Figure 6 As shown, the first etching stops below the STI structure 211 until the substrate 210 is exposed to form a trench 301 .

[0045] refer to Figure 7 , which shows a cross-sectional schematic diagram after the second etching. Figure 7 As shown, the second etching stops at a predetermined depth in the substrate 210 to form a deep trench 301. After the second etching, the photoresist 300 is removed. The depth of the deep trench 301 is deeper than the buried doped region 212. By forming the deep trench 302, the isolation of the buried doped regions of each active area is achieved, and no additional photolithography is required for ion implantation.

[0046] Step S3, forming a doped region in the substrate at the bottom of the deep trench.

[0047] refer to Figure 8 , which shows a cross-sectional schematic diagram after a doped region is formed in the substrate at the bottom of the deep trench. Figure 8 As shown, a doped region 213 may be formed in the substrate 210 at the bottom of the deep trench 302 by ion implantation (including annealing), and the doped region 213 may serve as a grounded electrode.

[0048] Step S4, forming an oxide layer on the sidewalls of the deep trench in the substrate.

[0049] Exemplarily, step S4 includes but is not limited to: forming an oxide layer on the surface of the region where the deep trench is located in the substrate; and removing the oxide layer at the bottom of the deep trench by a dry etching process.

[0050] refer to Fig. 9 , which shows a cross-sectional schematic diagram after an oxide layer is formed on the surface of the region where the deep trench is located in the substrate; Fig.10, which shows a cross-sectional schematic diagram after the oxide layer at the bottom of the deep trench is removed by a dry etching process. Fig. 9 and Fig.10 As shown, an oxide layer 223 may be formed on the surface of the deep trench 302 in the substrate 210 , and then the oxide layer 223 at the bottom of the deep trench 302 may be removed by dry etching, leaving the oxide layer 223 on the sidewall.

[0051] Step S5, filling the deep trench with a metal layer.

[0052] Exemplarily, step S5 includes but is not limited to: forming a metal layer, which fills the deep trench; performing a planarization process (for example, planarization can be performed by a chemical mechanical polishing (CMP) process) to remove the metal layer, hard mask layer and etch stop layer outside the deep trench until the interlayer dielectric layer is exposed.

[0053] refer to Fig.11 , which shows a cross-sectional schematic diagram after the metal layer is formed; refer to Fig.12 , which shows a schematic cross-sectional view after flattening. Fig.11 and Fig.12 As shown, the formed metal layer 260 fills the deep trench 302, and after planarization, the metal layer 260, the hard mask layer 252 and the etch stop layer 242 outside the deep trench 302 are removed, and the remaining metal layer 260 can be used as a contact hole (via) to lead out the ground electrode. Fig.13 As shown, the deep trench isolation structure provided by the present application removes the isolation spacing between active areas and realizes the lead-out of the ground electrode. The metal layer 260 may include a copper (Cu) layer, a tungsten (W) layer or an aluminum (Al) layer. When the metal layer 260 includes a tungsten layer, the metal layer 260 may be formed by a chemical vapor deposition (CVD) process.

[0054] In the embodiment of the present application, the conductivity types of the impurities doped into the buried doping region 213 and the doping region 213 are different. If the impurities doped into the buried doping region 213 are N (negative) type impurities, the impurities doped into the doping region 213 are P (positive) type impurities; if the impurities doped into the buried doping region 213 are P type impurities, the impurities doped into the doping region 213 are N type impurities.

[0055] To summarize, in the embodiment of the present application, by setting the STI structure as an interconnected mesh structure, deep trenches are formed in the STI structure to divide the pre-formed buried doped region, a doped region is formed in the substrate at the bottom of the deep trench, an oxide layer is formed on the peripheral side of the deep trench to achieve deep trench isolation, and then a metal layer is filled in the deep trench to lead out the ground electrode to the doped region at the bottom of the contactor. Since the deep trench isolation structures between adjacent active areas are shared with each other for isolation, there is no spacing between the deep trench isolation structures, thereby reducing the size of the chip; at the same time, since the buried doped region between each active area is divided by forming a deep trench isolation structure, there is no need to set up an additional photolithography process for ion implantation, thereby reducing the manufacturing cost.

[0056] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for manufacturing a deep trench isolation structure, characterized in that: include: A substrate is provided, wherein an STI structure is formed in the substrate, a buried doped region is formed below the STI structure in the substrate, the STI structure is a mesh structure when viewed from a top view, the region corresponding to each grid in the mesh structure is an active region of a semiconductor device, a semiconductor device is formed in the active region, a dielectric layer is covered on the surfaces of the substrate, an interlayer dielectric layer is formed on the dielectric layer, an etch stop layer is formed on the interlayer dielectric layer, and a hard mask layer is formed on the etch stop layer; Etching is performed by a photolithography process to form a deep trench, wherein the bottom of the deep trench is lower than the buried layer doping region, and when viewed from a top view, the deep trench is located within the STI structure and the width of the deep trench is smaller than the width of the STI structure; forming a doped region in the substrate at the bottom of the deep trench; forming an oxide layer on the sidewalls of the deep trench in the substrate; A metal layer is filled in the deep trench.

2. The method according to claim 1, characterized in that The etching is performed by a photolithography process to form a deep trench, comprising: covering the hard mask layer with a photoresist; Removing the photoresist in the area corresponding to the deep groove by sequentially exposing and developing; Performing a first etching until the substrate below the STI structure is exposed; The photoresist is removed, and a second etching is performed to etch to a predetermined depth in the substrate to form the deep trench.

3. The method according to claim 2, characterized in that The step of forming an oxide layer on the sidewall of the deep trench in the substrate includes: forming an oxide layer on the surface of the deep trench in the substrate; The oxide layer at the bottom of the deep trench is removed by a dry etching process.

4. The method according to claim 3, characterized in that The step of filling the deep trench with a metal layer comprises: forming a metal layer, wherein the metal layer fills the deep trench; A planarization process is performed to remove the metal layer outside the deep trench, the hard mask layer and the etch stop layer until the interlayer dielectric layer is exposed.

5. The method according to any one of claims 1 to 4, characterized in that: The metal layer includes a tungsten layer.

6. The method according to claim 5, characterized in that The interlayer dielectric layer and the hard mask layer include oxide layers.

7. The method according to claim 6, characterized in that The etch stop layer and the dielectric layer include silicon nitride layers.

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