Preparation method of semiconductor structure

Abstract

The invention relates to a preparation method of a semiconductor structure, and the method comprises the steps: providing a substrate which is provided with a plurality of grooves; forming an isolation dielectric layer in the groove and on the substrate, wherein the surface, deviating from the substrate, of the isolation dielectric layer is provided with a concave region and a convex part; forming an isolation dielectric layer in the groove and on the substrate, wherein the surface, deviating from the substrate, of the isolation dielectric layer is provided with a concave region and a convex part; annealing is carried out on the isolation dielectric layer and the covering layer; and removing the covering layer and a part of the isolation dielectric layer by adopting a chemical mechanical polishing process, and forming a shallow trench isolation structure in the trench. According to the method provided by the invention, the surfaces of the shallow trench isolation structures finally formed in different regions of the substrate are kept flat (the height difference of different shallow trench isolation structures is eliminated).

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure. Background Art

[0002] With the booming development of integrated circuits today, the miniaturization and integration of components is an inevitable trend and an important topic that all sectors are actively developing. As the size of components gradually decreases and the degree of integration gradually increases, the isolation structure between components must also be reduced, so the difficulty of component isolation technology is gradually increasing.

[0003] The commonly used isolation structures include Local Oxidation of Silicon (LOCOS) and Shallow Trench Isolation (STI). Shallow Trench Isolation is widely used in process nodes of 0.18μm and below because of its advantages of reducing the occupied wafer surface area, increasing device integration, maintaining wafer surface flatness, and less channel width erosion.

[0004] However, the shallow trench isolation structure formed by the existing process may have unevenness in different regions, which affects the isolation performance of the shallow trench isolation structure and affects the subsequent processes. Summary of the invention

[0005] Based on this, the present application provides a method for preparing a semiconductor structure, so as to keep the surface of the shallow trench isolation structure formed in different regions of the substrate flat.

[0006] In a first aspect, an embodiment of the present application provides a method for preparing a semiconductor structure, comprising:

[0007] Providing a substrate having a plurality of grooves therein;

[0008] forming an isolation dielectric layer in the groove and on the substrate, wherein a surface of the isolation dielectric layer facing away from the substrate has a recessed area and a raised portion;

[0009] A cover layer is formed on a surface of the isolation dielectric layer away from the substrate by a spin coating process, wherein the cover layer fills the recessed area and covers the raised portion, and a surface of the cover layer away from the substrate is a flat surface;

[0010] Annealing the isolation dielectric layer and the cover layer;

[0011] The cover layer and part of the isolation dielectric layer are removed by chemical mechanical polishing process to form a shallow trench isolation structure in the trench.

[0012] In some embodiments of the present application, the annealing is performed to reduce the difference between the hardness and / or density of the isolation dielectric layer and the hardness and / or density of the cover layer.

[0013] In some embodiments of the present application, the annealing temperature ranges from 900 degrees Celsius to 1500 degrees Celsius, and the annealing time ranges from 20 minutes to 40 minutes.

[0014] In some embodiments of the present application, after the annealing, the ratio of the hardness of the cover layer to the hardness of the isolation dielectric layer is in the range of 0.9-1.1.

[0015] In some embodiments of the present application, after the annealing, the ratio of the density of the capping layer to the density of the isolation dielectric layer is in a range of 0.9-1.1.

[0016] In some embodiments of the present application, after the annealing, the ratio of the hardness of the covering layer to the hardness of the isolation dielectric layer is in the range of 0.9-1.1, and the ratio of the density of the covering layer to the density of the isolation dielectric layer is in the range of 0.9-1.1.

[0017] In some embodiments of the present application, a vertical distance between a highest point and a lowest point of the cover layer away from the surface of the substrate is less than 50 nanometers.

[0018] In some embodiments of the present application, the material of the isolation dielectric layer is silicon oxide, and the material of the cover layer is silicon glass.

[0019] In some embodiments of the present application, it also includes: a stop layer located on the substrate, the stop layer having a plurality of openings corresponding to the grooves, the material of the stop layer being different from the materials of the isolation dielectric layer and the covering layer; forming the isolation dielectric layer in the groove and on the substrate includes: forming the isolation dielectric layer in the groove, in the openings and on the surface of the stop layer facing away from the substrate.

[0020] In some embodiments of the present application, a chemical mechanical polishing process is used to remove the cover layer and a portion of the isolation dielectric layer, and the stop layer is used as a polishing stop layer to form a shallow trench isolation structure in the trench.

[0021] The embodiments of the present application may or at least have the following advantages:

[0022] In the method for preparing a semiconductor structure in the embodiment of the present application, after forming an isolation dielectric layer in the groove and on the substrate, a spin coating process is used to form a covering layer on the surface of the isolation dielectric layer away from the substrate; after forming the covering layer by the spin coating process, the isolation dielectric layer and the covering layer are annealed; and the covering layer and a portion of the isolation dielectric layer are removed by a chemical mechanical polishing process to form a shallow trench isolation structure in the groove. The covering layer is formed by the spin coating process. Since the spin coating process has good hole filling ability and the material of the covering layer itself has good fluidity, the formed covering layer can better fill the recessed area on the surface of the isolation dielectric layer and cover the raised part on the surface of the isolation dielectric layer, and the surface of the formed covering layer away from the substrate is a flat surface. Moreover, after forming the covering layer by the spin coating process, the isolation dielectric layer and the covering layer need to be annealed to reduce the difference between the hardness and / or density of the isolation dielectric layer and the hardness and / or density of the covering layer, so that the chemical mechanical polishing process is used to remove the covering layer. When a shallow trench isolation structure is formed in the groove, the covering layer and part of the isolation dielectric layer prevent the different unevenness of the surface of the isolation dielectric layer and the difference in hardness and / or density between the covering layer and the isolation dielectric layer from affecting the grinding rate, thereby reducing the difference in grinding rates of the covering layer and / or the isolation dielectric layer in different areas during the chemical mechanical grinding process, so that the grinding rates of the covering layer and / or the isolation dielectric layer in different areas during the chemical mechanical grinding process can be kept consistent or very close, so that the surface of the shallow trench isolation structure finally formed in different areas of the substrate remains flat (eliminating the height difference between different shallow trench isolation structures).

[0023] The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1-Figure 3 The cross-sectional structure schematic diagram of each stage in the preparation method of a shallow trench isolation structure provided by the present application, wherein: Figure 1 To provide a schematic diagram of the cross-sectional structure after the substrate is provided, Figure 2 is a schematic diagram of the cross-sectional structure after an isolation dielectric layer is formed in the trench and on the substrate. Figure 3 is a schematic diagram of the structure after the isolation dielectric layer is planarized;

[0026] Figure 4-Figure 7 The cross-sectional structure diagrams of various stages in the method for preparing a semiconductor structure provided in some embodiments of the present application, wherein: Figure 4 To provide a schematic diagram of the cross-sectional structure after the substrate is provided, Figure 5 is a schematic diagram of the cross-sectional structure after an isolation dielectric layer is formed in the trench and on the substrate. Figure 6 It is a schematic diagram of the cross-sectional structure after a covering layer is formed on the surface of the isolation dielectric layer away from the substrate by a spin coating process. Figure 7 This is a schematic diagram of the structure after the cover layer and part of the isolation dielectric layer are removed by chemical mechanical polishing process.

[0027] Description of reference numerals:

[0028] 101-substrate; 102-buffer layer; 103-groove; 104-opening; 105-isolation dielectric layer; 106-shallow trench isolation structure; 107-stop layer;

[0029] 201 - substrate; 202 - buffer layer; 203 - trench; 204 - opening; 205 - isolation dielectric layer; 206 - cover layer; 207 - stop layer; 208 - shallow trench isolation structure. DETAILED DESCRIPTION

[0030] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0032] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0033] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0034] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0035] The structure of the embodiments of the present invention should not be limited to the specific shapes shown in the drawings of the specification, but includes shape deviations due to, for example, manufacturing technology.

[0036] It can be understood that in the drawings of the present application, some adjacent film layers with the same processed film material are drawn to be connected to make them close to the actual structure.

[0037] During the preparation of the shallow trench isolation structure, the shallow trench isolation structures formed in different areas of the wafer or substrate may be uneven. For example, the surface of the shallow trench isolation structure in a certain area may be higher or lower than the surface of the shallow trench isolation structure in another area, and there is an obvious height difference between the two surfaces. Specifically, Figure 1-Figure 3 The cross-sectional structure schematic diagram of each stage in a method for preparing a shallow trench isolation structure provided in the present application, the method for preparing the shallow trench isolation structure comprises: referring to Figure 1 , providing a substrate 101, the substrate 101 has a plurality of grooves 103, the substrate 101 may also have a buffer layer 102 and a stop layer 107 located on the buffer layer 102, the buffer layer 102 and the stop layer 107 have openings 104 corresponding to the grooves 103; referring to Figure 2 , an isolation dielectric layer 105 is formed in the groove 103 and on the substrate 101, and the surface of the isolation dielectric layer 105 facing away from the substrate 101 is uneven. The specific reason for the unevenness is that since there are a plurality of grooves 103 in the substrate 101, and the density of the grooves 103 in different regions is different, when the chemical mechanical polishing process is used to isolate the dielectric layer 105, the surface of the isolation dielectric layer 105 in the region with the grooves 103 facing away from the substrate 101 will be concave downward, and the surface of the isolation dielectric layer 105 in the region without the grooves facing away from the substrate 101 will be convex upward, and since the distribution density of the grooves 103 in different regions is different, the number of depressions on the surface of the isolation dielectric layer 105 facing away from the substrate 101 in different regions will be different, and the height of the convex upward of the surface of the isolation dielectric layer 105 facing away from the substrate 101 in different regions will also be different; refer to Figure 3 , the isolation dielectric layer 105 is planarized by a chemical mechanical polishing process, and the stop layer 107 is used as a polishing stop layer to form a shallow trench isolation structure 106 in the trench. During the chemical mechanical polishing process, due to the different unevenness of the surface of the isolation dielectric layer 105 away from the substrate 101, the polishing rates of different regions will be different, so that the shallow trench isolation structures 106 formed in different regions will have unevenness problems, such as Figure 3 As shown in FIG. 1 , for example, the surface of the shallow trench isolation structure 106 on the left and the middle is lower than the surface of the shallow trench isolation structure 106 on the right.

[0038] To this end, the embodiment of the present application provides a method for preparing a semiconductor structure, after forming an isolation dielectric layer in the groove and on the substrate, a cover layer is formed on the surface of the isolation dielectric layer away from the substrate by a spin coating process; after forming the cover layer by a spin coating process, the isolation dielectric layer and the cover layer are annealed; a chemical mechanical polishing process is used to remove the cover layer and part of the isolation dielectric layer to form a shallow trench isolation structure in the groove. This method can prevent the different concavities and convexities on the surface of the isolation dielectric layer from affecting the polishing rate of different areas, so that the polishing rate of different areas by the chemical mechanical polishing process can be kept consistent or very small, so that the surface of the shallow trench isolation structure finally formed in different areas of the substrate remains flat (eliminating the height difference of different shallow trench isolation structures).

[0039] The specific process of the method for preparing the semiconductor structure is described in detail below with reference to the accompanying drawings. Figure 4-Figure 7 Schematic diagram of the cross-sectional structure of each stage in the method for preparing a semiconductor structure provided in some embodiments of the present application.

[0040] refer to Figure 4 , providing a substrate 201 having a plurality of grooves 203 therein.

[0041] The material of the substrate 201 may be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it may also be silicon on insulator (SOI), germanium on insulator (GOI); or it may also be other materials, such as III-V compounds such as gallium arsenide. Certain doping ions may also be injected into the substrate 201 according to design requirements to change electrical parameters.

[0042] The substrate 201 has a plurality of grooves 203, and the depths of the grooves 203 are the same. In some embodiments, the substrate 201 may include different regions, and the densities of the grooves 203 formed in different regions are different. In a specific example, the substrate 201 may include at least one first region and at least one second region, the substrate 201 in the first region has a plurality of grooves 203, the substrate 201 in the second region has at least one groove 203, and the density of the grooves 203 in the substrate 201 in the first region is greater than the density of the grooves 203 in the substrate 201 in the second region. It should be noted that the density of the grooves 203 is the number of grooves 203 per unit area, or the area occupied by the grooves 203 per unit area.

[0043] In some embodiments, the substrate 201 also has a buffer layer 102 and a stop layer 207 located on the buffer layer 102. The buffer layer 202 is used to reduce the stress between the stop layer 207 and the substrate 201. The stop layer 207 serves as a grinding stop layer when an isolation dielectric layer is subsequently planarized using a chemical mechanical mask process. The buffer layer 202 and the stop layer 207 also have openings 204 corresponding to the grooves 203. In some embodiments, the formation process of the groove 203 includes: sequentially forming a buffer layer 202 and a stop layer 207 on the substrate 201, the material of the buffer layer 202 is different from the material of the stop layer 207, and the material of the stop layer 207 is different from the material of the isolation dielectric layer formed subsequently. In a specific example, the material of the buffer layer 202 may be silicon oxide, and the material of the stop layer 207 may be silicon nitride; forming a patterned photoresist layer (not shown in the figure) on the stop layer 207; using the patterned photoresist layer as a mask, etching the stop layer 207, the buffer layer 202 and the substrate 201 at one time, forming an opening 204 in the stop layer 207 and the buffer layer 202, and forming a groove 203 connected to the opening 204 in the substrate 201. In a specific example, the etching may adopt an anisotropic plasma etching process.

[0044] refer to Figure 5 An isolation dielectric layer 205 is formed in the groove 203 and on the substrate 201 , and a surface of the isolation dielectric layer 205 facing away from the substrate 201 has a recessed area 20 and a raised portion 21 .

[0045] The isolation dielectric layer 205 serves as the main structure of the shallow trench isolation structure formed subsequently. In some embodiments, the material of the isolation dielectric layer 205 includes silicon oxide, and the process of forming the isolation dielectric layer 205 can be a chemical vapor deposition process, and the chemical vapor deposition process can be a low pressure chemical vapor deposition process (LPCVD) or a plasma enhanced chemical vapor deposition process (PECVD), and the silicon source gas used in the chemical vapor deposition process includes tetraethylorthosilicate (TEOS) or SiH4, and the oxygen source gas includes O2 or O3.

[0046] In some embodiments, when a stop layer 207 is provided on the substrate 201 , the isolation dielectric layer 205 fills the opening 204 in the stop layer 207 and covers the surface of the stop layer 207 facing away from the substrate 201 in addition to filling the trench 203 .

[0047] When the isolation dielectric layer 205 is formed by chemical vapor deposition, since the substrate 201 has a plurality of grooves 203 and the density of the grooves 203 in different regions may be different, the surface of the isolation dielectric layer 205 formed away from the substrate 201 has depressions 20 and protrusions 21, that is, it is uneven. Specifically, the position of the depression 20 corresponds to the position of the grooves 203, and the protrusions 21 are between adjacent depressions 20. Moreover, since the density of the grooves 203 in different regions is different, the heights of the protrusions 21 in different regions will also be different. For example, the height of the protrusions 21 in the region with a high density of the grooves 203 will be smaller.

[0048] refer to Figure 6 A cover layer 206 is formed on the surface of the isolation dielectric layer 205 away from the substrate 201 by a spin coating process, and the cover layer 206 fills the recessed area 20 (reference Figure 5 ) and covers the raised portion 21 (reference Figure 5 ), the surface of the cover layer 206 facing away from the substrate 201 is a flat surface; the isolation dielectric layer 205 and the cover layer 206 are annealed.

[0049] In the present application, the cover layer 206 is formed by a spin coating process. Since the spin coating process has a good hole filling ability and the material of the cover layer 206 itself has good fluidity, the cover layer 206 can be formed to fill the recessed area 20 on the surface of the isolation dielectric layer 205 (refer to Figure 5 ) and covers the raised portion 21 on the surface of the isolation dielectric layer 205 (reference Figure 5 ), and the surface of the formed covering layer 206 facing away from the substrate is a flat surface, and after the covering layer 206 is formed by the spin coating process, the isolation dielectric layer 205 and the covering layer 206 need to be annealed to reduce the difference between the hardness and / or density of the isolation dielectric layer 205 and the hardness and / or density of the covering layer 206, so that the covering layer 206 and part of the isolation dielectric layer 205 are removed by the chemical mechanical polishing process, and a shallow trench isolation structure 208 is formed in the trench 203 (refer to Figure 7), thereby preventing the different unevenness of the surface of the isolation dielectric layer 205 and the difference in hardness and / or density between the covering layer 206 and the isolation dielectric layer 205 from affecting the grinding rate, thereby reducing the difference in grinding rates of the covering layer 206 and / or the isolation dielectric layer 205 in different areas during the chemical mechanical grinding process, so that the grinding rates of the covering layer 206 and / or the isolation dielectric layer 205 in different areas during the chemical mechanical grinding process can be kept consistent or very close, so that the surface of the shallow trench isolation structure 208 finally formed in different areas of the substrate 201 remains flat (eliminating the height difference between different shallow trench isolation structures 208).

[0050] Through the annealing, the solvent in the covering layer 206 is evaporated, so that the covering layer 206 is solidified, and the unsaturated or free oxygen bonds (O-) in the isolation dielectric layer 205 are converted into silicon oxygen bonds (Si-O), so that the hardness and density of the isolation dielectric layer 205 are increased, thereby reducing the difference between the hardness and / or density of the isolation dielectric layer 205 and the hardness and / or density of the covering layer 206.

[0051] In some embodiments, the material of the cover layer 206 is silicon glass, the annealing temperature range is 900 degrees Celsius-1500 degrees Celsius, specifically 900 degrees Celsius, 1000 degrees Celsius, 1100 degrees Celsius, 1200 degrees Celsius, 1300 degrees Celsius, 1400 degrees Celsius, 1500 degrees Celsius, and the annealing time range is 20 minutes-40 minutes, specifically 20 minutes, 25 minutes, 30 minutes, 35 minutes, 40 minutes. Under the specific annealing process parameters, the cover layer 206 can be better solidified, so that the cover layer 206 can maintain a certain hardness and density, and the hardness and density of the isolation dielectric layer 205 can be better increased, so that the difference between the hardness and / or density of the isolation dielectric layer 205 and the hardness and / or density of the cover layer 206 can be better reduced.

[0052] In some embodiments, the annealing is performed to reduce the difference between the hardness and / or density of the isolation dielectric layer 205 and the hardness and / or density of the covering layer 206, which specifically includes: the annealing is performed to reduce the difference between the hardness of the isolation dielectric layer 205 and the hardness of the covering layer 206; or the annealing is performed to reduce the difference between the density of the isolation dielectric layer 205 and the density of the covering layer 206; or the annealing is performed to reduce the difference between the hardness and density of the isolation dielectric layer 205 and the hardness and density of the covering layer 206.

[0053] In some embodiments, after the annealing, the ratio of the hardness of the cover layer to the hardness of the isolation dielectric layer is in the range of 0.9-1.1, and specifically may be 0.9, 1.0, or 1.1.

[0054] In some embodiments, after the annealing, the ratio of the density of the cover layer to the density of the isolation dielectric layer is in the range of 0.9-1.1, and specifically may be 0.9, 1.0, or 1.1.

[0055] In some embodiments, after the annealing, the ratio of the hardness of the covering layer to the hardness of the isolation dielectric layer is in the range of 0.9-1.1, specifically 0.9, 1.0, 1.1, and the ratio of the density of the covering layer to the density of the isolation dielectric layer is in the range of 0.9-1.1, specifically 0.9, 1.0, 1.1.

[0056] In some embodiments, the surface of the covering layer 206 formed by the spin coating process that is away from the substrate 201 is a flat surface. Specifically, the vertical distance between the highest point and the lowest point of the surface of the covering layer 206 that is away from the substrate 201 is less than 50 nanometers, for example, less than 50nm, less than 40nm, less than 30nm, less than 20nm, less than 15nm, less than 10nm, or less than 5nm.

[0057] refer to Figure 7 , the cover layer 206 is removed by chemical mechanical polishing process (refer to Figure 6 ) and part of the isolation dielectric layer 205, a shallow trench isolation structure 208 is formed in the trench 203.

[0058] When a stop layer 207 is provided on the substrate 201 , when a chemical mechanical polishing process is used to remove the cover layer 206 and a portion of the isolation dielectric layer 205 , the stop layer 207 is used as a polishing stop layer to form the shallow trench isolation structure 208 in the trench 203 .

[0059] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0060] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0061] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate having a plurality of grooves therein; forming an isolation dielectric layer in the groove and on the substrate, wherein a surface of the isolation dielectric layer facing away from the substrate has a recessed area and a raised portion; A cover layer is formed on a surface of the isolation dielectric layer away from the substrate by a spin coating process, wherein the cover layer fills the recessed area and covers the raised portion, and a surface of the cover layer away from the substrate is a flat surface; Annealing the isolation dielectric layer and the cover layer; The cover layer and part of the isolation dielectric layer are removed by chemical mechanical polishing process to form a shallow trench isolation structure in the trench.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: Through the annealing, the difference between the hardness and / or density of the isolation dielectric layer and the hardness and / or density of the cover layer is reduced.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The annealing temperature ranges from 900 degrees Celsius to 1500 degrees Celsius, and the annealing time ranges from 20 minutes to 40 minutes.

4. The method for preparing a semiconductor structure according to claim 2, characterized in that: After the annealing, the ratio of the hardness of the cover layer to the hardness of the isolation dielectric layer is in the range of 0.9-1.

1.

5. The method for preparing a semiconductor structure according to claim 2, characterized in that: After the annealing, the ratio of the density of the cover layer to the density of the isolation dielectric layer is in the range of 0.9-1.

1.

6. The method for preparing a semiconductor structure according to claim 2, characterized in that: After the annealing, the ratio of the hardness of the cover layer to the hardness of the isolation dielectric layer is in the range of 0.9-1.1, and the ratio of the density of the cover layer to the density of the isolation dielectric layer is in the range of 0.9-1.

1.

7. The method for preparing a semiconductor structure according to claim 2, characterized in that: A vertical distance between a highest point and a lowest point of the cover layer facing away from the substrate is less than 50 nanometers.

8. The method for preparing a semiconductor structure according to claim 1 or 2, characterized in that: The material of the isolation dielectric layer is silicon oxide, and the material of the cover layer is silicon glass.

9. The method for preparing a semiconductor structure according to claim 1 or 2, characterized in that: Also includes: A stop layer located on the substrate, the stop layer having a plurality of openings corresponding to the grooves, the material of the stop layer being different from the materials of the isolation dielectric layer and the cover layer; Forming an isolation dielectric layer in the trench and on the substrate includes: forming the isolation dielectric layer in the trench, in the opening, and on a surface of the stop layer facing away from the substrate.

10. The method for preparing a semiconductor structure according to claim 1, characterized in that: The cover layer and part of the isolation dielectric layer are removed by a chemical mechanical polishing process, and the stop layer is used as a polishing stop layer to form a shallow trench isolation structure in the trench.

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