Method for preparing CMOS (Complementary Metal Oxide Semiconductor) device by utilizing quasi-vertical gallium nitride and diamond and application

Abstract

The invention provides a method for preparing a CMOS (Complementary Metal Oxide Semiconductor) device by utilizing quasi-vertical gallium nitride and diamond and application. The method comprises the following steps: (1) preparing Cu-Pads on the surfaces of a planar p-diamond MOSFET wafer and a quasi-vertical GaN MOSFET wafer respectively so as to obtain a planar p-diamond MOSFET device containing a first Cu-Pads and a quasi-vertical GaN MOSFET device containing a second Cu-Pads; and (2) aligning the first Cu-Pads and the second Cu-Pads oppositely, and carrying out Cu-Cu bonding connection at a preset temperature and a preset pressure so as to obtain the gallium nitride diamond CMOS device. According to the method provided by the invention, different devices can be separately manufactured, and the technical problem of epitaxy of the GaN film on the diamond substrate is avoided, so that the production difficulty and cost can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a method and application of preparing a CMOS device by using quasi-vertical gallium nitride and diamond, and in particular to a method and application of preparing a CMOS device by using Cu-Cu bonding to integrate quasi-vertical gallium nitride and diamond. Background Art

[0002] CMOS (Complementary Metal-Oxide-Semiconductor) devices are core components of modern electronic technology and are widely used in various electronic devices. The core of CMOS circuits is to use the complementary characteristics of P-type MOSFET and N-type MOSFET to realize logical functions. It is currently the most widely used integrated circuit technology. Almost all modern microprocessors, microcontrollers, memory chips and various other integrated circuits are manufactured using CMOS technology.

[0003] Among them, silicon-based materials are widely used in CMOS devices due to their excellent electrical properties, thermal stability and mature manufacturing processes. They are characterized by low cost, high integration, and miniaturization. However, silicon-based materials also have their shortcomings: 1) Silicon-based CMOS devices have low thermal conductivity and are prone to performance degradation and failure at high temperatures; 2) The physical properties of silicon materials limit the application of high frequency and high power.

[0004] With the development of technology, gallium nitride (GaN) materials and diamond materials have also been applied to CMOS devices. Gallium nitride diamond CMOS devices (GaN diamond CMOS devices) are semiconductor devices that combine gallium nitride (GaN) and diamond materials, and are compatible with complementary metal oxide semiconductor (CMOS) processes. This device utilizes the excellent electrical properties of GaN materials and the efficient heat dissipation performance of diamond materials, aiming to achieve high-performance, high-power density and high-reliability electronic devices. However, there are very large technical bottlenecks in growing high-quality GaN films on diamond substrates. In addition, the process flow for preparing GaN diamond CMOS is complicated, the device preparation cost is high, and the product yield is low, which limits its large-scale application. Summary of the invention

[0005] The present invention aims to solve at least one of the technical problems in the related art to a certain extent. The present invention proposes a method for preparing a gallium nitride diamond CMOS device using a Cu-Cu bonding process, and the method provided is to connect the metal pads of a quasi-vertical GaNMOSFET device and the metal pads of a planar p-diamond MOSFET device together through high temperature and external pressure to form a gallium nitride diamond CMOS device. The provided method can combine the high electron mobility, high breakdown voltage and high frequency characteristics of GaN with the extremely high thermal conductivity, high breakdown voltage and chemical inertness of diamond to prepare a CMOS device with ultra-high power density, ultra-high energy conversion efficiency, high thermal stability and high frequency and high power at the same time.

[0006] Specifically, the present invention provides the following technical solutions:

[0007] In a first aspect of the present invention, a method for preparing a gallium nitride diamond CMOS device is provided, comprising:

[0008] (1) preparing Cu-Pads on the surface of a planar p-diamond MOSFET wafer to obtain a planar p-diamond MOSFET device containing the first Cu-Pads;

[0009] Preparing Cu-Pads on the surface of the quasi-vertical GaN MOSFET wafer to obtain a quasi-vertical GaN MOSFET device containing a second Cu-Pads;

[0010] (2) Aligning the first Cu-Pads of the planar p-diamond MOSFET device containing the first Cu-Pads and the second Cu-Pads of the quasi-vertical GaN MOSFET device containing the second Cu-Pads toward each other, and performing Cu-Cu bonding connection at a predetermined temperature and a predetermined pressure to obtain a gallium nitride diamond CMOS device.

[0011] According to an embodiment of the present invention, step (2) further comprises:

[0012] (2-1) The first Cu-Pads of the planar p-diamond MOSFET device containing the first Cu-Pads and the second Cu-Pads of the quasi-vertical GaN MOSFET device containing the second Cu-Pads are aligned toward each other, and a pressure of 50 N / cm3 is applied under the protection of an inert gas at a vacuum pressure of 0.1 Pa to 0.5 Pa. 2 ~150N / cm 2 The Cu-Cu bonding is performed by applying a pressure and heating at a temperature of 200 to 400°C for 20 to 50 minutes;

[0013] (2-2) Annealing is performed, and then the bonded product is heated at a temperature of 200 to 400° C. for 40 to 100 minutes under the protection of an inert gas.

[0014] According to an embodiment of the present invention, the step (1) of preparing Cu-Pads on the surface of a planar p-diamond MOSFET wafer to obtain a planar p-diamond MOSFET device containing first Cu-Pads comprises:

[0015] (1-1) growing a dielectric layer on the surface of a planar p-diamond MOSFET wafer by oxide deposition or polymer spin coating;

[0016] (1-2) etching the dielectric layer to form vertical metal connection holes at the metal pads of the planar p-diamond MOSFET wafer;

[0017] (1-3) continuing to perform etching on the dielectric layer to remove a portion of the dielectric layer so as to form a pattern in the dielectric layer;

[0018] (1-4) depositing Ti and Cu on the entire surface of the planar p-diamond MOSFET wafer containing the pattern close to the pattern side to form a Ti layer and a Cu layer, wherein the Ti layer and the Cu layer are distributed in the dielectric layer, the Cu layer is located on the surface of the Ti layer, and the surface of the formed Cu layer is polished;

[0019] (1-5) repeating the above steps (1-1) to (1-4) to obtain a planar p-diamond MOSFET device containing the first Cu-Pads;

[0020] The step (1) of preparing Cu-Pads on the surface of the quasi-vertical GaN MOSFET wafer to obtain a quasi-vertical GaN MOSFET device containing a second Cu-Pads comprises:

[0021] (1-a) growing a dielectric layer on the surface of the quasi-vertical GaN MOSFET wafer by polymer spin coating;

[0022] (1-b) etching the dielectric layer to form vertical metal connection holes at the metal pads of the quasi-vertical GaN MOSFET wafer;

[0023] (1-c) continuing to perform etching on the dielectric layer to remove a portion of the dielectric layer so as to form a pattern in the dielectric layer;

[0024] (1-d) depositing Ti and Cu on the entire surface of the quasi-vertical GaN MOSFET wafer including the pattern close to the pattern side to form a Ti layer and a Cu layer, wherein the Ti layer and the Cu layer are distributed in the dielectric layer, the Cu layer is located on the surface of the Ti layer, and the surface of the formed Cu layer is polished;

[0025] (1-e) Repeat the above steps (1-a) to (1-d) to obtain quasi-vertical GaN MOSFET devices containing the second Cu-Pads.

[0026] According to an embodiment of the present invention, the thickness of the dielectric layer is 2 to 6 micrometers.

[0027] According to an embodiment of the present invention, the oxide is selected from at least one of silicon dioxide, hafnium dioxide, aluminum oxide, and silicon nitride.

[0028] According to an embodiment of the present invention, the polymer is selected from at least one of polyimide, benzocyclobutene, polybenzo-bisoxazole and fluorinated aromatic AL-X 2010.

[0029] According to an embodiment of the present invention, the surface roughness Ra of the Cu surface after polishing is less than 1.0 nm.

[0030] According to an embodiment of the present invention, the polishing process is performed by chemical mechanical polishing.

[0031] According to an embodiment of the present invention, the etching process is performed by photolithography and oxide etching, respectively, in step (1-2), step (1-3), step (1-b) and step (1-c).

[0032] According to an embodiment of the present invention, step (1-4) and step (1-d) are each independently deposited by thermal evaporation, magnetron sputtering or electron beam evaporation to form a Ti layer and a Cu layer.

[0033] A second aspect of the present invention provides a gallium nitride diamond CMOS device, comprising:

[0034] A planar p-diamond MOSFET wafer and a quasi-vertical GaN MOSFET wafer arranged in alignment with each other;

[0035] A first dielectric layer and a second dielectric layer, wherein the first dielectric layer is disposed on a surface of the planar p-diamond MOSFET wafer, and the second dielectric layer is grown on a surface of the quasi-vertical GaN MOSFET wafer, and the first dielectric layer and the second dielectric layer are disposed opposite to each other;

[0036] A first Cu-Pad and a second Cu-Pad, wherein the first Cu-Pad is located on the surface of the planar p-diamond MOSFET wafer and distributed in the first dielectric layer, the second Cu-Pad is located on the surface of the quasi-vertical GaN MOSFET wafer and distributed in the second dielectric layer, the first Cu-Pad and the second Cu-Pad are aligned toward each other, and the first Cu-Pad and the second Cu-Pad are Cu-Cu bonded.

[0037] According to an embodiment of the present invention, the thickness of the first dielectric layer and the second dielectric layer are respectively 3-8 microns.

[0038] According to an embodiment of the present invention, the first dielectric layer is obtained by oxide deposition or polymer spin coating, and the second dielectric layer is obtained by polymer spin coating.

[0039] According to an embodiment of the present invention, the oxide is selected from at least one of silicon dioxide, hafnium dioxide, aluminum oxide, and silicon nitride.

[0040] According to an embodiment of the present invention, the polymer is selected from at least one of polyimide, benzocyclobutene, polybenzo-bisoxazole and fluorinated aromatic AL-X 2010.

[0041] According to an embodiment of the present invention, the provided GaN-diamond CMOS device is obtained according to the method described in the first aspect above.

[0042] The third aspect of the present invention provides the application of the gallium nitride diamond CMOS device described in the second aspect in the electronic field.

[0043] The beneficial effects achieved by the present invention are at least:

[0044] The present invention proposes a method for preparing a gallium nitride diamond CMOS device, which is to connect the metal pads of a quasi-vertical GaN MOSFET device and the metal pads of a planar p-diamond MOSFET device together through high temperature and external pressure to form a CMOS. It has many significant advantages, mainly including:

[0045] (1) The prepared GaN-diamond CMOS device combines the high power and high frequency characteristics of GaN with the excellent heat dissipation capability of diamond, achieving extremely high power density, energy conversion efficiency and voltage resistance. This combination ensures that the device has extremely high reliability in high power and high temperature environments, and can achieve high frequency and high power operation at the same time.

[0046] (2) The method provided by the present invention adopts Cu-Cu bonding technology to prepare gallium nitride diamond devices, avoiding the complexity and interface defect problems of direct epitaxy of GaN on diamond substrates, simplifying the process flow, reducing production costs and significantly improving product yield. It can be used in multiple technical fields. For example, in high-speed digital circuits and high-frequency communication systems, it can effectively reduce signal transmission losses, improve signal integrity, and ensure the quality of high-speed data transmission. For high-power integrated circuits and power electronic devices, Cu-Cu bonding technology reduces chip junction temperature through efficient heat dissipation, prolongs device life and improves its reliability. In addition, Cu-Cu bonding technology is relatively mature, and related process equipment and materials are relatively complete, which is convenient for promotion and application in actual process routes. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 The present invention provides a process flow chart for preparing Cu-Pads on the surface of a planar p-diamond MOSFET device according to an embodiment of the present invention.

[0048] Figure 2 The present invention provides a process flow chart for preparing Cu-Pads on the surface of a quasi-vertical GaN MOSFET device according to an embodiment of the present invention.

[0049] Figure 3 Cu-Cu bonding is performed for the quasi-vertical GaN MOSFET device and the planar p-diamond MOSFET device provided according to the embodiments of the present invention.

[0050] Figure 4 It is a schematic diagram of forming a dielectric layer on a planar p-diamond MOSFET wafer according to an embodiment of the present invention.

[0051] Figure 5 It is a schematic diagram of preparing metal connection holes in a dielectric layer on a planar p-diamond MOSFET wafer according to an embodiment of the present invention.

[0052] Figure 6 Schematic diagram of rewiring in a dielectric layer of a planar p-diamond MOSFET wafer according to an embodiment of the present invention.

[0053] Figure 7 Schematic diagram of metal deposition and CMP polishing according to an embodiment of the present invention.

[0054] Figure 8 Rewiring and forming Cu-Pads in the dielectric layer according to an embodiment of the present invention.

[0055] Fig. 9A schematic diagram of the surface layout and cross-sectional morphology of a planar p-diamond MOSFET device provided in an embodiment of the present invention, wherein a is a top view and b is a front view.

[0056] Fig.10 The diagram is a schematic diagram of forming a polymer dielectric layer on a quasi-vertical GaN MOSFET wafer according to an embodiment of the present invention.

[0057] Fig.11 A schematic diagram of the preparation of metal connection holes and rewiring in a dielectric layer according to an embodiment of the present invention.

[0058] Fig.12 Schematic diagram of metal deposition and CMP polishing according to an embodiment of the present invention.

[0059] Fig.13 Rewiring and forming Cu-Pads in the dielectric layer according to an embodiment of the present invention.

[0060] Fig.14 It is a schematic diagram of the surface layout and cross-sectional morphology of a quasi-vertical GaN MOSFET device provided according to an embodiment of the present invention, wherein a is a top view and b is a front view.

[0061] Fig.15 This is a schematic diagram of a CMOS structure after Cu-Cu bonding is completed according to an embodiment of the present invention, a is a top view, and b is a main view.

[0062] Fig.16 A schematic diagram of the structure of a gallium nitride diamond CMOS device provided according to an embodiment of the present invention, wherein reference numeral 1 represents a planar p-diamond MOSFET wafer, reference numeral 2 represents a first dielectric layer, reference numeral 3 represents a first Cu-Pads, reference numeral 4 represents a second Cu-Pads, reference numeral 5 represents a second dielectric layer, and reference numeral 6 represents a quasi-vertical GaN MOSFET wafer. DETAILED DESCRIPTION

[0063] Embodiments of the present invention are described in detail below. Examples of the embodiments are shown in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, but should not be construed as limiting the present invention.

[0064] In this article, "first" and "second" are only used for descriptive purposes and are not used to indicate order or importance.

[0065] The present invention adopts a Cu-Cu bonding process to prepare a gallium nitride diamond CMOS device. The method can realize the separate manufacturing of quasi-vertical GaN MOSFET devices and planar p-diamond MOSFET devices, avoiding the technical difficulties of epitaxy of GaN film on diamond substrate and the influence of GaN / diamond interface defects on device performance. Moreover, the provided method reduces the complexity of the process flow of GaN diamond CMOS, reduces the production difficulty and cost, and improves the product yield of GaN diamond CMOS. Moreover, the gallium nitride diamond CMOS device prepared by Cu-Cu bonding is used in high-speed digital circuits and high-frequency communication systems, which can significantly reduce signal transmission loss, improve signal integrity, and ensure the quality of high-speed data transmission. In high-power integrated circuits and power electronic devices, it can effectively dissipate heat, reduce chip junction temperature, and improve device reliability and life.

[0066] According to a specific embodiment, a method for preparing a gallium nitride diamond CMOS device is provided, comprising:

[0067] (1) preparing Cu-Pads on the surface of a planar p-diamond MOSFET wafer to obtain a planar p-diamond MOSFET device containing the first Cu-Pads;

[0068] Preparing Cu-Pads on the surface of the quasi-vertical GaN MOSFET wafer to obtain a quasi-vertical GaN MOSFET device containing a second Cu-Pads;

[0069] (2) Aligning the first Cu-Pads of the planar p-diamond MOSFET device containing the first Cu-Pads and the second Cu-Pads of the quasi-vertical GaN MOSFET device containing the second Cu-Pads toward each other, and performing Cu-Cu bonding connection at a predetermined temperature and a predetermined pressure to obtain a gallium nitride diamond CMOS device.

[0070] According to a specific embodiment, step (2) further comprises:

[0071] (2-1) Align the first Cu-Pads of the planar p-diamond MOSFET device containing the first Cu-Pads and the second Cu-Pads of the quasi-vertical GaN MOSFET device containing the second Cu-Pads toward each other, and apply 50N / cm2 of inert gas protection at a pressure of 0.1Pa to 0.5Pa. 2 ~150N / cm 2 The Cu-Cu bonding is performed by applying a pressure and heating at a temperature of 200 to 400°C for 20 to 50 minutes;

[0072] (2-2) Annealing is performed, and then the bonded product is heated at a temperature of 200 to 400° C. for 40 to 100 minutes under the protection of an inert gas.

[0073] During the Cu-Cu bonding process, the bonding needs to be performed under vacuum pressure to prevent the Cu surface from being oxidized.

[0074] According to a specific embodiment, the planar p-diamond MOSFET device containing the first Cu-Pads is prepared by the following method:

[0075] (1-1) growing a dielectric layer on the surface of a planar p-diamond MOSFET wafer by oxide deposition or polymer spin coating;

[0076] (1-2) etching the dielectric layer to form vertical metal connection holes at the metal pads of the planar p-diamond MOSFET wafer;

[0077] (1-3) continuing to perform etching on the dielectric layer to remove a portion of the dielectric layer so as to form a pattern in the dielectric layer;

[0078] (1-4) depositing Ti and Cu on the entire surface of the planar p-diamond MOSFET wafer containing the pattern close to the pattern side to form a Ti layer and a Cu layer, wherein the Ti layer and the Cu layer are distributed in the dielectric layer, the Cu layer is located on the surface of the Ti layer, and the surface of the formed Cu layer is polished;

[0079] (1-5) Repeat the above steps (1-1) to (1-4) to obtain a planar p-diamond MOSFET device containing the first Cu-Pads.

[0080] According to a specific embodiment, a quasi-vertical GaN MOSFET device containing the second Cu-Pads is prepared by the following method:

[0081] (1-a) growing a dielectric layer on the surface of the quasi-vertical GaN MOSFET wafer by polymer spin coating;

[0082] (1-b) etching the dielectric layer to form vertical metal connection holes at the metal pads of the quasi-vertical GaN MOSFET wafer;

[0083] (1-c) continuing to perform etching on the dielectric layer to remove a portion of the dielectric layer so as to form a pattern in the dielectric layer;

[0084] (1-d) depositing Ti and Cu on the entire surface of the quasi-vertical GaN MOSFET wafer including the pattern close to the pattern side to form a Ti layer and a Cu layer, wherein the Ti layer and the Cu layer are distributed in the dielectric layer, the Cu layer is located on the surface of the Ti layer, and the surface of the formed Cu layer is polished;

[0085] (1-e) Repeat the above steps (1-a) to (1-d) to obtain quasi-vertical GaN MOSFET devices containing the second Cu-Pads.

[0086] It should be noted that, whether it is a planar p-diamond MOSFET wafer or a quasi-vertical GaN MOSFET wafer, each MOSFET has its own Cu-Pads, but these original Cu-Pads are not suitable for directly completing Cu-Cu bonding. By forming vertical metal connection holes in the dielectric layer (connecting the original Cu-Pads) and the above-mentioned rewiring in the dielectric layer (rewiring can easily change the position of Cu-Pads), and then forming vertical metal connection holes, the final Cu-Pads are finally formed, which can be used for Cu-Cu bonding.

[0087] The thickness of the dielectric layer mentioned is 2 to 6 microns; by repeating the above steps, the thickness of the dielectric layer can be increased by about one time, for example, the thickness of the dielectric layer finally prepared can be 3 to 8 mm. In the actual preparation process, the thickness of the dielectric layer prepared for the first time can be thicker, and the thickness of the dielectric layer prepared for the second time can be slightly thinner. It can be adjusted according to the actual situation.

[0088] The dielectric layer can be prepared by methods commonly used in the art, for example, it can be obtained by oxide deposition or polymer spin coating. The convex (Source) and concave (Drain) on the surface of the quasi-vertical GaN MOSFET wafer (the vertical height difference between the Source and the Drain is relatively large, a difference of several microns) can be made flat by polymer spin coating to facilitate the next step. If the oxide dielectric layer is grown by plasma enhanced chemical vapor deposition (PECVD), the surface of the dielectric layer will be uneven. The dielectric layer can be obtained on a planar p-diamond MOSFET wafer by polymer spin coating or oxide deposition.

[0089] Useful oxides include, but are not limited to, silicon dioxide, hafnium dioxide, aluminum oxide, silicon nitride, etc.;

[0090] Useful polymers include, but are not limited to, polyimide, benzocyclobutene, polybenzo-bisoxazole, and fluorinated aromatic AL-X 2010, among others.

[0091] Polishing treatment can be carried out by the commonly used methods in the art, and the surface roughness Ra of the Cu surface after polishing treatment is less than 1.0nm. For example, the chemical mechanical polishing method can be used for the polishing treatment. Chemical mechanical polishing (CMP) is an ultra-precision polishing technology that combines mechanical friction and chemical corrosion. Its basic principle is to achieve flattening and smoothing of the workpiece surface through the combined effect of mechanical grinding and chemical liquid dissolution. The main process includes: (1) Chemical corrosion: The oxidant and catalyst in the polishing liquid react chemically with the workpiece surface material to form a layer of easily removable chemical reaction film on the workpiece surface; (2) Mechanical grinding: The abrasive particles and polymer materials in the polishing pad remove the chemical reaction film through mechanical action, so that the workpiece surface is exposed again; (3) Repeated alternation: Chemical action and mechanical action are carried out alternately to finally complete the polishing of the workpiece surface. The polishing liquid used can be purchased commercially and usually includes: ultrafine abrasive particles (such as SiO2, used for physical grinding); chemical corrosive agents (such as nitric acid, hydrofluoric acid, etc., used for chemical corrosion); dispersants and stabilizers (used to maintain the stability and uniformity of the polishing liquid) and pH adjusters (to control the pH value of the polishing liquid).

[0092] Step (1-2), step (1-3), step (1-b), and step (1-c) can be etched by photolithography and oxide etching, respectively.

[0093] The deposition of the metal layer Ti layer and the Cu layer can be carried out by methods commonly used in the art, including but not limited to thermal evaporation, magnetron sputtering or electron beam evaporation. Thermal evaporation can be achieved by a high-temperature wire rod or a boat-type evaporator, with simple equipment requirements and low cost. Magnetron sputtering is a technology that uses a magnetic field to control the movement of metal ions. This method can achieve deposition in a high vacuum environment, avoid gas collisions and reactions, and thus obtain high-quality films. Electron beam evaporation uses an electron beam to heat the material, causing it to evaporate and condense into a thin film on a substrate.

[0094] The thickness of the formed Ti layer may be 25 nm, and the thickness of the Cu layer may be 1.5 micrometers.

[0095] The present invention also provides a gallium nitride diamond CMOS device, which can be referred to as Fig.16 As shown, including:

[0096] A planar p-diamond MOSFET wafer and a quasi-vertical GaN MOSFET wafer arranged in alignment with each other;

[0097] A first dielectric layer and a second dielectric layer, wherein the first dielectric layer is disposed on a surface of the planar p-diamond MOSFET wafer, and the second dielectric layer is grown on a surface of the quasi-vertical GaN MOSFET wafer, and the first dielectric layer and the second dielectric layer are disposed opposite to each other;

[0098] A first Cu-Pad and a second Cu-Pad, wherein the first Cu-Pad is located on the surface of the planar p-diamond MOSFET wafer and distributed in the first dielectric layer, the second Cu-Pad is located on the surface of the quasi-vertical GaN MOSFET wafer and distributed in the second dielectric layer, the first Cu-Pad and the second Cu-Pad are aligned toward each other, and the first Cu-Pad and the second Cu-Pad are Cu-Cu bonded.

[0099] In this article, Cu-Cu bonding refers to direct contact and bonding of copper surfaces.

[0100] The gallium nitride diamond CMOS device provided by the present invention integrates quasi-vertical gallium nitride and diamond, and can achieve the following advantages: (1) The high power and high frequency characteristics of quasi-vertical GaN are combined with the excellent heat dissipation ability of diamond to achieve extremely high power density and high frequency operation. (2) The low on-resistance of quasi-vertical GaN and the good heat dissipation of diamond jointly improve the energy conversion efficiency. (3) Effective heat dissipation and material stability jointly ensure the reliability of the device in high-power and high-temperature environments. (4) Both quasi-vertical GaN and diamond have very high breakdown voltages, which further improves the voltage resistance of the device.

[0101] The thickness of the first dielectric layer and the second dielectric layer are respectively 3-8 microns.

[0102] The first dielectric layer can be obtained by oxide deposition or polymer spin coating, and the second dielectric layer can be obtained by polymer spin coating.

[0103] The oxides mentioned include but are not limited to silicon dioxide, hafnium dioxide, aluminum oxide, silicon nitride, etc. The polymers mentioned include but are not limited to at least one of polyimide, benzocyclobutene, polybenzo-bisoxazole and fluorinated aromatic AL-X 2010.

[0104] The gallium nitride diamond CMOS device provided by the present invention is characterized by electrical properties, thermal properties (such as thermal conductivity, junction temperature peak), reliability (such as radiation tolerance, long-term stability, etc.) and physical properties (such as X-ray diffraction). The results show that the gallium nitride diamond CMOS device provided by the present invention exhibits faster switching speed and higher efficiency in high-frequency and high-voltage applications compared to simple unbonded gallium nitride or unbonded diamond devices. Moreover, the integration of diamond devices significantly improves the heat dissipation capacity of gallium nitride devices, allowing the devices to maintain a low junction temperature at high power density.

[0105] The GaN-diamond CMOS devices provided can be used in the electronics field, including but not limited to high power amplifiers, switching power supplies and RF power amplifiers, 5G base stations, satellite communications and radar systems, electric vehicle power conversion systems and charging infrastructure, solar inverters and wind power generation systems, laptop high-efficiency chargers, military communications, navigation, electronic warfare and aerospace applications, as well as oil drilling and deep space exploration.

[0106] The technical scheme of the present invention is described below by specific examples. It should be noted that these examples are only used to facilitate the understanding of those skilled in the art and should not be regarded as limiting the scope of protection of the present invention. Unless otherwise specified, the reagents used in the examples can be obtained commercially.

[0107] Example 1

[0108] The present invention relates to a method and process flow for preparing gallium nitride diamond CMOS by integrating quasi-vertical gallium nitride devices and diamond devices using a Cu-Cu bonding process, which is specifically as follows:

[0109] (1) Refer to Figure 1 As shown, Cu-Pads are prepared on the surface of a planar p-diamond MOSFET device.

[0110] 1) Prepare an 8-inch planar p-diamond MOSFET wafer.

[0111] 2) A 5 μm thick SiO2 dielectric layer is grown on the surface of a planar p-diamond MOSFET wafer by plasma enhanced chemical vapor deposition (PECVD); the schematic diagram of the structure is shown in FIG. Figure 4 shown.

[0112] 3) Through photolithography and oxide etching processes, vertical metal connection holes are formed at the metal pads of the p-type diamond MOSFET wafer. Figure 5 shown.

[0113] 4) Again through the photolithography and oxide etching process, a pattern is formed in the dielectric layer to facilitate rewiring in the dielectric layer. Its structure is as follows Figure 6 shown.

[0114] 5) Sputter Ti and Cu and electrochemically deposit (ECD) Cu on the entire wafer to complete the wiring in the dielectric layer. The wafer surface is polished using a chemical mechanical polishing (CMP) process. The process diagram is shown in the figure below. Figure 7 shown.

[0115] 6) Repeat the above steps 2) to 5) to rewire the dielectric layer and obtain Cu-Pads on the wafer surface. The process steps are as follows: Figure 8 shown.

[0116] 7) The surface layout and cross-sectional morphology of the planar p-diamond MOSFET device with Cu-Pads are shown in Figure 2. Fig. 9 As shown in (a) and (b).

[0117] (2) Reference Figure 2 As shown, Cu-Pads are prepared on the surface of quasi-vertical GaN MOSFET devices.

[0118] 1) Prepare an 8-inch quasi-vertical GaN MOSFET wafer.

[0119] 2) Spin-coat the polymer PI (polyimide) on the surface of the quasi-vertical GaN MOSFET wafer and cure it for 1 hour to form a 4-7μm thick dielectric layer. The schematic diagram of its structure is shown in Fig.10 shown.

[0120] 3) Through photolithography and PI etching process, vertical metal connection holes are formed at the metal pads of the quasi-vertical GaN MOSFET wafer. Through photolithography and PI etching process again, patterns are formed in the polymer dielectric layer to facilitate rewiring in the dielectric layer. The process flow is as follows Fig.11 shown.

[0121] 4) Sputter Ti and Cu and electrochemically deposit (ECD) Cu on the entire wafer to complete the wiring in the dielectric layer. The wafer surface is polished using a chemical mechanical polishing (CMP) process. The process diagram is shown in the figure below. Fig.12 shown.

[0122] 5) Repeat the steps 2) to 4) of step 2 to rewire the polymer dielectric layer and obtain Cu-Pads on the wafer surface. The process steps are as follows: Fig.13 shown.

[0123] 6) The surface layout and cross-sectional morphology of the quasi-vertical GaN MOSFET device with Cu-Pads after rewiring in the polymer dielectric layer are shown in Figure 2. Fig.14 As shown in (a) and (b).

[0124] (3) Reference Figure 3 As shown, the quasi-vertical GaN MOSFET device and the planar p-diamond MOSFET device complete Cu-Cu bonding

[0125] The Cu-Pads of GaN and diamond MOSFET wafers were aligned, and a pressure of 25 kN was applied to the wafers under the protection of N2 atmosphere with a pressure of 0.1 Pa, and the wafers were heated at a temperature of 300 ° C for 30 minutes. After bonding, the bonded wafers were annealed and heated at a temperature of 300 ° C for 60 minutes under the protection of N2 atmosphere.

[0126] The schematic diagram of the CMOS structure after Cu-Cu bonding is shown in the figure below. Fig.15 As shown, Fig.15 (a) is a schematic diagram of the surface layout after Cu-Cu bonding. Fig.15 (b) Schematic diagram of the cross-sectional morphology of CMOS after Cu-Cu bonding.

[0127] Characterization shows that the GaN-diamond CMOS device provided by the present invention exhibits faster switching speed and higher efficiency in high-frequency and high-voltage applications compared to simple unbonded GaN or unbonded diamond devices. Moreover, the integration of diamond devices significantly improves the heat dissipation capacity of GaN devices, allowing the devices to maintain a low junction temperature at high power density.

[0128] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A method for preparing a CMOS device using quasi-vertical gallium nitride and diamond, characterized in that: include: (1) preparing Cu-Pads on the surface of a planar p-diamond MOSFET wafer to obtain a planar p-diamond MOSFET device containing the first Cu-Pads; Preparing Cu-Pads on the surface of the quasi-vertical GaN MOSFET wafer to obtain a quasi-vertical GaN MOSFET device containing a second Cu-Pads; (2) Aligning the first Cu-Pads of the planar p-diamond MOSFET device containing the first Cu-Pads and the second Cu-Pads of the quasi-vertical GaN MOSFET device containing the second Cu-Pads toward each other, and performing Cu-Cu bonding connection at a predetermined temperature and a predetermined pressure to obtain a gallium nitride diamond CMOS device.

2. The method according to claim 1, characterized in that Step (2) further comprises: (2-1) The first Cu-Pads of the planar p-diamond MOSFET device containing the first Cu-Pads and the second Cu-Pads of the quasi-vertical GaN MOSFET device containing the second Cu-Pads are aligned toward each other, and a pressure of 50 N / cm3 is applied under the protection of an inert gas at a vacuum pressure of 0.1 Pa to 0.5 Pa. 2 ~150N / cm 2 The Cu-Cu bonding is performed by applying a pressure and heating at a temperature of 200 to 400°C for 20 to 50 minutes; (2-2) Annealing is performed, and then the bonded product is heated at a temperature of 200 to 400° C. for 40 to 100 minutes under the protection of an inert gas.

3. The method according to claim 1, characterized in that The step (1) of preparing Cu-Pads on the surface of a planar p-diamond MOSFET wafer to obtain a planar p-diamond MOSFET device containing first Cu-Pads comprises: (1-1) growing a dielectric layer on the surface of a planar p-diamond MOSFET wafer by oxide deposition or polymer spin coating; (1-2) etching the dielectric layer to form vertical metal connection holes at the metal pads of the planar p-diamond MOSFET wafer; (1-3) continuing to perform etching on the dielectric layer to remove a portion of the dielectric layer so as to form a pattern in the dielectric layer; (1-4) depositing Ti and Cu on the entire surface of the planar p-diamond MOSFET wafer containing the pattern close to the pattern side to form a Ti layer and a Cu layer, wherein the Ti layer and the Cu layer are distributed in the dielectric layer, the Cu layer is located on the surface of the Ti layer, and the surface of the formed Cu layer is polished; (1-5) repeating the above steps (1-1) to (1-4) to obtain a planar p-diamond MOSFET device containing the first Cu-Pads; The step (1) of preparing Cu-Pads on the surface of the quasi-vertical GaN MOSFET wafer to obtain a quasi-vertical GaN MOSFET device containing a second Cu-Pads comprises: (1-a) growing a dielectric layer on the surface of the quasi-vertical GaN MOSFET wafer by polymer spin coating; (1-b) etching the dielectric layer to form vertical metal connection holes at the metal pads of the quasi-vertical GaN MOSFET wafer; (1-c) continuing to perform etching on the dielectric layer to remove a portion of the dielectric layer so as to form a pattern in the dielectric layer; (1-d) depositing Ti and Cu on the entire surface of the quasi-vertical GaN MOSFET wafer including the pattern close to the pattern side to form a Ti layer and a Cu layer, wherein the Ti layer and the Cu layer are distributed in the dielectric layer, the Cu layer is located on the surface of the Ti layer, and the surface of the formed Cu layer is polished; (1-e) Repeat the above steps (1-a) to (1-d) to obtain quasi-vertical GaN MOSFET devices containing the second Cu-Pads.

4. The method according to claim 3, characterized in that The thickness of the dielectric layer is 2 to 6 microns; Optionally, the oxide is selected from at least one of silicon dioxide, hafnium dioxide, aluminum oxide, and silicon nitride; Optionally, the polymer is selected from at least one of polyimide, benzocyclobutene, polybenzo-bisoxazole and fluorinated aromatic AL-X 2010.

5. The method according to claim 3, characterized in that: The surface roughness Ra of the Cu surface after polishing is less than 1.0 nm; Optionally, the polishing process is performed by chemical mechanical polishing.

6. The method according to claim 3, characterized in that Step (1-2), step (1-3), step (1-b) and step (1-c) are respectively subjected to the etching process by photolithography and oxide etching; Optionally, step (1-4) and step (1-d) are each independently deposited by thermal evaporation, magnetron sputtering or electron beam evaporation to form a Ti layer and a Cu layer.

7. A gallium nitride diamond CMOS device, characterized in that: include: A planar p-diamond MOSFET wafer and a quasi-vertical GaN MOSFET wafer arranged in alignment with each other; A first dielectric layer and a second dielectric layer, wherein the first dielectric layer is disposed on a surface of the planar p-diamond MOSFET wafer, and the second dielectric layer is grown on a surface of the quasi-vertical GaN MOSFET wafer, and the first dielectric layer and the second dielectric layer are disposed opposite to each other; A first Cu-Pad and a second Cu-Pad, wherein the first Cu-Pad is located on the surface of the planar p-diamond MOSFET wafer and distributed in the first dielectric layer, the second Cu-Pad is located on the surface of the quasi-vertical GaN MOSFET wafer and distributed in the second dielectric layer, the first Cu-Pad and the second Cu-Pad are aligned toward each other, and the first Cu-Pad and the second Cu-Pad are Cu-Cu bonded.

8. The GaN-diamond CMOS device according to claim 7, characterized in that: The thickness of the first dielectric layer and the second dielectric layer are 3 to 8 microns respectively; Optionally, the first dielectric layer is obtained by oxide deposition or polymer spin coating, and the second dielectric layer is obtained by polymer spin coating; Optionally, the oxide is selected from at least one of silicon dioxide, hafnium dioxide, aluminum oxide, and silicon nitride; Optionally, the polymer is selected from at least one of polyimide, benzocyclobutene, polybenzo-bisoxazole and fluorinated aromatic AL-X 2010.

9. The GaN-diamond CMOS device according to claim 7, characterized in that: Prepared according to the method according to any one of claims 1 to 6.

10. Application of the gallium nitride diamond CMOS device according to any one of claims 7 to 9 in the field of electronics.

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