Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof, and the preparation method comprises the steps: providing a first interlayer dielectric layer which is internally provided with a metal wire, the top surface of the first interlayer dielectric layer is exposed out of the top surface of the metal wire, and the top surface of the metal wire is provided with a recess; forming a conductive protection layer in the recess, wherein the top surface of the conductive protection layer is flush with the top surface of the first interlayer dielectric layer; forming a second interlayer dielectric layer on the top surface of the first interlayer dielectric layer, and forming a through hole exposing at least part of the surface of the conductive protection layer in the second interlayer dielectric layer; and forming a metal plug fully filling the through hole. According to the method, the metal wiring can be prevented from being damaged by etching and oxidized in the manufacturing process.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] In the process of manufacturing very large scale integrated circuits (VLSI), one or more layers of metal wiring and metal plugs (or through-hole connection structures) connected to the metal wiring are usually formed to realize the interconnection between devices.

[0003] However, in the process of forming metal wiring and through-hole structure in the existing process, the metal wiring is easily damaged by etching and oxidized. Summary of the invention

[0004] Based on this, the present application provides a semiconductor structure and a method for manufacturing the same to prevent metal wiring from being damaged by etching and oxidized during the manufacturing process.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a semiconductor structure, comprising:

[0006] Providing a first interlayer dielectric layer, wherein the first interlayer dielectric layer has a metal wiring, the top surface of the first interlayer dielectric layer exposes the top surface of the metal wiring, and the top surface of the metal wiring has a recess;

[0007] forming a conductive protection layer in the recess, wherein a top surface of the conductive protection layer is flush with a top surface of the first interlayer dielectric layer;

[0008] forming a second interlayer dielectric layer on the top surface of the first interlayer dielectric layer, and forming a through hole in the second interlayer dielectric layer to expose at least a portion of the surface of the conductive protection layer;

[0009] A metal plug is formed to fill the through hole.

[0010] In some embodiments of the present application, the depression is a butterfly-shaped depression, and the formation process of the depression includes: forming a groove in the first interlayer dielectric layer; forming a first metal material layer in the groove and on the top surface of the first interlayer dielectric layer, and the first metal material layer fills the groove; using a chemical mechanical polishing process to flatten the first metal material layer until the first interlayer dielectric layer is exposed to form the metal wiring, and when performing the chemical mechanical polishing process, the first metal material layer in the groove is over-polished so that the top surface of the metal wiring has a butterfly-shaped depression.

[0011] In some embodiments of the present application, the depression is a rectangular depression, and the formation process of the depression includes: forming a groove in the first interlayer dielectric layer; initial metal wiring in the groove, and the top surface of the metal wiring is flush with the top surface of the first interlayer dielectric layer; performing a sputtering process, using non-metallic plasma to bombard the top surface of the initial metal wiring, removing part of the thickness of the initial metal wiring, forming the rectangular depression, and the remaining initial metal wiring is the metal wiring.

[0012] In some embodiments of the present application, the recess includes a rectangular recess and a butterfly-shaped recess connected to the rectangular recess, and the formation process of the recess includes: forming a groove in the first interlayer dielectric layer; forming a first metal material layer in the groove and on the top surface of the first interlayer dielectric layer, and the first metal material layer fills the groove; using a chemical mechanical polishing process to flatten the first metal material layer until the first interlayer dielectric layer is exposed to form an initial metal wiring, and when performing the chemical mechanical polishing process, the first metal material layer in the groove is over-polished so that the top surface of the initial metal wiring has a butterfly-shaped recess; performing a sputtering process, bombarding the top surface of the initial metal wiring with non-metallic plasma, removing part of the thickness of the initial metal wiring, forming a rectangular recess connected to the butterfly-shaped recess, and deepening the depth of the butterfly-shaped recess, and the remaining initial metal wiring is the metal wiring.

[0013] In some embodiments of the present application, the non-metallic plasma used in the sputtering process includes argon-containing or hydrogen-containing plasma.

[0014] In some embodiments of the present application, the conductive protection layer includes a single-layer structure of one material selected from the group consisting of Ti, Ta, TiN, TaN, W, and WN, or a stacked-layer structure of several materials.

[0015] In some embodiments of the present application, the process of forming the conductive protective layer includes: forming a conductive protective material layer in the recess and on the top surface of the first interlayer dielectric layer; planarizing and removing the conductive protective material layer above the top surface of the first interlayer dielectric layer to form the conductive protective layer in the recess.

[0016] In a second aspect, an embodiment of the present application further provides a method for preparing a semiconductor structure, comprising:

[0017] Providing a first interlayer dielectric layer, wherein the first interlayer dielectric layer has a metal wiring, the top surface of the first interlayer dielectric layer exposes the top surface of the metal wiring, and the top surface of the metal wiring has a recess;

[0018] forming a non-conductive protective layer in the recess, wherein a top surface of the non-conductive protective layer is flush with a top surface of the first interlayer dielectric layer;

[0019] forming a second interlayer dielectric layer on the top surface of the first interlayer dielectric layer, wherein the second interlayer dielectric layer has a through hole exposing at least a portion of the surface of the non-conductive protective layer;

[0020] The non-conductive protective layer is removed along the through hole.

[0021] A metal plug is formed to fill the through hole.

[0022] In some embodiments of the present application, the non-conductive protective layer is aluminum oxide, and the process of removing the non-conductive protective layer includes wet etching.

[0023] In a third aspect, an embodiment of the present application further provides a semiconductor structure, including:

[0024] A first interlayer dielectric layer, wherein a metal wiring is provided in the first interlayer dielectric layer, a top surface of the first interlayer dielectric layer exposes a top surface of the metal wiring, and the top surface of the metal wiring has a recess;

[0025] A conductive protection layer located in the recess, wherein a top surface of the conductive protection layer is flush with a top surface of the first interlayer dielectric layer;

[0026] a second interlayer dielectric layer located on the top surface of the first interlayer dielectric layer, wherein the second interlayer dielectric layer has a through hole exposing at least a portion of the surface of the conductive protection layer;

[0027] A metal plug is located in the through hole.

[0028] The embodiments of the present application may or at least have the following advantages:

[0029] In the semiconductor structure and the preparation method thereof in the embodiment of the present application, a conductive protective layer is formed by a recess on the top surface of the metal wiring, and the top surface of the conductive protective layer is flush with the top surface of the first interlayer dielectric layer. When a second interlayer dielectric layer is subsequently formed on the top surface of the first interlayer dielectric layer and a through hole is formed in the second interlayer dielectric layer to expose at least part of the surface of the conductive protective layer, the conductive protective layer can protect the metal wiring from being damaged by plasma (such as fluorine-containing plasma and oxygen-containing plasma) during etching, and can prevent the metal wiring from reacting with carbon-containing residues after etching and prevent the metal wiring from being oxidized after etching, thereby avoiding the formation of hole defects and difficult-to-remove reactants in the top surface of the metal wiring during the manufacturing process, thereby not increasing the resistance of the metal wiring itself and the contact resistance between the metal wiring and the metal plug formed in the subsequent through hole, and the conductive protective layer can also extend the Q-time (waiting time) from etching to cleaning; in addition, since the conductive protective layer itself is conductive, the conductive protective layer may not be removed in the subsequent process, and a metal plug electrically connected to the conductive protective layer may be directly formed in the through hole later. Furthermore, the presence of the depression on the top surface of the metal wiring allows the subsequently formed conductive protective layer to be accurately confined within the depression, thereby improving the accuracy of the conductive protective layer formation position. Furthermore, the depression (especially the butterfly-shaped depression) can increase the contact area between the subsequently formed conductive protective layer and the metal wiring, thereby reducing the contact resistance between the wire protective layer and the metal wiring. Furthermore, when the conductive protective layer is formed in the depression, the top surface of the conductive protective layer can be easily made flush with the top surface of the first interlayer dielectric layer through a chemical mechanical polishing process, thereby providing a flat surface for the subsequent formation of a second interlayer dielectric layer and a patterned photoresist layer, etc., and thereby helping to improve the accuracy of subsequent processes.

[0030] The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1-Figure 4 A schematic diagram of the cross-sectional structure of each stage in a method for preparing a semiconductor structure provided in the present application;

[0033] Figure 5-Figure 11A schematic diagram of a cross-sectional structure at various stages in a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0034] Figure 12-Figure 18 Schematic diagrams of cross-sectional structures at various stages in a method for preparing a semiconductor structure provided in other embodiments of the present application;

[0035] Figure 19-Figure 25 Schematic diagram of the cross-sectional structure of each stage in a method for preparing a semiconductor structure provided in some other embodiments of the present application.

[0036] Description of reference numerals:

[0037] 101-first interlayer dielectric layer; 102-metal wiring; 103-second interlayer dielectric layer; 104-etched sacrificial layer; 105-patterned photoresist layer; 106-opening; 107-through hole; 108-damaged layer; 109-hole defect;

[0038] 201-first interlayer dielectric layer; 202-metal wiring; 203-second interlayer dielectric layer; 204-etched sacrificial layer; 205-patterned photoresist layer; 206-opening; 207-through hole; 208-recess; 208a-butterfly-shaped recess; 208b-rectangular recess; 209-conductive protective material layer; 210-conductive protective layer; 211-conductive metal layer; 212-metal plug. DETAILED DESCRIPTION

[0039] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0041] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0042] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0043] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0044] The structure of the embodiments of the present invention should not be limited to the specific shapes shown in the drawings of the specification, but includes shape deviations due to, for example, manufacturing technology.

[0045] It can be understood that in the drawings of the present application, some adjacent film layers with the same processed film material are drawn to be connected to make them close to the actual structure.

[0046] During the manufacturing process of integrated circuits, after forming semiconductor devices on the substrate, it is necessary to form at least one wiring layer to electrically connect the semiconductor devices. Each wiring layer generally includes metal wiring and metal plugs (or through-hole connection structures) connected to the metal wiring. In the process of forming metal wiring and through-hole structures, metal wiring is easily etched, damaged and oxidized. For specific manufacturing processes, please refer to Figure 1-Figure 4 ,refer to Figure 1 , providing a first interlayer dielectric layer 101, wherein the first interlayer dielectric layer 101 has a metal wiring 102, and the top surface of the first interlayer dielectric layer 101 exposes the top surface of the metal wiring 102; a second interlayer dielectric layer 103, an etched sacrificial layer 104, and a patterned photoresist layer 105 are sequentially located on the top surface of the first interlayer dielectric layer 101, and the patterned photoresist layer 105 has an opening 106 that exposes a portion of the top surface of the etched sacrificial layer 104; referring to Figure 2 , the patterned photoresist layer 105 is used as a mask, and the etching sacrificial layer 104 and the second interlayer dielectric layer 103 are sequentially etched along the opening 106 to form a through hole 107 in the second interlayer dielectric layer 103. The patterned photoresist layer 105 and the etching sacrificial layer 104 are removed synchronously during the process, as shown in FIG. Figure 3 As shown, when etching the second interlayer dielectric layer 103, the fluorine-containing plasma and the oxygen plasma may damage the metal wiring 102 exposed at the bottom of the through hole 107, and form a damaged layer 108 on the top surface of the metal wiring 102, as shown in FIG. Figure 4 As shown, the damaged layer 108 will be removed during the subsequent cleaning after etching, thereby forming a hole defect 109 on the top surface of the metal wiring 102, affecting the connection performance between the metal wiring 102 and the metal plug formed in the subsequent through hole 107 (for example, increasing the contact resistance between the metal wiring and the metal plug). In addition, after the through hole 107 is formed, the metal wiring 102 (the material of the metal wiring 102 is, for example, copper) exposed at the bottom of the through hole 107 is easily oxidized and also easily reacts with the carbon-containing residue after etching, which is difficult to remove by cleaning, forming defects, increasing the resistance of the metal wiring 102 itself and increasing the contact resistance between the metal wiring 102 and the metal plug.

[0047] To this end, an embodiment of the present application provides a semiconductor structure and a preparation method thereof. The preparation method provides a concave top surface of a metal wiring in a first interlayer dielectric layer, and then forms a conductive protective layer in the concave, wherein the top surface of the conductive protective layer is flush with the top surface of the first interlayer dielectric layer. When a second interlayer dielectric layer is subsequently formed on the top surface of the first interlayer dielectric layer, and a through hole is formed in the second interlayer dielectric layer to expose at least part of the surface of the conductive protective layer, the conductive protective layer can protect the metal wiring from being damaged by plasma during etching, and can prevent the metal wiring from being damaged by plasma during etching. The conductive protective layer reacts with the carbon-containing residues after etching and prevents the metal wiring from being oxidized after etching, thereby avoiding the formation of hole defects and difficult-to-remove reactants in the top surface of the metal wiring during the manufacturing process, thereby not increasing the resistance of the metal wiring itself and the contact resistance between the metal wiring and the metal plug. In addition, the conductive protective layer can also extend the Q-time (waiting time) from etching to cleaning. In addition, since the conductive protective layer itself is conductive, the conductive protective layer may not be removed in the subsequent process, and a metal plug electrically connected to the conductive protective layer may be directly formed in the through hole.

[0048] The specific process of the method for preparing the semiconductor structure is described in detail below with reference to the accompanying drawings. Figure 5-Figure 11 A schematic diagram of a cross-sectional structure at various stages in a method for preparing a semiconductor structure provided in some embodiments of the present application; Figure 12-Figure 18 Schematic diagrams of cross-sectional structures at various stages in a method for preparing a semiconductor structure provided in other embodiments of the present application; Figure 19-Figure 25 Schematic diagram of cross-sectional structure at various stages in a method for preparing a semiconductor structure provided in other embodiments of the present application

[0049] First, refer to Figure 5 , providing a first interlayer dielectric layer 201, wherein the first interlayer dielectric layer 201 has a metal wiring 202, the top surface of the first interlayer dielectric layer 201 exposes the top surface of the metal wiring 202, and the top surface of the metal wiring 202 has a recess 208.

[0050] The first interlayer dielectric layer 201 is used for electrical isolation between metal wirings 202 and between metal wirings 202 and subsequently formed metal plugs. In some embodiments, the first interlayer dielectric layer 201 includes a single layer or a multi-layer stacked structure. In some embodiments, the material of the first interlayer dielectric layer 201 includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide) or BPSG (boron-phosphorus-doped silicon dioxide), low dielectric constant (K less than 2.5) materials or combinations thereof. The formation of the first interlayer dielectric layer 201 includes atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), high pressure chemical vapor deposition (HPCVD), plasma enhanced chemical vapor deposition (PECVD) or high density plasma chemical vapor deposition (HDPCVD).

[0051] In some embodiments, it also includes: providing a substrate (not shown in the figure); forming a plurality of semiconductor devices (not shown in the figure) in the substrate; the semiconductor devices are formed on the substrate and cover the semiconductor devices. The material of the substrate may include silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it may also be silicon on insulator (SOI), germanium on insulator (GOI); or it may also include other materials, such as III-V compounds such as gallium arsenide. The substrate may also be implanted with certain doping ions to change electrical parameters according to design requirements. A shallow trench isolation structure (not shown in the figure) is also formed in the substrate. The shallow trench isolation structure is used to isolate different semiconductor devices and prevent electrical connection between different semiconductor devices. The material of the shallow trench isolation structure may include silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. In some embodiments, the semiconductor device includes active devices and / or passive devices, wherein the active device includes a metal-oxide-semiconductor field-effect transistor (MOSFET), a bipolar junction transistor (BJT), a field effect transistor (FET), a fin field effect transistor (FinFET), an insulated gate bipolar transistor (IGBT), a nanowire transistor, a memory device, or a combination thereof. The passive device includes a diode, a resistor, a capacitor, an inductor, or a combination thereof.

[0052] The metal wiring 202 is located in the first interlayer dielectric layer 201. The metal wiring 202 is used to electrically connect to the metal plug formed subsequently. In some embodiments, the metal wiring 202 can also be used to electrically connect to the semiconductor device formed on the substrate. In some embodiments, there is also an anti-diffusion barrier layer (not shown in the figure) between the outer wall of the metal wiring 202 and the first interlayer dielectric layer 201. The material of the metal wiring 202 includes Cu, Al, W, Ag, Au, Pt, Ni or a combination thereof. The material of the anti-diffusion barrier layer includes one or more of Ti, Ta, TiN, TaN, TaC, and WN.

[0053] The top surface of the metal wiring 102 has a depression 208 that is concave downward, and a conductive protection layer 210 is subsequently formed in the depression 208 (refer to Figure 7 ), the recess 208 can accurately limit the subsequently formed conductive protection layer within the recess 208, thereby improving the accuracy of the conductive protection layer formation position, and the recess 208 (especially the butterfly-shaped recess) can increase the contact area between the subsequently formed conductive protection layer 210 and the metal wiring 102, thereby reducing the contact resistance between the wire protection layer 210 and the metal wiring 102, and when the conductive protection layer 210 is formed in the recess 208, the top surface of the conductive protection layer 210 can be easily made flush with the top surface of the first interlayer dielectric layer 201 through a chemical mechanical polishing process, thereby providing a flat surface for the subsequent formation of a second interlayer dielectric layer and a patterned photoresist layer, etc., which is beneficial to improving the accuracy of subsequent processes.

[0054] In some embodiments, continue to refer to Figure 5 The depression 208 is a butterfly-shaped depression, and the formation process of the depression 208 includes: forming a groove (not shown in the figure) in the first interlayer dielectric layer 201; forming a first metal material layer in the groove and on the top surface of the first interlayer dielectric layer 201, and the first metal material layer fills the groove; using a chemical mechanical polishing process to flatten the first metal material layer until the first interlayer dielectric layer 201 is exposed, forming the metal wiring 202, and during the chemical mechanical polishing process, the first metal material layer in the groove is over-polished, so that the top surface of the metal wiring 202 has a butterfly-shaped depression. The process of forming the metal wiring 202 with the depression 208 in this solution is relatively simple.

[0055] In addition to the aforementioned butterfly shape, the recess 208 may also be in other shapes. Fig.12, the depression 208 is a rectangular depression, and the formation process of the depression 208 includes: forming a groove (not shown in the figure) in the first interlayer dielectric layer 201; initially forming a metal wiring in the groove, the top surface of the metal wiring being flush with the top surface of the first interlayer dielectric layer 201; performing a sputtering process, bombarding the top surface of the initial metal wiring with non-metallic plasma, removing a portion of the thickness of the initial metal wiring, forming the rectangular depression 208, and the remaining initial metal wiring is the metal wiring 202. In a specific example, the non-metallic plasma used in the sputtering process includes argon-containing or hydrogen-containing plasma to avoid damage to the metal wiring 202.

[0056] In another embodiment, reference Fig.19 The recess 208 includes a rectangular recess 208b and a butterfly-shaped recess 208a connected to the rectangular recess 208b, and the formation process of the recess 208 includes: forming a groove in the first interlayer dielectric layer 201; forming a first metal material layer in the groove and on the top surface of the first interlayer dielectric layer, and the first metal material layer fills the groove; using a chemical mechanical polishing process to flatten the first metal material layer until the first interlayer dielectric layer 201 is exposed to form an initial metal wiring, and when performing the chemical mechanical polishing process, the first metal material layer in the groove is over-polished so that the top surface of the initial metal wiring has a butterfly-shaped recess 208a; performing a sputtering process, bombarding the top surface of the initial metal wiring with non-metallic plasma, removing part of the thickness of the initial metal wiring, forming a rectangular recess 208b connected to the butterfly-shaped recess, and deepening the depth of the butterfly-shaped recess 208a, and the remaining initial metal wiring is the metal wiring 202. The recess 208 of this specific structure makes the conductive protection layer 210 (refer to Fig.21 ) The contact area with the metal wiring 202 is further increased. On the other hand, the conductive protection layer 210 can maintain a certain thickness in the rectangular recess 208b at the edge, so that the conductive protection layer 210 and the first interlayer dielectric layer 201 have a certain transition area, which prevents the conductive protection layer 210 at the edge from warping or falling off during the chemical mechanical polishing process, further improves the adhesion between the formed conductive protection layer 210 and the metal wiring 202 and improves the surface flatness of the formed conductive protection layer 210.

[0057] Next, refer to Figure 6 and Figure 7 , or refer to Fig.13 and Fig.14 , or refer to Fig. 20 and Fig.21 , in the recess 208 (reference Figure 5 ,or Fig.12 ,or Fig.19 ), a conductive protection layer 210 is formed in the first interlayer dielectric layer 201, and a top surface of the conductive protection layer 210 is flush with a top surface of the first interlayer dielectric layer 201.

[0058] In the present application, a conductive protection layer 210 is formed in the recess 208, and the top surface of the conductive protection layer 210 is flush with the top surface of the first interlayer dielectric layer 201. The conductive protection layer 210 is subsequently formed on the top surface of the first interlayer dielectric layer 201 to form a second interlayer dielectric layer 203 (refer to Fig. 9 ,or Fig.16 ,or Fig.23 ), and when a through hole 207 is formed in the second interlayer dielectric layer 203 to expose at least part of the surface of the conductive protection layer 210, the metal wiring 202 can be protected from being damaged by the plasma (such as fluorine-containing plasma and oxygen-containing plasma) during etching, and the metal wiring 202 can be prevented from reacting with the carbon-containing residue after etching and from being oxidized after etching, thereby avoiding the formation of hole defects and difficult-to-remove reactants in the top surface of the metal wiring 202 during the manufacturing process, thereby not increasing the resistance of the metal wiring 202 itself and the metal plug 212 (reference Fig.11 , or refer to Fig.18 or reference Fig.25 ), and the conductive protection layer 210 can also extend the Q-time (waiting time) from etching to cleaning; in addition, since the conductive protection layer 210 itself is conductive, the conductive protection layer 210 may not be removed in subsequent processes, and a metal plug 212 electrically connected to the conductive protection layer 210 may be directly formed in the through hole 207.

[0059] In some embodiments, the conductive protection layer 210 includes a single layer structure of one material selected from Ti, Ta, TiN, TaN, W, and WN, or a stacked structure of several materials. In some embodiments, when the conductive protection layer 210 is a stacked structure, the stacked structure may include a metal layer and a metal nitride layer located on the metal layer. Specifically, the wire protection layer 210 may include a Ti layer and a TiN layer located on the Ti layer, or a Ta layer and a TaN layer located on the Ta layer, or a W layer and a WN layer located on the W layer. The conductive protection layer 210 may be fully retained, partially removed, or fully removed before the subsequent formation of a metal plug. When the conductive protection layer 210 is partially removed, the conductive protection layer 210 is the stacked structure, and a wet etching process may be used to remove the metal nitride layer in the stacked structure, and the metal layer in the stacked structure may be retained, such as removing the TiN layer, TaN layer, or WN layer in the conductive protection layer 210.

[0060] In some embodiments, reference Figure 6 , or refer to Fig.13 , or refer to Fig. 20 The formation process of the conductive protection layer 210 includes: forming a conductive protection material layer 209 in the recess 208 and on the top surface of the first interlayer dielectric layer 203; Figure 7 , or refer to Fig.14 , or refer to Fig.21 The conductive protection material layer 209 above the top surface of the first interlayer dielectric layer 201 is planarized and removed, and the conductive protection layer 210 is formed in the recess. The top surface of the conductive protection layer 210 is flush with the top surface of the first interlayer dielectric layer 203. The planarization adopts a chemical mechanical polishing process.

[0061] Next, refer to Figure 8 and Fig. 9 , or refer to Fig.15 and Fig.16 , or refer to Fig. 22 and Fig.23 A second interlayer dielectric layer 203 is formed on the top surface of the first interlayer dielectric layer 201 , and a through hole 207 is formed in the second interlayer dielectric layer 203 to expose at least a portion of the surface of the conductive protection layer 210 .

[0062] The second interlayer dielectric layer 203 is used for electrical isolation between metal plugs formed in subsequent through holes 207 and between metal plugs and metal wiring 202. In some embodiments, the second interlayer dielectric layer 203 includes a single layer or a multi-layer stacked structure. In some embodiments, the material of the second interlayer dielectric layer 203 includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide) or BPSG (boron-phosphorus-doped silicon dioxide), low dielectric constant (K less than 2.5) materials or combinations thereof. The formation of the second interlayer dielectric layer 203 includes atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), high pressure chemical vapor deposition (HPCVD), plasma enhanced chemical vapor deposition (PECVD) or high density plasma chemical vapor deposition (HDPCVD).

[0063] In some embodiments, continue to refer to Figure 8 , or refer to Fig.15 , or refer to Fig. 22After forming the second interlayer dielectric layer 203, an etching sacrificial layer 204 and a patterned photoresist layer 205 located on the etching sacrificial layer 204 can also be formed on the second interlayer dielectric layer 203. The etching sacrificial layer 204 can be used as a hard mask in the etching process. The material of the etching sacrificial layer 204 is different from the material of the second interlayer dielectric layer 203 to improve the etching selectivity during etching. The patterned photoresist layer 205 has an opening 206 that exposes a portion of the top surface of the etching sacrificial layer 204. When etching is performed subsequently, the patterned photoresist layer 205 is used as a mask to etch the etching stop layer 204 and the second interlayer dielectric layer 203 in sequence along the opening to form a through hole 207 in the second interlayer dielectric layer 203. It should be noted that, during the etching process, the patterned photoresist layer 205 and the etch stop layer 204 can be removed simultaneously, or the patterned photoresist layer 205 and the etch stop layer 204 can also be removed by an additional removal process after the etching is completed. For example, the patterned photoresist layer 205 can be removed by an ashing process, and the etch stop layer 204 can be removed in the subsequent planarization process of forming a metal plug.

[0064] Finally, reference Fig.10 and Fig.11 , or refer to Fig.17 and Fig.18 , or refer to Fig.24 and Fig.25 , forming a metal plug 212 that fills the through hole.

[0065] The material of the metal plug 212 is one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0066] In some embodiments, the process of forming the metal plug 212 includes: Fig.10 , or refer to Fig.17 , or refer to Fig.24 , forming a conductive metal layer 211 in the through hole and on the top surface of the second interlayer dielectric layer 203; referring to Fig.11 , or refer to Fig.18 , or refer to Fig.25 The conductive metal layer 211 above the top surface of the second interlayer dielectric layer 203 is planarized and removed by a chemical mechanical polishing process to form a metal plug 212 in the through hole.

[0067] Some other embodiments of the present application further provide a method for preparing a semiconductor structure, including:

[0068] Providing a first interlayer dielectric layer, wherein the first interlayer dielectric layer has a metal wiring, the top surface of the first interlayer dielectric layer exposes the top surface of the metal wiring, and the top surface of the metal wiring has a recess;

[0069] forming a non-conductive protective layer in the recess, wherein a top surface of the non-conductive protective layer is flush with a top surface of the first interlayer dielectric layer;

[0070] forming a second interlayer dielectric layer on the top surface of the first interlayer dielectric layer, wherein the second interlayer dielectric layer has a through hole exposing at least a portion of the surface of the non-conductive protective layer;

[0071] The non-conductive protective layer is removed along the through hole.

[0072] A metal plug is formed to fill the through hole.

[0073] The main difference between this embodiment and the above-mentioned embodiments is that in this embodiment, the non-conductive protective layer is conductive, and the non-conductive protective layer needs to be removed before forming the metal plug.

[0074] In some embodiments, the non-conductive protective layer is aluminum oxide, and the process of removing the non-conductive protective layer includes wet etching.

[0075] The present application also provides a semiconductor structure, referring to Fig.11 , or refer to Fig.18 , or refer to Fig.25 ,include:

[0076] A first interlayer dielectric layer 201 has a metal wiring 202 in the first interlayer dielectric layer 201. The top surface of the first interlayer dielectric layer 201 exposes the top surface of the metal wiring 202, and the top surface of the metal wiring 202 has a recess 208 (refer to Figure 5 ,or Fig.12 ,or Fig.19 );

[0077] A conductive protection layer 210 located in the recess, wherein a top surface of the conductive protection layer 210 is flush with a top surface of the first interlayer dielectric layer 201;

[0078] A second interlayer dielectric layer 203 located on the top surface of the first interlayer dielectric layer 203, wherein the second interlayer dielectric layer 203 has a through hole exposing at least a portion of the surface of the conductive protection layer 210;

[0079] A metal plug 212 is located in the through hole.

[0080] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0081] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0082] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a first interlayer dielectric layer, wherein the first interlayer dielectric layer has a metal wiring, the top surface of the first interlayer dielectric layer exposes the top surface of the metal wiring, and the top surface of the metal wiring has a recess; forming a conductive protection layer in the recess, wherein a top surface of the conductive protection layer is flush with a top surface of the first interlayer dielectric layer; forming a second interlayer dielectric layer on the top surface of the first interlayer dielectric layer, and forming a through hole in the second interlayer dielectric layer to expose at least a portion of the surface of the conductive protection layer; A metal plug is formed to fill the through hole.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The depression is a butterfly-shaped depression, and the formation process of the depression includes: forming a groove in the first interlayer dielectric layer; forming a first metal material layer in the groove and on the top surface of the first interlayer dielectric layer, and the first metal material layer fills the groove; using a chemical mechanical polishing process to flatten the first metal material layer until the first interlayer dielectric layer is exposed to form the metal wiring, and when performing the chemical mechanical polishing process, the first metal material layer in the groove is over-polished so that the top surface of the metal wiring has a butterfly-shaped depression.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: The depression is a rectangular depression, and the formation process of the depression includes: forming a groove in the first interlayer dielectric layer; initial metal wiring in the groove, and the top surface of the metal wiring is flush with the top surface of the first interlayer dielectric layer; performing a sputtering process, using non-metallic plasma to bombard the top surface of the initial metal wiring, removing part of the thickness of the initial metal wiring, forming the rectangular depression, and the remaining initial metal wiring is the metal wiring.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that: The depression includes a rectangular depression and a butterfly-shaped depression connected to the rectangular depression, and the formation process of the depression includes: forming a groove in the first interlayer dielectric layer; forming a first metal material layer in the groove and on the top surface of the first interlayer dielectric layer, and the first metal material layer fills the groove; using a chemical mechanical polishing process to flatten the first metal material layer until the first interlayer dielectric layer is exposed to form an initial metal wiring, and when performing the chemical mechanical polishing process, the first metal material layer in the groove is over-polished so that the top surface of the initial metal wiring has a butterfly-shaped depression; performing a sputtering process, using non-metallic plasma to bombard the top surface of the initial metal wiring, removing part of the thickness of the initial metal wiring, forming a rectangular depression connected to the butterfly-shaped depression, and deepening the depth of the butterfly-shaped depression, and the remaining initial metal wiring is the metal wiring.

5. The method for preparing a semiconductor structure according to claim 3 or 4, characterized in that: The non-metallic plasma used in the sputtering process includes plasma containing argon or hydrogen.

6. The method for preparing a semiconductor structure according to any one of claims 1 to 4, characterized in that: The conductive protection layer includes a single layer structure of one material selected from Ti, Ta, TiN, TaN, W, and WN, or a stacked layer structure of several materials.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that: The formation process of the conductive protection layer includes: forming a conductive protection material layer in the recess and on the top surface of the first interlayer dielectric layer; planarizing and removing the conductive protection material layer above the top surface of the first interlayer dielectric layer to form the conductive protection layer in the recess.

8. A method for preparing a semiconductor structure, characterized in that: include: Providing a first interlayer dielectric layer, wherein the first interlayer dielectric layer has a metal wiring, the top surface of the first interlayer dielectric layer exposes the top surface of the metal wiring, and the top surface of the metal wiring has a recess; forming a non-conductive protective layer in the recess, wherein a top surface of the non-conductive protective layer is flush with a top surface of the first interlayer dielectric layer; forming a second interlayer dielectric layer on the top surface of the first interlayer dielectric layer, wherein the second interlayer dielectric layer has a through hole exposing at least a portion of the surface of the non-conductive protective layer; The non-conductive protective layer is removed along the through hole. A metal plug is formed to fill the through hole.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: The non-conductive protective layer is aluminum oxide, and the process of removing the non-conductive protective layer includes wet etching.

10. A semiconductor structure, characterized in that: include: A first interlayer dielectric layer, wherein a metal wiring is provided in the first interlayer dielectric layer, a top surface of the first interlayer dielectric layer exposes a top surface of the metal wiring, and the top surface of the metal wiring has a recess; A conductive protection layer located in the recess, wherein a top surface of the conductive protection layer is flush with a top surface of the first interlayer dielectric layer; a second interlayer dielectric layer located on the top surface of the first interlayer dielectric layer, wherein the second interlayer dielectric layer has a through hole exposing at least a portion of the surface of the conductive protection layer; A metal plug is located in the through hole.

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