Semiconductor device and preparation method thereof, and storage system

Abstract

The invention provides a semiconductor device, a preparation method thereof and a storage system, relates to the technical field of semiconductor chips, and aims to solve the problem of how to improve defects such as gaps or cracks of the semiconductor device caused by mechanical stress generated in a wafer cutting process. The embodiment of the invention provides a semiconductor device. The semiconductor device comprises a device body and a first protection layer. The device body includes a plurality of side surfaces. The first protection layer is located on one side of the side surface away from the device body. The first protection layer is arranged between the device body and the cutting channel structure, cutting stress generated in the wafer cutting process is transmitted to the first protection layer and is blocked, and the cutting stress cannot be continuously transmitted to the device body; therefore, the problem of defects such as gaps or cracks of the semiconductor device caused by the cutting stress generated in the cutting process can be improved, and the semiconductor device can be protected.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor device and a manufacturing method thereof, and a storage system. Background Art

[0002] The wafer includes a plurality of device bodies arranged vertically and horizontally and a dicing road structure. The process of separating the wafer into individual device bodies is formed by cutting the wafer along the dicing road.

[0003] During the wafer cutting process, the cutting stress generated during the cutting process can easily lead to defects such as notches or cracks in the device body. Summary of the invention

[0004] The embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, and a storage system, which are intended to solve the problem of how to improve defects such as notches or cracks in the device body caused by cutting stress generated during the wafer cutting process.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] In one aspect, a semiconductor device is provided, comprising: a device body and a first protective layer. The device body comprises a plurality of side surfaces. The first protective layer is located on a side of the side surface away from the device body.

[0007] The semiconductor device provided in the above-mentioned embodiment of the present disclosure includes a first protective layer, and the first protective layer is located on the side of the side surface of the semiconductor device away from the device body. That is to say, on the wafer, the first protective layer can be located between the device body and the cutting path structure. By arranging the first protective layer between the device body and the cutting path structure, the cutting stress generated in the process of cutting the wafer is blocked when it is transmitted to the first protective layer, and the cutting stress cannot continue to be transmitted to the device body, which is beneficial to reduce the situation where the device body is caused by the cutting stress generated in the cutting process. The defects such as notches or cracks are generated, which is beneficial to protect the device body and improve the yield of the cut wafer.

[0008] In some embodiments, at least one of the side surfaces is an inclined surface.

[0009] In some embodiments, at least one of the side surfaces is a flat surface or a curved surface.

[0010] In some embodiments, the device body further includes a bottom surface adjacent to the plurality of side surfaces, and an angle between the bottom surface and at least one of the side surfaces ranges from 80° to 90°.

[0011] In some embodiments, the device body includes a central portion, a sealing ring, and a peripheral portion, the sealing ring is located between the central portion and the peripheral portion, and a peripheral surface of the peripheral portion includes the plurality of side surfaces.

[0012] In some embodiments, the device body further includes a substrate, the central portion, the sealing ring, and the peripheral portion are located on a same side of the substrate, and the substrate includes a bottom surface.

[0013] In some embodiments, the semiconductor device further includes a second protection layer, which is located on a side of the central portion, the sealing ring, and the peripheral portion away from the substrate and is connected to the first protection layer.

[0014] In some embodiments, the material of the first protection layer and / or the second protection layer includes oxide.

[0015] On the other hand, a method for preparing a semiconductor device is provided, comprising: providing a wafer, the wafer comprising a plurality of device bodies and a cutting path structure, the cutting path structure connecting the plurality of device bodies; etching a portion of the cutting path structure from one side of the wafer to replace it with a sacrificial structure; removing the remaining cutting path structure from the other side of the wafer; and removing the sacrificial structure by wet etching to form a plurality of separate semiconductor devices.

[0016] The above-mentioned embodiment removes the sacrificial structure by wet etching, thereby cutting the wafer, which can avoid using cutting tools to cut the wafer, thus avoiding the cutting stress generated during the cutting process, which is beneficial to improving the yield of the cut wafer. At the same time, the method of removing the sacrificial structure by wet etching can separate multiple device bodies at the same time, which is beneficial to improving the cutting efficiency of the wafer compared to the traditional method of cutting wafers, which requires horizontal and vertical cutting in sequence. In addition, the cost of wafer cutting tools is expensive, and the method of cutting wafers in this embodiment does not require the use of special processes or additional equipment, which is beneficial to reducing the cost of cutting wafers.

[0017] In some embodiments, the device body also includes a substrate, which is located on the same side of the central portion, the sealing ring and the peripheral portion of the device body, and the cutting path structure includes a stacked connection layer and a connection substrate, the connection layer is connected to the peripheral portion and is arranged on the same layer, and the connection substrate is connected to the substrate and is arranged on the same layer; etching part of the cutting path structure from one side of the wafer to replace it with a sacrificial structure includes: etching the connection layer and part of the connection substrate to form a groove; forming the sacrificial structure in the groove.

[0018] In some embodiments, the material of the sacrificial structure includes silicon nitride and / or polysilicon.

[0019] In some embodiments, the connection substrate, the substrate and the sacrificial structure are made of the same material; after etching the connection layer and part of the connection substrate, and before forming the sacrificial structure in the groove, it also includes: forming a first protective layer in the groove, the first protective layer covering the side walls of the groove and the bottom of the groove, the first protective layer and the device body together constitute the semiconductor device.

[0020] In some embodiments, while forming the first protection layer in the groove, the method further includes: forming a second protection layer on a side of the device body away from the substrate, wherein the second protection layer, the first protection layer and the device body together constitute the semiconductor device.

[0021] In some embodiments, removing the remaining scribe line structure from the other side of the wafer includes: grinding away the remaining connection substrate from the other side of the wafer.

[0022] In some embodiments, grinding away the remaining connection substrate from the other side of the wafer also includes: grinding away the first protection layer covering the bottom of the groove and a portion of the substrate.

[0023] On the other hand, a storage system is provided, including a semiconductor device and a controller, wherein the semiconductor device is the semiconductor device described above; and the controller is coupled to the semiconductor device to control the semiconductor device to store data.

[0024] It can be understood that the beneficial effects that can be achieved by the method for preparing the semiconductor device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor device mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0026] Figure 1 is a block diagram of an electronic device according to some embodiments;

[0027] Figure 2 is a block diagram of a storage system according to some embodiments;

[0028] Figure 3is a block diagram of a storage system according to some other embodiments;

[0029] Figure 4 is a schematic structural diagram of a wafer according to some embodiments;

[0030] Figure 5 is a schematic structural diagram of a semiconductor device according to some embodiments;

[0031] Figure 6 is a cross-sectional view of a semiconductor device according to some embodiments;

[0032] Figure 7 is a cross-sectional view of a semiconductor device according to some embodiments;

[0033] Figure 8 is a cross-sectional view of a semiconductor device according to some embodiments;

[0034] Fig. 9 is a cross-sectional view of a semiconductor device according to some embodiments;

[0035] Fig.10 is a flow chart of a method for preparing a semiconductor device according to some embodiments;

[0036] Fig.11 is a schematic structural diagram of a semiconductor device manufacturing process according to some embodiments;

[0037] Fig.12 is a schematic structural diagram of a semiconductor device manufacturing process according to some embodiments;

[0038] Fig.13 is a schematic structural diagram of a semiconductor device manufacturing process according to some embodiments;

[0039] Fig.14 is a schematic structural diagram of a semiconductor device manufacturing process according to some embodiments;

[0040] Fig.15 is a schematic structural diagram of a semiconductor device manufacturing process according to some embodiments;

[0041] Fig.16 is a schematic structural diagram of a semiconductor device manufacturing process according to some embodiments;

[0042] Fig.17 is a schematic structural diagram of a semiconductor device manufacturing process according to some embodiments;

[0043] Fig.18 is a schematic structural diagram of a semiconductor device manufacturing process according to some embodiments;

[0044] Fig.19Schematic diagram of the structure of a semiconductor device manufacturing process according to some embodiments.

[0045] Figure numerals: 1. wafer; 10. semiconductor device; 11. device body; 111. side surface; 112. bottom surface; 113. center portion; 114. sealing ring; 115. outer portion; 116. substrate; 12. first protective layer; 13. second protective layer; 20. cutting path structure; 21. connecting layer; 22. connecting substrate; 23. groove; 24. sacrificial structure; 2. electronic device; 3. storage system; 4. circuit board; 5. controller. DETAILED DESCRIPTION

[0046] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0047] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0048] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0049] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0050] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0051] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0052] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0053] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0054] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0055] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0056] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0057] Some embodiments of the present disclosure provide an electronic device. Figure 1 A block diagram of an electronic device provided in some embodiments of the present disclosure. Figure 1 As shown, the electronic device 2 includes a storage system 3 and a circuit board 4. The storage system 3 is electrically connected to the circuit board 4. In addition, the electronic device 2 may also include at least one of a central processing unit (CPU) and a cache.

[0058] Exemplarily, the electronic device 2 can be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0059] Some embodiments of the present disclosure further provide a storage system 3. The storage system 3 can be applied to the above-mentioned electronic device 2. Of course, the storage system 3 can also be applied to other electronic devices 2, and the present disclosure does not limit this.

[0060] Figure 2 3 is a block diagram of a storage system 3 provided in some embodiments of the present disclosure. Figure 2As shown, the storage system 3 includes a controller 5 and a semiconductor device 10. The controller 5 is coupled to the semiconductor device 10 and is configured to control the semiconductor device 10 to store data. The storage system 3 can be integrated into various types of storage devices, for example, included in the same package (for example, a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 3 can be applied to and packaged into different types of electronic products, for example, mobile phones (such as mobile phones), desktop computers, tablet computers, laptops, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices 2 having storage therein.

[0061] In some embodiments, Figure 2 As shown, the storage system 3 includes a controller 5 and a semiconductor device 10, and the storage system 3 can be integrated into a memory card.

[0062] Among them, the memory card includes any one of PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital (SD) card, and UFS.

[0063] In other embodiments, Figure 3 As shown, the storage system 3 includes a controller 5 and a plurality of semiconductor devices 10, and the storage system 3 is integrated into a solid state drive (SSD).

[0064] In the storage system 3, in some embodiments, the controller 5 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices 2 such as personal computers, digital cameras, mobile phones, etc.

[0065] In other embodiments, the controller 5 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, laptops, and enterprise storage arrays.

[0066] In some embodiments, the controller 5 may be configured to manage data stored in the semiconductor device 10 and communicate with an external device (e.g., a host). In some embodiments, the controller 5 may also be configured to control operations of the semiconductor device 10, such as read, erase, and program operations. In some embodiments, the controller 5 may also be configured to manage various functions regarding data stored or to be stored in the semiconductor device 10, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 5 is also configured to process error correction codes regarding data read from or written to the semiconductor device 10.

[0067] Of course, the controller 5 may also perform any other suitable functions, such as formatting the semiconductor device 10 ; for example, the controller 5 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0068] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI Express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics 2 (IDE) protocol, and Firewire protocol.

[0069] The controller 5 may be, for example, a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof.

[0070] Some embodiments of the present disclosure provide a semiconductor device 10. The semiconductor device 10 can be applied to the above-mentioned storage system 3. Of course, the semiconductor device 10 can be applied to other storage systems 3, and the present disclosure does not limit this.

[0071] By way of example, the semiconductor device 10 may be a device such as a flash memory, a dynamic random access memory, or a chip. The semiconductor device 10 includes a device body 11, and by way of example, the device body 11 may include a bare chip. The device body 11 may be formed into the semiconductor device 10 through a subsequent bonding process, a packaging process, and the like. The present disclosure takes the device body 11 as a bare chip as an example to explain the solution to be protected by the present disclosure.

[0072] Figure 4 FIG. 1 is a schematic diagram of the structure of a wafer according to some embodiments. Figure 4 As shown, the wafer 1 includes a cutting road structure 20 and a plurality of device bodies 11 arranged vertically and horizontally. In the process of manufacturing semiconductor devices, it is necessary to cut the plurality of device bodies 11 arranged vertically and horizontally on the wafer 1 into individual device bodies 11, and then further process the device bodies 11 to finally form semiconductor devices. In the process of cutting the wafer 1, a laser or a cutting tool is often used to cut all the longitudinal cutting road structures 20 one by one (or all the transverse cutting road structures 20 can be cut one by one first), and the wafer 1 is cut into a plurality of long strips, and then cut along the transverse cutting road structures 20, and the plurality of long strips of wafer 1 are cut into a plurality of device bodies 11.

[0073] During the above-mentioned process of cutting the wafer 1 , cutting stress is generated by cutting the cutting street structure 20 . The cutting stress is transmitted to the device body 11 , which may easily cause defects such as notches or cracks in the device body 11 , thereby damaging the device body 11 .

[0074] Based on this, some embodiments of the present disclosure provide a semiconductor device. Figure 5 is a schematic structural diagram of a semiconductor device according to some embodiments of the present disclosure, Figure 6 FIG. 1 is a schematic diagram of a semiconductor device according to some embodiments. Figure 5 and Figure 6 As shown, the semiconductor device 10 provided in some embodiments of the present disclosure includes a device body 11 and a first protective layer 12. The device body 11 includes a plurality of side surfaces 111, and the first protective layer 12 is located on a side of the side surface 111 away from the device body 11. It can be understood that the first protective layer 12 is located on a side of the side surface 111 away from the device body 11, and the first protective layer 12 is located on a side of the side surface 111 away from the device body 11. Figure 1 , Figure 5 and Figure 6 It can be seen that on the wafer 1 , the first protection layer 12 is located between the device body 11 and the scribe line structure 20 .

[0075] Exemplarily, the first protection layer 12 may be made of an insulating material, such as an insulating material such as silicon oxide, silicon nitride, and a combination of one or more high dielectric constant insulating materials, or other suitable materials.

[0076] By setting the first protective layer 12 between the device body 11 and the cutting path structure 20, the cutting stress generated in the process of cutting the wafer 1 is blocked from being transmitted to the first protective layer 12, and the cutting stress cannot continue to be transmitted to the device body 11, which is beneficial to reduce defects such as notches or cracks in the device body caused by the cutting stress generated in the cutting process, which is beneficial to protecting the device body 11 and improving the yield of wafer cutting.

[0077] In some embodiments, Figure 5 and Figure 6 As shown, at least one side surface 111 of the device body 11 is an inclined surface. Figure 5 It can be seen that the device body 11 in this embodiment includes four side surfaces 111, wherein the four side surfaces 111 can all be inclined surfaces. It can be understood that when the side surfaces 111 of the device body 11 are inclined surfaces, in the step of cutting the wafer, a wet etching process can be used to etch the cutting road structure to complete the process of cutting the wafer. When the wet etching process is used, an inclined side surface 111 will be formed, and the generation of cutting stress can be avoided, thereby improving the yield of wafer cutting.

[0078] In some embodiments, Figure 6 As shown, at least one side surface 111 of the semiconductor device 10 may be a plane. Exemplarily, the semiconductor device 10 in this embodiment includes four side surfaces 111, and the four side surfaces 111 may all be inclined planes, such as Figure 6 In the figure, the cross section of the semiconductor device 10 is a trapezoid with a narrow top and a wide bottom, and its side surface 111 is an inclined plane. The first protective layer 12 is located on the side of the side mark surface away from the device body 11, which is beneficial to prevent the cutting stress during the cutting process from being transmitted to the device body 11, thereby improving the fragmentation during the cutting process.

[0079] In other embodiments, Figure 7 As shown, at least one side surface 111 of the semiconductor device 10 may be a curved surface (not shown in the figure). Exemplarily, the semiconductor device 10 in this embodiment includes four side surfaces 111, and the four side surfaces 111 may all be inclined curved surfaces, and the side surfaces 111 may be recessed toward the device body 11. The first protective layer 12 is located on the side of the side surface 111 away from the device body 11, which is beneficial to prevent the cutting stress during the cutting process from being transmitted to the device body 11, thereby reducing the fragmentation generated during the cutting process.

[0080] In some embodiments, Figure 6As shown, the device body 11 also includes a bottom surface 112 adjacent to the plurality of side surfaces 111, and the angle between the bottom surface 112 and at least one side surface 111 ranges from 80° to 90°. Exemplarily, the angle between the bottom surface 112 and the side surface 111 can be 80°, 85° or 90°. When the angle between the side surface 111 and the bottom surface 112 of the device body 11 is in the range of 80° to 90°, the side surface 111 of the device body 11 can be an inclined surface, and the top surface of the device body 11 is smaller in area than the bottom surface 112 of the device body 11. Therefore, during the cutting process of the wafer 1, the debris generated by splashing when the cutting road structure 20 is cut is not easy to fall onto the top surface of the device body 11, so it is beneficial to protect the semiconductor device 10.

[0081] In some embodiments, Figure 5 and Figure 6 As shown, the device body 11 includes a central portion 113, a sealing ring 114 and a peripheral portion 115. The sealing ring 114 is located between the central portion 113 and the peripheral portion 115. The peripheral surface of the peripheral portion 115 includes a plurality of side surfaces 111. Figure 5 As shown, the peripheral surface of the outer portion 115 includes four side surfaces 111. Figure 6 As shown, the first protective layer 12 is located on the side of the side surface 111 away from the device body 11, that is, the first protective layer 12 is located on the side of the peripheral surface of the outer portion 115 away from the device body 11. Through the above arrangement, it is beneficial to improve the fragmentation generated during the cutting process and to protect the semiconductor device 10.

[0082] Figure 8 is a cross-sectional view of a semiconductor device according to some embodiments.

[0083] In some embodiments, Figure 8 As shown, the device body 11 also includes a substrate 116. The central portion 113, the sealing ring 114 and the peripheral portion 115 are located on the same side of the substrate 116, and the substrate 116 includes a bottom surface 112. The central portion 113 of the device body 11 may include a functional circuit. The sealing ring 114 seals the central portion 113 and isolates the central portion 113 from the peripheral portion 115, which is beneficial to protecting the internal circuit of the chip. In this embodiment, the side surface 111 of the device body 11 is the peripheral surface of the peripheral portion 115, and the bottom surface 112 of the device body 11 is the bottom surface 112 of the substrate 116. A first protective layer 12 is provided on the surface of the peripheral portion 115 on the side away from the central portion 113 and the sealing ring 114, which is beneficial to prevent the cutting stress generated in the process of cutting the wafer 1 from continuing to be transmitted to the device body 11, thereby reducing the situation of broken pieces, which is beneficial to improving the yield of cutting the semiconductor device 10.

[0084] Fig. 9is a cross-sectional view of a semiconductor device according to some embodiments.

[0085] In the process of cutting the wafer 1, using a cutting tool to cut the cutting path structure 20 of the wafer 1 will generate flying powder, which is easy to damage the semiconductor device 10. Based on this, in some embodiments, such as Fig. 9 As shown, the semiconductor device 10 further includes a second protection layer 13, which is located on the side of the central portion 113, the sealing ring 114 and the peripheral portion 115 away from the substrate 116 and connected to the first protection layer 12. Fig. 9 In the embodiment, the second protective layer 13 is located on the side of the top surface of the device body 11 away from the device body 11, and the second protective layer 13 is connected to the first protective layer 12. When cutting the cutting path structure 20 of the wafer 1, generally the cutting starts from the top surface of the wafer 1, and the second protective layer 13 can block the splashing powder generated during the cutting. In addition, if the wafer 1 is cut by a wet etching process to remove the cutting path structure 20 to separate a plurality of semiconductor devices 10, the first protective layer 12 and the second protective layer 13 have the function of protecting the semiconductor device 10 and preventing the semiconductor device 10 from being etched by the etching solution. Moreover, since the second protective layer 13 is connected to the first protective layer 12, in the process of manufacturing the semiconductor device 10, the first protective layer 12 and the second protective layer 13 can be formed together, which is beneficial to the manufacturing, and at the same time, the manufacturing steps are saved and the manufacturing process difficulty is reduced. In this embodiment, by providing the second protective layer 13 on the top surface of the device body 11, it is beneficial to protect the semiconductor device 10 and prevent the splashing powder generated during the cutting process from damaging the semiconductor device 10.

[0086] In some embodiments, Fig. 9 As shown, the constituent material of the first protective layer 12 may include oxides, such as silicon oxide. The first protective layer 12 is located on the side of the side mark surface away from the device body 11, which is beneficial to prevent the cutting stress during the cutting process from being transmitted to the device body 11, thereby reducing the fragmentation during the cutting process. The constituent material of the second protective layer 13 may also include oxides, such as silicon oxide. The second protective layer 13 is provided on the side of the top surface of the device body 11 away from the device body 11, which is beneficial to protecting the semiconductor device 10 and preventing the splashing powder generated during the cutting process from damaging the semiconductor device 10.

[0087] Fig.10 is a flow chart of a method for manufacturing a semiconductor device according to some embodiments.

[0088] Some embodiments of the present disclosure also provide a method for preparing a semiconductor device 10, such as Fig.10 As shown, it includes: S1~S4.

[0089] S1: providing a wafer, wherein the wafer includes a plurality of device bodies and a cutting path structure, wherein the cutting path structure connects the plurality of device bodies.

[0090] Fig.11 Schematic diagram of the structure of a semiconductor device manufacturing process according to some embodiments.

[0091] In the above steps, refer to Figure 8 and Fig.11 The wafer 1 includes a plurality of device bodies 11 and a cutting road structure 20, and the cutting road structure 20 is located between adjacent device bodies 11. The device body 11 also includes a substrate 116, and the substrate 116 is located on the same side of the central portion 113, the sealing ring 114 and the peripheral portion 115 of the device body 11. The plurality of device bodies 11 and the cutting road structure 20 are located together on one side of the substrate 116. The cutting road structure 20 includes a stacked connection layer 21 and a connection substrate 22, and the connection layer 21 is connected to the peripheral portion 115 and is arranged in the same layer. The connection substrate 22 is connected to the substrate 116 and is arranged in the same layer. Through the above arrangement, it is convenient to separate the plurality of device bodies 11 on the wafer 1 later.

[0092] The “same-layer arrangement” here and in the following text refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask template through a single patterning process.

[0093] S2: Etching a portion of the saw street structure from one side of the wafer to replace it with a sacrificial structure.

[0094] Fig.12 FIG. 1 is a schematic diagram of a semiconductor device manufacturing process according to some embodiments. Fig.12 , etching part of the scribe line structure 20 from one side of the wafer 1 (generally the side away from the substrate 116). Exemplarily, in the above steps, a dry or wet etching process may be used to remove the connection layer 21 and part of the connection substrate 22 of the scribe line structure 20.

[0095] When a wet etching process is used in this step to remove part of the cutting path structure 20, since the etching liquid used in the wet etching process will penetrate into both sides of the cutting path structure 20, after the wet etching process is used to remove part of the cutting path structure 20, the side surface 111 of the device body 11 will form an inclined surface, or a surface that is recessed into the inside of the device body 11.

[0096] Fig.13 FIG. 1 is a schematic diagram of a semiconductor device manufacturing process according to some embodiments. Fig.11 , Fig.12 and Fig.13 The above steps can etch the connection layer 21 and a portion of the connection substrate 22 to form a groove 23. After the groove 23 is formed, a sacrificial material is deposited in the groove 23 to form a sacrificial structure 24 in the groove 23.

[0097] In some embodiments, Fig.13 As shown, the material of the sacrificial structure includes silicon nitride or polysilicon.

[0098] For example, the sacrificial structure may include silicon nitride. Alternatively, the sacrificial structure may include polysilicon. Alternatively, the sacrificial structure may include silicon nitride and polysilicon. In this way, it is beneficial to remove the sacrificial structure 24 by etching or the like in subsequent processes, so that the multiple semiconductor devices 10 on the wafer 1 are separated into separate semiconductor devices 10.

[0099] In the above steps, since the constituent materials of the substrate 116 and the connecting substrate 22 include polysilicon, when the material forming the sacrificial structure 24 includes polysilicon, the semiconductor device 10 will be damaged when the sacrificial structure 24 is removed by a subsequent wet etching process. Fig.14 is a schematic structural diagram of a semiconductor device manufacturing process according to some embodiments, Fig.15 FIG. 1 is a schematic diagram of a semiconductor device manufacturing process according to some embodiments. Fig.11 , Fig.12 , Fig.13 , Fig.14 and Fig.15 As shown, it is necessary to form a first protective layer 12 in the groove 23 after etching the connection layer 21 and part of the connection substrate 22, and before forming the sacrificial structure 24 in the groove 23. The first protective layer 12 covers the sidewalls of the groove 23 and the bottom of the groove 23, and the first protective layer 12 and the device body 11 together constitute the semiconductor device 10. Exemplarily, a deposition process can be used to form the first protective layer 12. The constituent materials of the first protective layer 12 may include silicon oxide, silicon nitride or other suitable insulating materials. Through the above arrangement, when the sacrificial structure 24 is subsequently removed to separate a plurality of semiconductor devices 10, the first protective layer 12 can prevent the etching solution from contacting the semiconductor device 10, which is beneficial to prevent the semiconductor device 10 from being etched.

[0100] In some embodiments, Fig.15 As shown, while the first protection layer 12 is formed in the groove 23 , the second protection layer 13 is also formed on the side of the device body 11 facing away from the substrate 116 . The second protection layer 13 , the first protection layer 12 and the device body 11 together constitute the semiconductor device 10 .

[0101] In the above steps, the first protective layer 12 and the second protective layer 13 can be formed by a single deposition process, which is beneficial to improving the manufacturing efficiency. At the same time, the second protective layer 13 is located on the side of the device body 11 away from the substrate 116, which is beneficial to protect the device body 11 from being damaged by the etching solution, thereby improving the yield of the wafer 1 cutting.

[0102] S3: Removing the remaining scribe line structure from the other side of the wafer.

[0103] Usually, before wafer 1 is cut, the excess base material on the back side of wafer 1 (i.e., the side with substrate 116) needs to be ground to remove a certain thickness of material to meet the requirements of chip packaging thickness and surface roughness, as well as the physical strength, heat dissipation and size requirements of the chip. This process is called wafer 1 thinning process.

[0104] Fig.16 FIG. 1 is a schematic diagram of a semiconductor device manufacturing process according to some embodiments. Fig.16 In the above steps, after a portion of the scribe line structure 20 is etched from one side of the wafer 1 and replaced with the sacrificial structure 24, the remaining scribe line structure 20 is removed from the other side of the wafer 1 (the side of the substrate 116). Exemplarily, the wafer 1 thinning process can be used to remove the remaining scribe line structure 20 until the sacrificial structure 24 is exposed.

[0105] In the above steps, the remaining connection substrate 22 is also ground off from the other side of the wafer 1. Fig.16 and Fig.17 As shown, after grinding off the remaining connection substrate 22 from the other side of the wafer 1 (one side of the substrate 116), the sacrificial structure 24 is exposed, which is conducive to the use of a wet etching process to remove the sacrificial structure 24 in the subsequent process, thereby separating the various semiconductor devices 10 on the wafer 1. The method of removing the sacrificial structure 24 by wet etching, thereby cutting the wafer 1, avoids the use of cutting tools to cut the wafer 1, and also avoids the situation where the semiconductor device 10 is broken, which is conducive to improving the yield of cutting the wafer 1. At the same time, the method of removing the sacrificial structure 24 by wet etching can separate multiple semiconductor devices 10 at the same time, compared with the traditional method of cutting the wafer 1, which requires horizontal and vertical cutting in sequence, which is conducive to improving the cutting efficiency of the wafer 1. In addition, the cost of the wafer 1 cutting tool is expensive, and the method of cutting the wafer 1 in this embodiment does not require the use of a special process, nor does it require additional equipment, which is conducive to reducing the cost of cutting the wafer 1.

[0106] Fig.17 FIG. 1 is a schematic diagram of a semiconductor device manufacturing process according to some embodiments. Fig.17 As shown, when the semiconductor device 10 includes the first protective layer 12, the above steps further include: grinding away the first protective layer 12 covering the bottom of the groove 23, and a portion of the substrate 116. In the above steps, while grinding away the remaining connection substrate 22 on one side of the substrate 116 of the wafer 1, the first protective layer 12 covering the bottom of the groove 23, and a portion of the substrate 116 are ground away to expose the sacrificial structure 24, so as to facilitate the subsequent removal of the sacrificial structure 24 by a wet etching process to separate multiple semiconductor devices 10.

[0107] S4: removing the sacrificial structure by wet etching to form a plurality of separated semiconductor devices.

[0108] Fig.18 is a schematic structural diagram of a semiconductor device manufacturing process according to some embodiments, Fig.19 FIG. 1 is a schematic diagram of a semiconductor device manufacturing process according to some embodiments. Fig.16 , Fig.17 , Fig.18 and Fig.19 In the above steps, wet etching is used to remove the sacrificial structure 24, so as to separate the multiple semiconductor devices 10 on the wafer 1, and thus a plurality of separated semiconductor devices 10 can be formed. In this step, the sacrificial structure 24 is removed by wet etching, so as to cut the wafer 1, thereby avoiding the use of cutting tools to cut the wafer 1, and thus avoiding the situation where the device body 11 is broken, which is beneficial to improving the yield of cutting the wafer 1. At the same time, the method of removing the sacrificial structure 24 by wet etching can separate multiple device bodies 11 at the same time, which is beneficial to improving the cutting efficiency of the wafer 1 compared to the traditional method of cutting the wafer 1, which requires horizontal and vertical cutting in sequence. In addition, the cost of the wafer 1 cutting tool is expensive, and the method of cutting the wafer 1 in this embodiment does not require the use of special processes, nor does it require new equipment, which is beneficial to reducing the cost of cutting the wafer 1.

[0109] Since the first protective layer 12 is formed in the groove 23 before the sacrificial structure 24 is formed in the groove 23, when the sacrificial structure 24 is removed by wet etching in the above step, the first protective layer 12 can block the etching solution from contacting the semiconductor device 10, thereby preventing the semiconductor device 10 from being etched, which is beneficial to improving the yield of wafer cutting.

[0110] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: a device body, the device body comprising a plurality of side surfaces; A first protective layer is located on a side of the side surface away from the device body.

2. The semiconductor device according to claim 1, wherein: At least one of the side surfaces is an inclined surface.

3. The semiconductor device according to claim 2, characterized in that At least one of the side surfaces is a flat surface or a curved surface.

4. The semiconductor device according to claim 2, characterized in that The device body further includes a bottom surface adjacent to the plurality of side surfaces, and an angle between the bottom surface and at least one of the side surfaces ranges from 80° to 90°.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that: The device body includes a central portion, a sealing ring, and a peripheral portion, the sealing ring being located between the central portion and the peripheral portion, and a peripheral surface of the peripheral portion including the plurality of side surfaces.

6. The semiconductor device according to claim 5, characterized in that The device body further includes a substrate, the central portion, the sealing ring, and the peripheral portion are located on a same side of the substrate, and the substrate includes a bottom surface.

7. The semiconductor device according to claim 6, characterized in that The semiconductor device further includes a second protection layer, which is located on a side of the central portion, the sealing ring, and the peripheral portion away from the substrate and is connected to the first protection layer.

8. The semiconductor device according to claim 7, characterized in that The material of the first protection layer and / or the second protection layer includes oxide.

9. A method for preparing a semiconductor device, characterized in that: include: Providing a wafer, the wafer comprising a plurality of device bodies and a dicing road structure, the dicing road structure connecting the plurality of device bodies; Etching a portion of the scribe line structure from one side of the wafer to replace it with a sacrificial structure; removing the remaining scribe line structure from the other side of the wafer; The sacrificial structure is removed by wet etching to form a plurality of separated semiconductor devices.

10. The method for preparing a semiconductor device according to claim 9, characterized in that: The device body further includes a substrate, which is located on the same side of the central portion, the sealing ring and the peripheral portion of the device body, and the cutting path structure includes a connection layer and a connection substrate which are stacked, the connection layer is connected to the peripheral portion and arranged in the same layer, and the connection substrate is connected to the substrate and arranged in the same layer; The etching of a portion of the scribe line structure from one side of the wafer to replace it with a sacrificial structure comprises: Etching the connection layer and a portion of the connection substrate to form a groove; The sacrificial structure is formed in the groove.

11. The method for preparing a semiconductor device according to claim 10, characterized in that: The material of the sacrificial structure includes silicon nitride and / or polysilicon.

12. The method for preparing a bare semiconductor device according to claim 10 or 11, characterized in that: The connecting substrate, the substrate and the sacrificial structure are made of the same material; after etching the connecting layer and part of the connecting substrate and before forming the sacrificial structure in the groove, the method further includes: A first protective layer is formed in the groove, the first protective layer covers the sidewalls of the groove and the bottom of the groove, and the first protective layer and the device body together constitute the semiconductor device.

13. The method for preparing a semiconductor device according to claim 12, characterized in that: While forming the first protection layer in the groove, the method further includes: forming a second protection layer on a side of the device body away from the substrate, wherein the second protection layer, the first protection layer and the device body together constitute the semiconductor device.

14. The method for preparing a semiconductor device according to claim 13, characterized in that: The removing the remaining scribe line structure from the other side of the wafer includes: grinding away the remaining connection substrate from the other side of the wafer.

15. The method for preparing a semiconductor device according to claim 14, characterized in that: While grinding away the remaining connection substrate from the other side of the wafer, the method also includes: grinding away the first protection layer covering the bottom of the groove and a portion of the substrate.

16. A storage system, characterized in that: include: A semiconductor device, wherein the semiconductor device is the semiconductor device according to any one of claims 1 to 8; The controller is coupled to the semiconductor device to control the semiconductor device to store data.

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