An FCBGA package structure

Abstract

This invention relates to the field of chip packaging, and more particularly to an FCBGA packaging structure. It includes a substrate for mounting an MXG100 chip. Two memory pin connection areas are symmetrically arranged on the substrate, with the axes of symmetry of the two memory pin connection areas coinciding with the axes of symmetry of two dynamic random access memory (DRAM) interface areas. Based on the symmetrical layout of the GDDR PHY in the MXG100 chip, this invention also symmetrically arranges two memory pin connection areas, allowing for the reuse of connection schemes within the two memory pin connection areas. Furthermore, the pin arrangement in each unit pin connection area within each memory pin connection area is identical, thereby improving the reusability of pin arrangement schemes. Additionally, during subsequent simulation verification, only the connection scheme with the longest trace distance needs to be processed. This reduces the number of simulation verifications and improves GPU development efficiency.

Description

Technical Field

[0001] This invention relates to the field of chip packaging, and more particularly to an FCBGA packaging structure. Background Technology

[0002] With technological advancements, technologies demanding higher graphics rendering acceleration have emerged, such as AI-powered graphics and the Metaverse. To meet these requirements, current graphics cards are designed using large-size FCBGA (Flip Chip Ball Grid Array) packaging structures, and feature high-performance graphics chips and more video memory. The graphics chip determines the functions and basic performance of the graphics card, while its overall performance largely depends on the video memory. The video memory capacity determines the output resolution, while the computing power of the graphics chip determines the output efficiency. This, in turn, improves rendering efficiency and image resolution.

[0003] However, in current technologies, the placement of GDDRPHY (Graphics Double Data Rate Physical, the chip that provides the external signal interface to video memory) and GDDR (Graphics Double Data Rate, video memory) chips is irregular during GPU (graphics processing unit) design. This necessitates separate layout and routing designs for each channel during package and PCB design, resulting in different layouts and routing schemes for each channel. Consequently, simulation verification of all channels on the board is required later. This leads to a large number of verification operations, which are time-consuming, labor-intensive, and prone to introducing errors, thus reducing GPU development efficiency. Summary of the Invention

[0004] In view of this, the present invention provides an FCBGA packaging structure that at least partially solves the problems existing in the prior art.

[0005] According to one aspect of the present invention, an FCBGA package structure is provided, comprising:

[0006] The substrate is used to mount the MXG100 chip. Two memory pin connection areas are symmetrically arranged on the substrate, adjacent to the two dynamic random access memory (DRAM) interface areas within the MXG100 chip. These DRAM interface areas are the PHY locations corresponding to the DRAMs within the MXG100 chip. The axes of symmetry of the two memory pin connection areas coincide with the axes of symmetry of the two DRAM interface areas.

[0007] The memory pin connection area includes four identical rectangular cell pin connection areas. Three of these cell pin connection areas are arranged end-to-end along their own length to form a rectangular strip connection area. The long side of the remaining cell pin connection area is arranged adjacent to the short side of the rectangular strip area to form an L-shaped pin connection area.

[0008] The pins of each unit are arranged in the same way in the pin connection area. Each pin in the pin connection area of ​​each unit is electrically connected to the corresponding pin in the PHY of the MXG100 chip.

[0009] Furthermore, the unit pin connection area includes data line connection pins, address line connection pins, and digital ground connection pins.

[0010] The data line connection pins are located on the side closer to the MXG100 chip placement area, and the address line connection pins are located on the side closer to the edge of the substrate.

[0011] Each data line connector has a corresponding digital ground connector arranged adjacent to each other on each side.

[0012] Each address line connection pin has at least three corresponding digital ground connection pins arranged adjacent to it.

[0013] Furthermore, the unit pin connection area includes data line connection pins, address line connection pins, and digital ground connection pins.

[0014] The data line connection pins are located on the side closer to the MXG100 chip placement area, and the address line connection pins are located on the side closer to the edge of the substrate.

[0015] Multiple data line connection pins belonging to the same group are arranged sequentially and adjacently in a corresponding first preset data pin area.

[0016] Multiple address line connection pins belonging to the same group are arranged adjacently in a corresponding second preset data pin area.

[0017] A corresponding third preset data pin area is sandwiched between any two adjacent first preset data pin areas.

[0018] A corresponding third preset data pin area is sandwiched between any two adjacent second preset data pin areas. The third preset data pin area is a line-shaped pin area formed by multiple digital ground connection pins arranged sequentially.

[0019] Furthermore, the dynamic random access memory is GDDR6 DRAM.

[0020] Furthermore, at least two circuit trace layers are provided on the inner side of the substrate. The traces of the data line connection pins are located in the inner circuit trace layer, and the traces of the data line connection pins and the digital ground connection pins are located in the same circuit trace layer.

[0021] Furthermore, the substrate also has a chip power pin area and multiple other device pin areas.

[0022] The chip power pin area is the pin area corresponding to the orthographic projection area below the mounting position of the MXG100 chip on the substrate.

[0023] Multiple other device pin areas are respectively arranged in the pin connection areas above and below the chip power pin area.

[0024] Furthermore, it also includes:

[0025] The PCB graphics card motherboard has its base plate electrically connected to the PCB graphics card motherboard.

[0026] There are 16 GDDR6 DRAMs, with 8 GDDR6 DRAMs on each side of the PCB graphics card motherboard.

[0027] The eight GDDR6 DRAM chips on the same side of the PCB graphics card motherboard are symmetrically arranged in two groups. The axis of symmetry of the two groups of GDDR6 DRAM chips is the same as the axis of symmetry of the two memory pin connection areas.

[0028] Each GDDR6 DRAM in the same group has the same relative position to the corresponding rectangular cell pin connection area. The connection traces for each GDDR6 DRAM and its corresponding rectangular cell pin connection area are identical.

[0029] Furthermore, the PCB graphics card motherboard includes multiple layers of circuit traces.

[0030] The connection traces between the address line pins and the GDDR6 DRAM are located on the upper surface layer of the PCB graphics card motherboard.

[0031] Furthermore, the data cable connection pins and the GDDR6 DRAM connection traces are located on the inner circuit trace layer of the PCB graphics card motherboard.

[0032] Furthermore, other device pin areas include the pin areas corresponding to the PCIe module, Display module, and SerDes module, respectively.

[0033] The technical solution of the present invention has at least the following beneficial effects:

[0034] The packaging structure of this invention uses the MXG100 chip, which includes eight GDDR PHYs arranged symmetrically in two groups about the center line of the MXG100 chip. Based on the layout characteristics of the GDDR PHYs in the chip, two memory pin connection areas are also symmetrically arranged on the substrate, respectively for pin connections with the GDDR PHYs in the two groups. Furthermore, according to the L-shaped layout of each memory pin connection area, it is divided into four identical rectangular unit pin connection areas, which are arranged in an L-shape. The pin arrangement of each type within each unit pin connection area is identical.

[0035] like Figure 8 As shown, each GDDR PHY connects to a corresponding external GDDR chip, and their functions are identical during use. Therefore, given sufficient space, the reuse rate of the connection scheme (pin arrangement and wiring scheme) between each GDDR PHY and its corresponding external GDDR chip can be maximized. This eliminates the need for repeated simulation verification of the reused connection scheme and reduces the number of errors in the connection scheme design, thereby improving GPU development efficiency.

[0036] This invention first utilizes the symmetrical layout of the GDDR PHY in the MXG100 chip, symmetrically arranging two memory pin connection areas, thus allowing for the reuse of connection schemes within these two areas. Furthermore, the pin arrangement within each unit pin connection area of ​​each memory pin connection area is identical, further improving the reusability of pin arrangement schemes. This, in turn, reduces the number of simulation verification iterations and improves GPU development efficiency.

[0037] Furthermore, since the routing schemes between the various cell pin connection areas within the same memory pin connection area and their corresponding GDDR PHY differ only in routing distance, during later simulation verification, if the connection scheme with the longest routing distance meets the requirements, the other connection schemes will also necessarily meet the requirements. This further reduces the number of simulation verifications and improves GPU development efficiency. Attached Figure Description

[0038] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1This is a schematic diagram of the arrangement of the pin areas of each device on the substrate in one embodiment of this application.

[0040] Figure 2 This is a schematic diagram of the connection structure between the substrate and the MXG100 chip in another embodiment of this application.

[0041] Figure 3 This is a schematic diagram of the connection structure between the DQ and CA pins of the GDDR PHY in the MXG100 chip and the corresponding pins on the substrate in another embodiment of this application. The right side is a partial enlarged view of the area selected in the middle box on the left.

[0042] Figure 4 This is a schematic diagram showing the overall arrangement of pins in the unit pin connection area in another embodiment of this application, where DQ:VSS = 1:1 and CA:VSS = 1:1.

[0043] Figure 5 This is a schematic diagram showing the overall arrangement of pins in the unit pin connection area in another embodiment of this application, with DQ:VSS = 2:1 and CA:VSS = 2:1.

[0044] Figure 6 The following is an experimental result of inter-group crosstalk in another embodiment of this application when the unit pin connection area is arranged according to two pin layouts, wherein the horizontal axis is the communication frequency of the DQ pin and the vertical axis is the crosstalk value of the DQ pin.

[0045] Figure 7 This is a schematic diagram illustrating the connection between the FCBGA package structure and the PCB graphics card motherboard in another embodiment of this application.

[0046] Figure 8 This is a schematic diagram of a GPU reuse design in another embodiment of this application.

[0047] Figure 9 This is a pinout diagram of a GDDR6 DRAM chip in another embodiment of this application.

[0048] Figure Labels

[0049] 1. Substrate; 10. Chip power pin area; 11. Unit pin connection area; 12. Memory pin connection area; 13. Other device pin area; 2. MXG100 chip; 3. PCB graphics card motherboard; 4. Dynamic random access memory. Detailed Implementation

[0050] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0051] It should be noted that, unless otherwise specified, the following embodiments and features can be combined with each other. Furthermore, all other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0052] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0053] As one embodiment of the present invention, such as Figure 1 and Figure 2 As shown, an FCBGA package structure is provided, including: substrate 1.

[0054] Substrate 1 is used to mount MXG100 chip 2. Specifically, MXG100 chip 2 and substrate 1 are connected using FCBGA packaging. Substrate 1 has a chip power pin area 10 and multiple other device pin areas 13.

[0055] like Figure 1 As shown, the chip power pin area 10 ( Figure 1 The area highlighted by the dashed line is the pin area corresponding to the orthographic projection area below the mounting position of the MXG100 chip 2 on substrate 1. Pin areas 13 for multiple other devices ( Figure 1 The areas (selected by solid lines) are respectively located above and below the chip power pin area 10 in the pin connection areas. Other device pin areas 13 include: pin areas corresponding to the PCIe module, Display module, and SerDes module.

[0056] The MXG100 chip 2 has multiple PHY modules distributed around it, including a PCIe (Peripheral Component Interconnect express, high-speed serial computer expansion bus standard) module, a Display module, a Serdes (serializer / deserializer) module, and a GDDR module.

[0057] Furthermore, the arrangement of these modules is characterized by the following features: the PHYs of the PCIe, Display, and SerDes modules are primarily concentrated in the upper and lower boundary regions of the MXG100 chip 2, with the PHYs in the upper boundary region mainly concentrated in the middle. The remaining GDDR PHYs are symmetrically distributed in the left and right boundary regions of the MXG100 chip 2, as well as the empty space in the upper boundary region. This forms an inverted "L"-shaped arrangement.

[0058] Based on the layout characteristics of each PHY in the above chip, two memory pin connection areas 12 are symmetrically arranged on the substrate 1. Figure 1 The area selected by the dashed line in the middle, with the axis of symmetry as... Figure 1 As shown by the dashed lines, the two memory pin connection areas 12 are respectively located near the interface areas of the two dynamic random access memories (DRAMs) 4 in the MXG100 chip 2. The interface areas of the DRAMs 4 are the areas where the PHY corresponding to the DRAMs 4 in the MXG100 chip 2 is located. The axis of symmetry of the two memory pin connection areas 12 coincides with the axis of symmetry of the two interface areas of the DRAMs 4. The DRAM 4 is GDDR6 DRAM. Specifically, the GDDR6 DRAM chip can be: Samsung K4ZAF325BC-SC24, K4ZAF325BC-SC20, or K4ZAF325BC-SC16.

[0059] like Figure 1 As shown, the memory pin connection area 12 includes four identical rectangular cell pin connection areas 11. Three of the cell pin connection areas 11 are arranged end to end along their own length direction to form a rectangular strip connection area. The long side of the remaining cell pin connection area 11 is arranged adjacent to the short side of the rectangular strip area to form an L-shaped pin connection area.

[0060] The pin arrangement of each type in the pin connection area 11 of each unit is the same, and each pin in the pin connection area 11 of each unit is electrically connected to the corresponding pin in the PHY of the MXG100 chip 2.

[0061] In this invention, based on the symmetrical layout of the GDDR PHY in the MXG100 chip 2, two memory pin connection areas 12 are also symmetrically arranged, allowing for the reuse of connection schemes in the two memory pin connection areas 12. Furthermore, the pin arrangement in each unit pin connection area 11 within each memory pin connection area 12 is identical, further improving the reusability of pin arrangement schemes. This, in turn, reduces the number of simulation verification iterations and improves GPU development efficiency.

[0062] Furthermore, since the routing schemes between the various cell pin connection areas 11 and the corresponding GDDRPHY within the same memory pin connection area 12 differ only in routing distance, subsequent electrical performance simulations will ensure that as long as the connection scheme with the longest routing distance meets the requirements, the other connection schemes will also necessarily meet the requirements. This avoids extracting all channels on the entire board, further reducing the number of simulation verifications and improving GPU development efficiency.

[0063] As another embodiment of the present invention, such as Figure 3 and Figure 4 As shown, the unit pin connection area 11 includes data line connection pins (DQ grid area in the figure), address line connection pins (CA grid area in the figure), and digital ground connection pins (VSS grid area in the figure).

[0064] The unit pin connection area 11 is a pin area on the substrate 1 used for connection with the GDDR PHY. The pin types included are the same as those in the GDDR PHY, which is prior art in this field and will not be described in detail here.

[0065] However, different types of pins have different signal transmission rates and different requirements for signal transmission quality. Specifically, data line connection pins have the highest requirements for signal transmission quality, followed by address line connection pins.

[0066] like Figure 3 As shown, the data line connection pins are positioned near the MXG100 chip 2 mounting area, and the address line connection pins are positioned near the edge of the substrate 1. The substrate 1 has two circuit trace layers on its inner side. The traces for the data line connection pins are located on the inner circuit trace layer, while the traces for the address line connection pins, data line connection pins, and digital ground connection pins are located on the same circuit trace layer.

[0067] like Figure 3 As shown, this arrangement offers the following two advantages:

[0068] Firstly, since the number of circuit routing layers in substrate 1 is relatively small, the routing of address line connection pins, data line connection pins, and digital ground connection pins will be placed in the same layer as much as possible to reduce space occupation. Secondly, since the distribution area of ​​data line connection pins in the GDDR6 PHY is basically symmetrical about the distribution area of ​​address line connection pins, the current pin distribution method is less likely to result in connection line crossings during routing, thus facilitating routing.

[0069] Secondly, this arrangement facilitates the routing of connections between the pins on the substrate 1 and the corresponding pins on the PCB graphics card motherboard 3.

[0070] Specifically, the PCB graphics card motherboard 3 includes multiple circuit trace layers.

[0071] Because the data line connection pins have higher requirements for signal transmission quality, the connection traces between the data line connection pins and the GDDR6 DRAM are located on the inner layer of the PCB graphics card motherboard 3. The address line connection pins have slightly lower requirements for signal transmission quality, so the connection traces between the address line connection pins and the GDDR6 DRAM are located on the upper layer of the PCB graphics card motherboard 3.

[0072] Meanwhile, since the address line connection pin area is closer to the edge of the substrate 1, there is no need to avoid the vias on the PCB graphics card motherboard 3 when routing the traces, resulting in a more complete routing area and making it easier to arrange the traces.

[0073] Each data line connector has a corresponding digital ground connector arranged adjacent to each other on each side.

[0074] Each address line connection pin has at least three corresponding digital ground connection pins arranged adjacent to it.

[0075] The pin arrangement in this embodiment is as follows: Figure 4 As shown, the overall arrangement is DQ:VSS = 1:1 and CA:VSS = 1:1.

[0076] During signal transmission, if the distance between two pins is too close, crosstalk can easily occur, and the impact of crosstalk is greater at higher transmission rates. To reduce the crosstalk between adjacent pins, in this embodiment, a corresponding digital ground connection pin is arranged adjacent to each side of each data line connection pin to increase the spacing between any two adjacent data line connection pins, thereby reducing the impact of crosstalk. Simultaneously, since the number of pins in the entire unit pin connection area 11 is limited, the pins with lower signal transmission quality requirements are arranged with higher density. In this embodiment, priority is given to ensuring the density of data line connection pins and address line connection pins. The remaining pins are set according to existing pin arrangement rules, specifically as follows... Figure 4 As shown.

[0077] As another embodiment of the present invention, such as Figure 3 and Figure 5 As shown, the unit pin connection area 11 includes data line connection pins, address line connection pins, and digital ground connection pins.

[0078] like Figure 3 As shown, the data line connection pin (DQ) is located near the MXG100 chip 2 placement area, and the address line connection pin (CA) is located near the edge of the substrate 1.

[0079] The arrangement is the same as the scheme in the above embodiments, and will not be described again here.

[0080] Multiple data line connection pins belonging to the same group are arranged sequentially and adjacently in a corresponding first preset data pin area.

[0081] Multiple address line connection pins belonging to the same group are arranged adjacently in a corresponding second preset data pin area.

[0082] The pin arrangement in this embodiment is as follows: Figure 5 As shown, the overall arrangement is DQ:VSS = 2:1, CA:VSS = 2:1.

[0083] The specific pin grouping mentioned above is based on the GDDR6 DRAM chip. The manufacturer defines the specific pin grouping within the GDDR6 DRAM chip; for example, DQ0-DQ07 form one group, and DQ8-DQ015 form another. In this embodiment, pins belonging to the same group are grouped together, thereby saving placement space. Specifically, as shown... Figure 4 and Figure 5 As shown, Figure 5 The pin arrangement method in the middle is more than Figure 4 The pin arrangement in the middle saves 24 pins.

[0084] A corresponding third preset data pin area is sandwiched between any two adjacent first preset data pin areas.

[0085] A corresponding third preset data pin area is sandwiched between any two adjacent second preset data pin areas. The third preset data pin area is a line-shaped pin area formed by multiple digital ground connection pins arranged sequentially.

[0086] Because crosstalk between different data line groups has a greater impact, a third preset data pin area is inserted between two adjacent pin groups. This increases the distance between different adjacent pins, thereby reducing the impact of crosstalk. Additionally, in this embodiment... Figure 5 As shown, multiple first preset data pin areas and second preset data pin areas are arranged vertically. Therefore, by setting a third preset data pin area, the trace spacing between two adjacent groups can be increased, which can reduce crosstalk generated between different groups at the traces.

[0087] In this embodiment, because the signal transmission of pins in the same group is highly consistent, the crosstalk generated is small. At the same time, because the signal transmission frequencies between data line connection pins and address line connection pins differ significantly, the crosstalk between adjacent data line connection pin groups and address line connection pin groups is also relatively small.

[0088] The pin arrangement in this embodiment can save more pin arrangement area while reducing the impact of crosstalk, making it more suitable for chips with limited pin area on substrate 1.

[0089] like Figure 6 The image shows the crosstalk effects between pin groups for two different pin layouts of the same GDDR PHY. Specifically, it shows the crosstalk values ​​between pins DQ12-B and DQ15-B. The darker lines indicate pin layouts as follows: Figure 5 The image shows the crosstalk results when the overall pinout is arranged in the form of DQ:VSS = 2:1. The light-colored lines represent the pinout as shown. Figure 4 As shown, this is the crosstalk result when the overall arrangement is in the form of DQ:VSS = 1:1.

[0090] As shown in the figure, the crosstalk value gradually increases with the increase of the GDDR PHY operating frequency. However, the crosstalk value of the pin layout scheme represented by the light-colored line is generally smaller than that of the pin layout scheme represented by the dark-colored line.

[0091] As another embodiment of the present invention, such as Figure 7 As shown, it also includes:

[0092] PCB graphics card motherboard 3, substrate 1 is electrically connected to PCB graphics card motherboard 3. This PCB graphics card motherboard 3 is an existing standard graphics card motherboard.

[0093] There are 16 GDDR6 DRAMs, with 8 GDDR6 DRAMs on each of the two sides of the PCB graphics card motherboard 3. The GDDR6 DRAMs are arranged in the same way on both sides of the PCB graphics card motherboard 3.

[0094] In this design, the eight GDDR6 DRAM chips on the same side surface of the PCB graphics card motherboard 3 are symmetrically arranged in two groups. The axis of symmetry of the two groups of GDDR6 DRAM chips is the same as the axis of symmetry of the two memory pin connection areas 12.

[0095] Each GDDR6 DRAM in the same group has the same relative position to the corresponding rectangular cell pin connection area 11. The connection traces between each GDDR6 DRAM and the corresponding rectangular cell pin connection area 11 are identical.

[0096] In this embodiment, 16 GDDR6 DRAMs are configured to increase the size of the video memory and improve the resolution of the rendered image. However, due to the large number of GDDR6 DRAMs, designing and simulating the routing scheme of each one separately would inevitably result in a huge workload.

[0097] In this embodiment, 16 GDDR6 DRAMs are arranged on both sides of the PCB graphics card motherboard 3, and the GDDR6 DRAMs on both sides adopt the same arrangement, so the routing schemes on both sides can be reused.

[0098] Additionally, the eight GDDR6 DRAM chips on the same side are symmetrically arranged in two groups. Although the GDDR6 DRAM chips are arranged in a rotational manner on the PCB graphics card motherboard 3, the pinout of the GDDR6 DRAM chips is a centrally symmetrical figure, as shown in the diagram. Figure 9 As shown. Therefore, when the GDDR6 DRAM is rotated 180°, its pin arrangement is exactly the same as when the GDDR6 DRAM is symmetrical. Thus, the routing schemes of the two sets of GDDR6 DRAM on the same side surface in this embodiment can also be reused.

[0099] In summary, this embodiment only requires designing and verifying the wiring scheme for the four GDDR6 DRAM connections in the same group on one side of the surface. The rest can be implemented by reuse, which can greatly improve the design and verification efficiency, and thus improve the development efficiency of the GPU.

[0100] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. An FCBGA package structure, characterized in that, include: A substrate for mounting an MXG100 chip; two memory pin connection areas are symmetrically arranged on the substrate, and the two memory pin connection areas are respectively located near the two dynamic random access memory (DRAM) interface areas in the MXG100 chip. The DRAM interface areas are the PHY placement areas corresponding to the DRAM in the MXG100 chip; the axis of symmetry of the two memory pin connection areas coincides with the axis of symmetry of the two DRAM interface areas. The memory pin connection area includes four identical rectangular unit pin connection areas, of which three unit pin connection areas are arranged end to end along their own length direction to form a rectangular strip connection area, and the long side of the remaining unit pin connection area is arranged adjacent to the short side of the rectangular strip area to form an L-shaped pin connection area. The pin arrangement of each type in the pin connection area of ​​each unit is the same, and each pin in the pin connection area of ​​each unit is electrically connected to the corresponding pin in the PHY of the MXG100 chip.

2. The FCBGA packaging structure according to claim 1, characterized in that, The unit pin connection area includes data line connection pins, address line connection pins, and digital ground connection pins; The data line connection pins are located near the MXG100 chip placement area, and the address line connection pins are located near the edge of the substrate. Each of the data line connection pins has a corresponding digital ground connection pin arranged adjacent to each other on each side. Each of the address line connection pins shall have at least three corresponding digital ground connection pins arranged adjacent to each other.

3. The FCBGA packaging structure according to claim 1, characterized in that, The unit pin connection area includes data line connection pins, address line connection pins, and digital ground connection pins; The data line connection pins are located near the MXG100 chip placement area, and the address line connection pins are located near the edge of the substrate. Multiple data line connection pins belonging to the same group are arranged adjacently in a corresponding first preset data pin area; Multiple address line connection pins belonging to the same group are arranged adjacently in a corresponding second preset data pin area; A corresponding third preset data pin area is sandwiched between any two adjacent first preset data pin areas; A corresponding third preset data pin area is sandwiched between any two adjacent second preset data pin areas; The third preset data pin area is a linear pin area formed by arranging multiple digital ground connection pins adjacent to each other.

4. The FCBGA packaging structure according to claim 1, characterized in that, The dynamic random access memory is GDDR6 DRAM.

5. An FCBGA packaging structure according to claim 2 or 3, characterized in that, The substrate has at least two circuit trace layers on its inner side. The traces of the data line connection pins are located in the inner circuit trace layer. The traces of the data line connection pins and the digital ground connection pins are located in the same circuit trace layer.

6. The FCBGA packaging structure according to claim 1, characterized in that, The substrate is also provided with a chip power pin area and multiple other device pin areas; The chip power pin area is the pin area corresponding to the orthographic projection area below the mounting position of the MXG100 chip in the substrate; The pin areas of the other devices are respectively arranged above and below the pin connection area of ​​the chip power pin area.

7. An FCBGA packaging structure according to claim 5, characterized in that, Also includes: A PCB graphics card motherboard, wherein the substrate is electrically connected to the PCB graphics card motherboard; The PCB graphics card motherboard has 16 GDDR6 DRAMs, with 8 GDDR6 DRAMs on each of its two sides. Among them, the eight GDDR6 DRAMs on the same side surface of the PCB graphics card motherboard are symmetrically arranged in two groups; the axis of symmetry of the two groups of GDDR6 DRAMs is the same as the axis of symmetry of the two memory pin connection areas; Each GDDR6 DRAM in the same group has the same relative position to the corresponding rectangular cell pin connection area; the connection traces of each GDDR6 DRAM and the corresponding rectangular cell pin connection area are the same.

8. The FCBGA packaging structure according to claim 7, characterized in that, The PCB graphics card motherboard includes multiple circuit trace layers; The address line connection pins and the connection traces to the GDDR6 DRAM are located on the upper surface circuit trace layer of the PCB graphics card motherboard.

9. An FCBGA packaging structure according to claim 8, characterized in that, The data line connection pins and the connection traces to the GDDR6 DRAM are located in the inner circuit trace layer of the PCB graphics card motherboard.

10. An FCBGA packaging structure according to claim 6, characterized in that, The other device pin areas include the pin areas corresponding to the PCIe module, Display module, and SerDes module, respectively.

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