A silicon capacitor

Abstract

This invention relates to the field of silicon capacitor technology and is widely used in various radio frequency and optical communication products. The main technology is a silicon capacitor comprising: a through-silicon via (TSV) substrate, a dielectric layer, a second electrode layer, an insulating layer, a first electrode layer, through-hole leads, and upper and lower pads. The TSVs in the TSV substrate are cylindrical, prismatic, or dumbbell-shaped. The cylindrical and prismatic sidewalls are vertical, while the dumbbell-shaped sidewalls are inclined. Inverted truncated pyramids are formed by anisotropic etching of silicon on both sides. The TSV array forms a repeating structure, with the opening diameter of a single TSV ranging from 2μm to 20μm. This invention utilizes TSV technology, opening on both sides, overcoming the problems of poor uniformity in U-shaped deep trench etching and inconsistent hole depth in existing technologies, as well as the high stress and fragmentation during capacitor fabrication caused by U-shaped deep trenches opening on only one side.

Description

Technical Field

[0001] This invention relates to the field of capacitor technology, and more specifically, to a silicon capacitor. Background Technology

[0002] With the rapid development of communication technology, there are increasingly higher requirements for bandwidth, frequency and loss. Silicon capacitors have been widely used in various radio frequency and optical communication products.

[0003] Silicon capacitors utilize semiconductor technology, with a heavily doped silicon substrate as the lower electrode and silicon dioxide or silicon nitride commonly used as the dielectric. Heavily doped polycrystalline silicon serves as the upper electrode. To increase capacitance, the most common method is to etch a deep, narrow shape into the substrate, using a trench structure. Typically, the cross-section of the trench structure resembles a "U" shape. Furthermore, to increase capacitance, trenches are repeated at regular intervals on the silicon substrate in an array.

[0004] However, due to the poor uniformity of U-shaped deep groove etching in existing technologies, the depth of the holes cannot be guaranteed to be consistent, resulting in a large deviation in capacitance values. Furthermore, the fact that one side of the U-shaped deep groove is open causes high stress during the capacitor manufacturing process, leading to breakage. Summary of the Invention

[0005] This invention proposes a silicon capacitor to overcome the problems of poor uniformity in U-shaped deep trench etching, inconsistent hole depth, and high stress and fragmentation during capacitor fabrication caused by the opening on one side of the U-shaped deep trench in the prior art. This invention provides a silicon capacitor with a through-hole structure in the silicon trench, which avoids capacitance deviation caused by poor uniformity due to blind hole etching. At the same time, because it is open on both sides, it releases the stress generated during deep silicon etching.

[0006] The technical solution of the present invention is as follows: A silicon capacitor, comprising a first capacitor, wherein the first capacitor includes:

[0007] The first through-silicon via substrate is low-resistivity silicon with a resistivity of 0.001~0.01Ω·cm, a thickness of 50~300μm, and a crystal orientation of 100.

[0008] The first through-hole is provided with multiple through-holes arranged alternately in a parallel array on the first silicon through-hole substrate. The first through-hole is either cylindrical or prismatic, and the sidewalls of the cylindrical or prismatic holes are vertical. The opening diameter of a single through-hole is 2μm~20μm.

[0009] The first dielectric layer uniformly covers the surface of the first through-silicon via substrate and the entire area of ​​the first through-silicon via sidewall, with a thickness of 1 nm to 2000 nm.

[0010] The first upper electrode layer uniformly covers the surface of the first dielectric layer, including the surface of the first through-silicon via substrate and the sidewall of the first through-silicon via, thereby filling the interior of the first through-silicon via with a thickness of 10nm~2000nm, and together with the first dielectric layer, forms an upper electrode structure.

[0011] The first insulating layer uniformly covers the outer side of the first upper electrode layer on the lower surface of the first through-silicon via substrate;

[0012] The first through-hole lead is vertically led out from the bottom of the first through-silicon via substrate to form an electrical connection between the first lower electrode layer and the low-resistivity first through-silicon via substrate in the vertical direction.

[0013] The first lower electrode layer is located at the bottom of the first through-silicon via substrate and uniformly covers the surface of the first insulating layer. The thickness is 10nm~2000nm. Together with the first through-silicon via substrate, it forms the lower electrode, thus forming a complete capacitor structure with the upper electrode.

[0014] The first upper pad is located on the surface of the first upper electrode layer and has a thickness of 1000nm~10000nm;

[0015] The first lower pad is located on the surface of the first lower electrode layer and has a thickness of 1000nm~10000nm.

[0016] Preferably, the first dielectric layer is one or a combination of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, tungsten oxide, and indium oxide.

[0017] Preferably, the first upper electrode layer is one of heavily doped polycrystalline silicon, metallic gold, metallic aluminum, metallic copper, tantalum nitride, and titanium nitride.

[0018] Preferably, the first lower electrode layer is one of metal gold, metal aluminum, metal copper, tantalum nitride, and titanium nitride.

[0019] Preferably, the first upper pad and the first lower pad are one or more combinations of metals such as gold, aluminum, copper, titanium, nickel, and palladium.

[0020] A silicon capacitor includes a second capacitor, the second capacitor comprising:

[0021] The second through-silicon via substrate is made of low-resistivity silicon with a resistivity of 0.001~0.01Ω·cm, a thickness of 50~300μm, and a crystal orientation of 100.

[0022] The second via is provided with multiple vias arranged alternately in parallel array on the second silicon via substrate. The second via is dumbbell-shaped with symmetrical obtuse angle distribution on the sidewalls. An inverted truncated pyramid structure is formed on the via wall by anisotropic etching of silicon on both sides. The opening diameter of a single via is 2μm~20μm.

[0023] The second dielectric layer uniformly covers the surface of the second through-silicon via substrate and the entire area of ​​the second through-silicon via sidewall, with a thickness of 1 nm to 2000 nm.

[0024] The second upper electrode layer uniformly covers the surface of the second dielectric layer, including the surface of the second through-silicon via substrate and the sidewall of the second through-silicon via, thereby filling the interior of the second through-silicon via with a thickness of 10nm~2000nm, and together with the second dielectric layer, forms an upper electrode structure.

[0025] The second insulating layer uniformly covers the outer side of the second upper electrode layer on the lower surface of the second through-silicon via substrate;

[0026] The second via lead is vertically led out from the bottom of the second silicon via substrate to form an electrical connection between the second lower electrode layer and the low-resistivity second silicon via substrate in the vertical direction.

[0027] The second lower electrode layer is located at the bottom of the second through-silicon via substrate and uniformly covers the surface of the second insulating layer. The thickness is 10nm~2000nm. Together with the second through-silicon via substrate, it forms the lower electrode, thus forming a complete capacitor structure with the upper electrode.

[0028] The second upper pad is located on the surface of the second upper electrode layer and has a thickness of 1000nm~10000nm;

[0029] The second lower pad is located on the surface of the second lower electrode layer and has a thickness of 1000nm~10000nm.

[0030] Preferably, the second dielectric layer is one or a combination of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, tungsten oxide, indium oxide, etc.

[0031] Preferably, the second upper electrode layer is one of heavily doped polycrystalline silicon, metallic gold, metallic aluminum, metallic copper, tantalum nitride, and titanium nitride.

[0032] Preferably, the second lower electrode layer is one of metal gold, metal aluminum, metal copper, tantalum nitride, and titanium nitride.

[0033] Preferably, the second upper pad and the second lower pad are one or more combinations of metals such as gold, aluminum, copper, titanium, nickel, and palladium.

[0034] The beneficial effects of this invention are as follows:

[0035] This invention employs through-silicon via (TSV) technology, which opens on both sides, overcoming the problems of poor uniformity in etching U-shaped deep trenches and inconsistent hole depths in existing technologies, as well as the high stress and fragmentation caused by one side opening of the U-shaped deep trench during capacitor fabrication. Attached Figure Description

[0036] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0037] Figure 1 This is a schematic cross-sectional view of a silicon capacitor according to Embodiment 1 of the present invention.

[0038] Figure 2 This is a schematic cross-sectional view of a silicon capacitor according to Embodiment 2 of the present invention;

[0039] Figure 3 This refers to the capacitance value distribution of a capacitor as proposed in Embodiments 1 and 2 of the present invention, compared to that of a traditional silicon capacitor.

[0040] In the figure: 100, first capacitor; 101, first through-silicon via substrate; 102, first via; 103, first dielectric layer; 104, first upper electrode layer; 105, first insulating layer; 106, first via lead; 107, first lower electrode layer; 108, first upper pad; 109, first lower pad; 200, second capacitor; 201, second through-silicon via substrate; 202, second through-silicon via substrate; 202, second via; 203, second dielectric layer; 204, second upper electrode layer; 205, second insulating layer; 206, second via lead; 207, second lower electrode layer; 208, second upper pad; 209, second lower pad. Detailed Implementation

[0041] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0042] Example 1

[0043] Please see Figure 1 This embodiment proposes a silicon capacitor, including a first capacitor 100. The first capacitor 100 includes a first through-silicon via substrate 101, a first through-hole 102, a first dielectric layer 103, a first upper electrode layer 104, a first insulating layer 105, a first through-hole lead 106, a first lower electrode layer 107, a first upper pad 108, and a first lower pad 109. The first through-silicon via substrate 101 is low-resistivity silicon with a resistivity of 0.001~0.01Ω·cm, a thickness of 50~300μm, and a crystal orientation of 100.

[0044] Furthermore, the first through-hole 102 is provided with multiple through-holes arranged alternately in a parallel array on the first silicon through-hole substrate 101. The first through-hole 102 is either cylindrical or prismatic. The sidewalls of the cylindrical and prismatic shapes are both vertical, and the opening diameter of a single through-hole is 2μm~20μm.

[0045] Furthermore, the first dielectric layer 103 uniformly covers the surface of the first silicon via substrate 101 and the entire area of ​​the sidewall of the first via 102, with a thickness of 1nm~2000nm. The first dielectric layer 103 is one or a combination of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, tungsten oxide, indium oxide, etc. If a single layer of silicon oxide is used, it can be deposited by thermal oxidation process. Other materials are deposited by plasma enhanced chemical vapor deposition (PECVD) or atomic vapor deposition (ALD) processes.

[0046] Furthermore, the first upper electrode layer 104 uniformly covers the surface of the first dielectric layer 103 and also includes the surface of the first through-silicon via substrate 101 and the sidewall of the first through-hole 102, thereby filling the interior of the first through-hole 102 with a thickness of 10nm~2000nm, and forming an upper electrode structure with the first dielectric layer 103. The first upper electrode layer 104 is one of heavily doped polycrystalline silicon, metallic gold, metallic aluminum, metallic copper, tantalum nitride, and titanium nitride. If heavily doped polycrystalline silicon is used, in-situ doping low-pressure chemical vapor deposition (LPCVD) process can be used. If metal is used, a sidewall seed layer can be covered on the upper and lower surfaces of the through-silicon via substrate 101 and the sidewall of the through-hole with a thickness of 10nm~100nm by magnetron sputtering, and then the interior of the through-hole is filled by electroplating process.

[0047] Furthermore, the first insulating layer 105 uniformly covers the outer surface of the first upper electrode layer 104 on the lower surface of the first through-silicon via substrate 101. Its main purpose is to isolate the electrical connection between the first lower electrode layer 107 and the first upper electrode layer 104. It is produced using plasma-enhanced chemical vapor deposition (PECVD) or atomic vapor deposition (ALD) processes, with a thickness of 5nm to 2000nm.

[0048] Furthermore, the first via lead 106 is vertically led out from the bottom of the first through-silicon via substrate 101, serving as a vertical lead between the first lower electrode layer 107 and the low-resistivity first through-silicon via substrate 101 to form an electrical connection.

[0049] Furthermore, the first lower electrode layer 107 is located at the bottom of the first through-silicon via substrate 101, uniformly covering the surface of the first insulating layer 105. It is deposited using a magnetron sputtering process and has a thickness of 10nm~2000nm. Together with the first through-silicon via substrate 101, it forms the lower electrode, thus forming a complete capacitor structure with the upper electrode. The capacitance value depends on the thickness of the dielectric layer and the height and density of the via. If a higher capacitance value is required, the dielectric layer and electrode layer can be repeatedly deposited in the first via 102 to form multiple capacitors in parallel. The first lower electrode layer 107 is one of metals such as gold, aluminum, copper, tantalum nitride, and titanium nitride.

[0050] Furthermore, the first upper pad 108 is located on the surface of the first upper electrode layer 104 and is thickened by electroplating, with a thickness of 1000nm~10000nm. The first lower pad 109 is located on the surface of the first lower electrode layer 107 and has a thickness of 1000nm~10000nm. Both the first upper pad 108 and the first lower pad 109 are one or more combinations of metals such as gold, aluminum, copper, titanium, nickel, and palladium.

[0051] Example 2

[0052] Please see Figure 2 This embodiment proposes a silicon capacitor, including a second capacitor 200. The second capacitor 200 includes a second silicon via substrate 201, a second via 202, a second dielectric layer 203, a second upper electrode layer 204, a second insulating layer 205, a second via lead 206, a second lower electrode layer 207, a second upper pad 208, and a second lower pad 209. The second silicon via substrate 201 is low-resistivity silicon with a resistivity of 0.001~0.01Ω·cm, a thickness of 50~300μm, and a crystal orientation of 100. Multiple second vias 202 are arranged alternately in parallel array on the second silicon via substrate 201. Unlike embodiment one, the second vias 202 in this embodiment are dumbbell-shaped with symmetrical obtuse angle distribution on the sidewalls. An inverted truncated pyramid structure is formed on the hole wall by anisotropic etching of silicon on both sides. The opening diameter of a single via is 2μm~20μm. The rest of the structure is the same as in embodiment one.

[0053] The above embodiment provides a silicon capacitor in which the silicon trench is a through-hole structure, avoiding capacitance deviation caused by poor uniformity due to blind via etching. Please refer to [link to relevant documentation]. Figure 3 As shown in the table below, the capacitance uniformity of the through-silicon via structure within the wafer is less than 1.3%, while the capacitance uniformity of the blind via structure of the same depth within the wafer is approximately 15.5%. The statistical data clearly demonstrates the advantage of this invention in improving capacitance deviation.

[0054]

[0055] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A silicon capacitor, characterized in that, Includes a first capacitor (100), the first capacitor (100) comprising: The first through-silicon via substrate (101) is low-resistivity silicon with a resistivity of 0.001~0.01Ω·cm, a thickness of 50~300μm, and a crystal orientation of 100. The first through hole (102) is provided with multiple through holes arranged alternately in a parallel array on the first silicon through hole substrate (101). The first through hole (102) is either cylindrical or prismatic. The sidewalls of the cylindrical and prismatic shapes are vertical. The opening diameter of a single through hole is 2μm~20μm. The first dielectric layer (103) uniformly covers the surface of the first through-silicon via substrate (101) and the entire area of ​​the sidewall of the first through-hole (102), with a thickness of 1nm~2000nm; The first upper electrode layer (104) uniformly covers the surface of the first dielectric layer (103) and also includes the surface of the first through-silicon via substrate (101) and the sidewall of the first through-hole (102) hole wall, thereby filling the interior of the first through-hole (102) with a thickness of 10nm~2000nm, and forming an upper electrode structure with the first dielectric layer (103). The first insulating layer (105) uniformly covers the outer side of the first upper electrode layer (104) on the lower surface of the first through-silicon via substrate (101); The first through-hole lead (106) is vertically led out from the bottom of the first through-silicon via substrate (101) to form an electrical connection between the first lower electrode layer (107) and the low-resistivity first through-silicon via substrate (101) in the vertical direction. The first lower electrode layer (107) is located at the bottom of the first through-silicon via substrate (101), uniformly covers the surface of the first insulating layer (105), and has a thickness of 10nm~2000nm. Together with the first through-silicon via substrate (101), it forms the lower electrode, thereby forming a complete capacitor structure with the upper electrode. The first upper pad (108) is located on the surface of the first upper electrode layer (104) and has a thickness of 1000nm~10000nm; The first lower pad (109) is located on the surface of the first lower electrode layer (107) and has a thickness of 1000nm~10000nm.

2. A silicon capacitor according to claim 1, characterized in that, The first dielectric layer (103) is one or a combination of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, tungsten oxide, and indium oxide.

3. A silicon capacitor according to claim 1, characterized in that, The first upper electrode layer (104) is one of heavily doped polycrystalline silicon, metallic gold, metallic aluminum, metallic copper, tantalum nitride and titanium nitride.

4. A silicon capacitor according to claim 1, characterized in that, The first lower electrode layer (107) is one of gold, aluminum, copper, tantalum nitride and titanium nitride.

5. A silicon capacitor according to claim 1, characterized in that, The first upper pad (108) and the first lower pad (109) are both one or more combinations of metals such as gold, aluminum, copper, titanium, nickel, and palladium.

6. A silicon capacitor, characterized in that, Includes a second capacitor (200), the second capacitor (200) comprising: The second through-silicon via substrate (201) is low-resistivity silicon with a resistivity of 0.001~0.01Ω·cm, a thickness of 50~300μm, and a crystal orientation of 100. The second via (202) is provided with multiple vias arranged alternately in parallel array on the second silicon via substrate (201). The second via (202) is dumbbell-shaped with symmetrical obtuse angle distribution on the sidewalls. An inverted truncated pyramid structure is formed on the hole wall by anisotropic etching of silicon on both sides. The opening diameter of a single via is 2μm~20μm. The second dielectric layer (203) uniformly covers the surface of the second through-silicon via substrate (201) and the entire area of ​​the sidewall of the second through-silicon via substrate (202), with a thickness of 1nm~2000nm; The second upper electrode layer (204) uniformly covers the surface of the second dielectric layer (203), including the surface of the second through-silicon via substrate (201) and the sidewall of the second through-hole (202) hole wall, thereby filling the interior of the second through-hole (202) with a thickness of 10nm~2000nm, and forming an upper electrode structure with the second dielectric layer (203); The second insulating layer (205) uniformly covers the outer side of the second upper electrode layer (204) on the lower surface of the second through-silicon via substrate (201); The second via lead (206) is vertically led out from the bottom of the second silicon via substrate (201) to form an electrical connection between the second lower electrode layer (207) and the low-resistivity second silicon via substrate (201) in the vertical direction. The second lower electrode layer (207) is located at the bottom of the second through-silicon via substrate (201), uniformly covers the surface of the second insulating layer (205), and has a thickness of 10nm~2000nm. Together with the second through-silicon via substrate (201), it forms the lower electrode, thereby forming a complete capacitor structure with the upper electrode. The second upper pad (208) is located on the surface of the second upper electrode layer (204) and has a thickness of 1000nm~10000nm; The second lower pad (209) is located on the surface of the second lower electrode layer (207) and has a thickness of 1000nm~10000nm.

7. A silicon capacitor according to claim 6, characterized in that, The second dielectric layer (203) is one or a combination of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, tungsten oxide, and indium oxide.

8. A silicon capacitor according to claim 6, characterized in that, The second upper electrode layer (204) is one of heavily doped polycrystalline silicon, metallic gold, metallic aluminum, metallic copper, tantalum nitride and titanium nitride.

9. A silicon capacitor according to claim 6, characterized in that, The second lower electrode layer (207) is one of metal gold, metal aluminum, metal copper, tantalum nitride and titanium nitride.

10. A silicon capacitor according to claim 6, characterized in that, The second upper pad (208) and the second lower pad (209) are both one or more combinations of metals such as gold, aluminum, copper, titanium, nickel, and palladium.

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