Integrated circuit device and manufacturing method thereof

Abstract

Integrated circuit (IC) devices and methods of making the same are provided. An IC device includes a back-end-of-line (BEOL) region including first and second vias on first and second lower metal lines, respectively. The BEOL region includes a first upper metal line coupled to the first lower metal line through a first via, and a second upper metal line coupled to the second lower metal line through a second via. The first upper metal line and the first via each include a first metal. The second upper metal line and the second via each include a second metal different from the first metal. In addition, the second upper metal line is wider than the first upper metal line.

Description

Technical Field

[0001] The present disclosure relates generally to the field of integrated circuit (IC) devices, and more particularly to IC devices having metal lines in a back-end of line (BEOL) region thereof, and methods of manufacturing such IC devices. Background Art

[0002] The BEOL region of an IC device may include multiple vertical levels of metal lines (e.g., interconnect wires). An upper metal line in the BEOL region may be coupled to a lower metal line in the BEOL region through a metal via. For example, a single upper metal line may be coupled to two lower metal lines through corresponding metal vias. Summary of the invention

[0003] An IC device according to some embodiments of the present invention may include a BEOL region including a first lower metal line and a second lower metal line extending parallel to each other in a first direction. The BEOL region may include a first via and a second via on the first lower metal line and the second lower metal line, respectively. The BEOL region may include a first upper metal line and a second upper metal line extending in a second direction perpendicular to the first direction. The first upper metal line may be coupled to the first lower metal line through a first via. The second upper metal line may be coupled to the second lower metal line through a second via. The first upper metal line and the first via may each include a first metal. The second upper metal line and the second via may each include a second metal different from the first metal. In addition, the second upper metal line may be wider than the first upper metal line in the first direction.

[0004] An IC device according to some embodiments herein may include a BEOL region including a first lower metal line and a second lower metal line extending parallel to each other at a first vertical level. The BEOL region may include a ruthenium path at a second vertical level and on the first lower metal line. The BEOL region may include a copper path at a second vertical level and on the second lower metal line. In addition, the BEOL region may include a ruthenium upper metal line and a copper upper metal line, which are at a third vertical level and are collinear in a direction in which the first lower metal line and the second lower metal line are spaced apart from each other. The ruthenium upper metal line may be coupled to the first lower metal line via a ruthenium path. The copper upper metal line may be coupled to the second lower metal line via a copper path. The copper upper metal line may be wider than the ruthenium upper metal line in a direction in which the first lower metal line and the second lower metal line extend in parallel.

[0005] According to some embodiments of the present invention, a method for forming a BEOL region of an IC device may include forming a first metal layer. The method may include forming a first lower metal line, a second lower metal line, and a first via by performing a subtractive etch of the first metal layer. The method may include forming a second metal layer on the first lower metal line, the second lower metal line, and the first via. The method may include forming a first upper metal line by removing a portion of the second metal layer located on the second lower metal line, the first upper metal line being coupled to the first lower metal line through the first via. The first upper metal line and the first via may each include a first metal. In addition, the method may include forming a second upper metal line and a second via by a dual damascene process, the second upper metal line and the second via each including a second metal different from the first metal. The second upper metal line may be coupled to the second lower metal line through the second via. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A is a schematic block diagram of an IC device according to some embodiments herein.

[0007] Figure 1B yes Figure 1A An example plan view of the BEOL region of an IC device.

[0008] Figure 1C yes Figure 1B Example cross-sectional view of the BEOL region.

[0009] Figure 1D and Figure 1E yes Figure 1C Example top view of a pathway.

[0010] Figures 2A-2J is a cross-sectional diagram illustrating operations of forming a BEOL region according to some embodiments herein.

[0011] Figure 3 is corresponding to Figures 2A-2J Flowchart of the operations shown in . DETAILED DESCRIPTION

[0012] According to an embodiment of the present invention, an IC device is provided that includes a BEOL region having upper metal lines with different metals and widths. As a result, the interconnect resistance in the BEOL region can be reduced. For example, embodiments of the present invention can provide a narrow ruthenium (Ru) upper line and a wide copper (Cu) upper line.

[0013] The resistivity of the Cu metal wire can increase as its width decreases to less than 10 nanometers (nm), as discussed in Scaling Properties of Ru, Rh and Ir for Future Generation Metallization by Min-Sik Kim et al., IEEE Journal of the Electron Devices Society, Vol. 11, pp. 399-405 (July 2023), the entire contents of which are incorporated herein by reference. For sub-10nm upper metal wires (i.e., upper metal wires with a width less than 100 angstroms), metals such as Ru, rhodium (Rh) and iridium (Ir) have lower resistivities than Cu, and therefore can be advantageously used instead of Cu. The resistivity increase of Cu below 10nm is related to electron scattering at the surface and grain boundaries. However, for wide upper metal wires, Cu can have a resistivity lower than Ru. Therefore, the embodiments herein advantageously use both low-resistance narrow metal wires (e.g., narrow Ru wires) and low-resistance wide metal wires (e.g., wide Cu wires).

[0014] Example embodiments will be described in more detail with reference to the accompanying drawings.

[0015] Figure 1A 1 is a schematic block diagram of an IC device 100 according to some embodiments. The device 100 may be, for example, a semiconductor memory device for storing data and / or a semiconductor logic device for processing data. The device 100 includes a substrate (e.g., a semiconductor substrate) 110, a BEOL region 130 on the substrate 110, and a front-end process (FEOL) and / or middle-end process (MEOL) region 120 between the BEOL region 130 and the substrate 110 (in a vertical direction Z). As an example, the FEOL / MEOL region 120 may include devices such as transistors, capacitors, and / or resistors. In addition, the BEOL region 130 may include interconnect wires, vias, and dielectric structures.

[0016] Figure 1B yes Figure 1A FIG. 1 is an example plan view of the BEOL region 130. Figure 1B As shown, BEOL region 130 includes a plurality of BEOL elements, including various metal lines (eg, metal / interconnect wires) and metal vias. The metal lines include lower metal lines 132a-132e, narrow upper metal lines 138a-138c, and wide upper metal line 140. The metal vias include vias 134 and 136.

[0017] The lower metal lines 132a-132e extend parallel to each other in a horizontal direction Y, and are spaced apart from each other in another horizontal direction X that intersects the direction Y (e.g., is perpendicular to the direction Y). Narrow upper metal lines 138a-138c intersect the lower metal lines 132a and 132b, and wide upper metal line 140 intersects the lower metal lines 132d and 132e. Narrow upper metal lines 138a-138c extend parallel to each other in the direction X, are spaced apart from each other in the direction Y, and are at the same vertical level as the wide upper metal line 140 in the direction Z. For example, the narrow upper metal lines 138a-138c may have coplanar uppermost surfaces and / or coplanar lowermost surfaces.

[0018] Lower metal line 132c is between lower metal lines 132b and 132d. In some embodiments, lower metal line 132c does not cross any of narrow upper metal lines 138a-138c or wide upper metal line 140. In addition, there may be no other lower metal lines 132 (except lower metal line 132c) between lower metal lines 132b and 132d.

[0019] Narrow upper metal line 138b may be coupled to lower metal line 132b via via 134, and wide upper metal line 140 may be coupled to lower metal line 132d via via 136. Figure 1B , the locations of vias 134 and 136 are indicated above narrow upper metal line 138 b and wide upper metal line 140, respectively. However, it will be understood that vias 134 and 136 are below narrow upper metal line 138 b and wide upper metal line 140, respectively, and thus may not be visible on top of narrow upper metal line 138 b and wide upper metal line 140. Vias 134 and 136 may be at the same vertical level as each other in direction Z, which is below the vertical level of narrow upper metal lines 138 a-138 c and wide upper metal line 140. As an example, vias 134 and 136 may have coplanar uppermost surfaces and / or coplanar lowermost surfaces.

[0020] The via 136 is colinear with the via 134 in the direction X. Thus, an axis 142 extending in the direction X may pass through the via 134 and the via 136. In addition, the wide upper metal line 140 is spaced apart from the narrow upper metal line 138b along the axis 142. For example, the wide upper metal line 140 may be spaced apart from the narrow upper metal line 138b by a greater width in the direction X of the lower metal line 132c therebetween.

[0021] The wide upper metal line 140 is wider than the narrow upper metal line 138b in the direction Y. For example, the wide upper metal line 140 may be at least twice as wide as the narrow upper metal line 138b. In some embodiments, the width of the narrow upper metal line 138b may be less than 10nm, and the width of the wide upper metal line 140 may be greater than 10nm. In addition, the wide upper metal line 140 and the narrow upper metal line 138b include different metals. For example, the wide upper metal line 140 may include Cu, and the narrow upper metal line 138b may include Ru, Rh, or Ir.

[0022] According to some embodiments, the pitch of narrow upper metal lines 138a-138c (in the Y direction) can be twice the width of each of the narrow upper metal lines 138a-138c. Therefore, narrow upper metal lines 138a and 138b can be spaced apart from each other by a distance equal to the width of each of the narrow upper metal lines 138a-138c. Similarly, narrow upper metal lines 138b and 138c can be spaced apart from each other by a distance equal to the width of each of the narrow upper metal lines 138a-138c. In some embodiments, the distance between two adjacent narrow upper metal lines of narrow upper metal lines 138a-138c can be less than 10nm, and each of the narrow upper metal lines 138a-138c can have a width less than 10nm. Therefore, the pitch of narrow upper metal lines 138a-138c can be less than 20nm.

[0023] Figure 1C yes Figure 1B The BEOL region 130 is along the axis 142 ( Figure 1B ). Figure 1C As shown, narrow upper metal line 138b is coupled to lower metal line 132b through via 134, and wide upper metal line 140 is coupled to lower metal line 132d through via 136. In some embodiments, lower metal lines 132a-132e may include the same metal (e.g., Ru, Rh, or Ir) as via 134 and narrow upper metal line 138b. In addition, wide upper metal line 140 may include the same metal (e.g., Cu) as via 136. The metal of wide upper metal line 140 and via 136 may be different from the metal of narrow upper metal line 138b and via 134. Therefore, lower metal lines 132a-132e may include a metal different from the metal of via 136 and wide upper metal line 140.

[0024] Figure 1CThree vertical levels of BEOL region 130 are shown in direction Z. Lower metal lines 132a-132e are each at a low (e.g., lowest) level, vias 134 and 136 are each at an intermediate level, and narrow upper metal line 138b and wide upper metal line 140 are each at a high (e.g., highest) level. For example, the uppermost surface of narrow upper metal line 138b may be coplanar with the uppermost surface of wide upper metal line 140, and / or the lowermost surface of narrow upper metal line 138b may be coplanar with the lowermost surface of wide upper metal line 140.

[0025] In some embodiments, via 134 may have a shape different from that of via 136. For example, via 134 may have a constant width in direction X from the top of via 134 to the bottom of via 134. On the other hand, via 136 may have a tapered width in direction X that becomes narrower as it approaches lower metal line 132 d in direction Z.

[0026] To simplify the explanation, Figure 1C Only the metal elements of the BEOL region 130 are shown in FIG. However, it should be understood that the BEOL region 130 may include one or more insulating (e.g., dielectric) layers having metal elements therein. As an example, the insulating layer may electrically isolate the narrow upper metal line 138 b from the wide upper metal line 140 .

[0027] Figure 1D and Figure 1E yes Figure 1C 134 and 136. Figure 1D The location of via 136 is indicated on the wide upper metal line 140 in FIG. Figure 1E 14. The location of via 134 is indicated on narrow upper metal line 138b in FIG. However, it will be understood that vias 134 and 136 are below narrow upper metal line 138b and wide upper metal line 140, respectively, and thus may not be visible on top of narrow upper metal line 138b and wide upper metal line 140.

[0028] like Figure 1D As shown, the via 136 may have a cylindrical shape whose diameter in the direction Y is narrower than the width of the wide upper metal line 140 in the direction Y. Figure 1E As shown, the via 134 may have a rectangular shape whose width in the direction Y is equal to the width of the narrow upper metal line 138 b in the direction Y.

[0029] To simplify the explanation, Figure 1E A circular outline 144 is depicted superimposed on passage 134 to indicate the size of passage 136 relative to the size of passage 134. Thus, Figure 1EThe widest portion (e.g., diameter) of via 136 is shown to be wider than the widest portion of via 134 in direction Y. For example, vias 134 and 136 may each be formed by a self-aligned via process, and thus may each have a via size corresponding to the width of the upper metal line thereon in direction Y. Thus, via 134 may be narrower than via 136 because narrow upper metal line 138 b is narrower than wide upper metal line 140.

[0030] Figures 2A-2J FIG. 1 is a diagram showing the formation of a BEOL region 130 ( Figure 1A )'s operation. Figure 3 is corresponding to Figures 2A-2J Flowchart of the operations shown in .

[0031] like Figure 2A and Figure 3 As shown, a metal adhesion layer 202 may be formed, and a first metal layer 204 may be formed on the adhesion layer 202 (block 310). For example, the metal layer 204 may include Ru and may be formed by a blanket Ru fill. The adhesion layer 202 may include an improved metal layer 204 to the underlying insulating layer (e.g., oxide layer) of the BEOL region 130 or the FEOL / MEOL region 120 ( Figure 1A As an example, the adhesion layer 202 may include aluminum (Al) or chromium (Cr).

[0032] like Figure 2B and Figure 3 As shown, the metal layer 204 ( Figure 2A ) performs a subtractive etch (block 312) to form lower metal lines 132b-132d and via 134. As an example, a subtractive Ru top via patterning may be performed. To simplify the description, Figure 2B The lower metal lines 132a and 132e are omitted from the view in FIG. Figure 1B ). However, it should be understood that the lower metal lines 132 a - 132 e may all be formed by subtractive etching of the metal layer 204 .

[0033] like Figure 2C and Figure 3 As shown, an insulating liner 206 may be conformally formed on lower metal line 132 and via 134 (block 314). For example, liner 206 may be formed on the sidewalls and uppermost surface of via 134, the sidewalls of lower metal line 132b, and the sidewalls and uppermost surface of each of lower metal lines 132c and 132d. In some embodiments, liner 206 may include nitride and may be formed by conformal nitride deposition.

[0034] like Figure 2D and Figure 3 As shown, after forming the liner 206, a first dielectric layer 208 may be formed on the lower metal line 132 and the via 134 (block 316). For example, the dielectric layer 208 may be formed between the sidewalls of the lower metal line 132 and on the uppermost surface of the via 134 and the lower metal line 132. In some embodiments, the dielectric layer 208 may be formed by performing a low-k material fill on the lower metal line 132 and the via 134.

[0035] As used herein, the term "low-k" refers to a material having a dielectric constant smaller than that of silicon dioxide. Low-k materials may include, for example, fluorine-doped silicon dioxide, organosilicate glass, carbon-doped oxides, porous silicon dioxide, porous organosilicate glass, spin-on organic polymer dielectrics, or spin-on silicon-based polymer dielectrics.

[0036] like Figure 2E and Figure 3 As shown, a portion of dielectric layer 208 may be removed to expose an uppermost surface of via 134 (block 318). For example, dielectric layer 208 may be planarized (such as by chemical mechanical planarization (CMP)) to reveal an uppermost surface of via 134. After planarization, an uppermost surface of dielectric layer 208 on lower metal lines 132 c and 132 d may be coplanar with an uppermost surface of via 134 or adjacent to the level of an uppermost surface of via 134.

[0037] like Figure 2F and Figure 3 As shown, a second metal layer 214 can be formed on the exposed uppermost surface of the via 134 and on the planarization dielectric layer 208 (block 320). The metal layer 214 can include the same metal as the via 134 and / or the lower metal line 132. For example, the metal layer 214 can include Ru and can be formed on the exposed uppermost surface of the via 134 and on the planarization dielectric layer 208 by Ru deposition. In some embodiments, before forming the metal layer 214, a metal adhesion layer 212 can be formed on the exposed uppermost surface of the via 134 and on the planarization dielectric layer 208. The adhesion layer 212 can include a metal (e.g., Al or Cr) that improves adhesion of the metal layer 214 to the dielectric layer 208.

[0038] like Figure 2G and Figure 3 As shown, the metal layer 214 ( Figure 2F) may be patterned (block 322) to remove portions of metal layer 214 that overlap (in direction Z) with lower metal lines 132c-132e. After patterning (e.g., etching) metal layer 214, it may overlap lower metal lines 132a and 132b without overlapping lower metal lines 132c-132e. In addition, portions of adhesion layer 212 that overlap lower metal lines 132c-132e may also be removed. After patterning metal layer 214, the remaining portions of metal layer 214 serve as narrow upper metal lines 138b. In some embodiments, adhesion layer 212 is interposed between via 134 and narrow upper metal line 138b (in direction Z). As an example, adhesion layer 212 may contact the uppermost surface of via 134 and the lowermost surface of narrow upper metal line 138b.

[0039] like Figure 2H and Figure 3 As shown, a second dielectric layer 216 may be formed on the uppermost surface of the first dielectric layer 208 and on the exposed sidewalls of the narrow upper metal line 138b (block 324). For example, the dielectric layer 216 may be formed by intermetallic dielectric filling followed by planarization. In some embodiments, the dielectric layer 216 may include an oxide, and the planarization may be an oxide CMP.

[0040] According to some embodiments, dielectric layer 216 may include the same insulating material as dielectric layer 208. In other embodiments, dielectric layer 216 may include an insulating material different from the insulating material of dielectric layer 208. As an example, dielectric layer 216 may include silicon dioxide, and dielectric layer 208 may include an insulating material having a smaller dielectric constant than silicon dioxide.

[0041] like Fig.2I and Figure 3 As shown, the uppermost surface 222 of the lower metal line 132d can be exposed by removing a portion of the dielectric layer 216 and a portion of the dielectric layer 208 (block 326), thereby providing an opening 218 extending through the dielectric layers 208 and 216. The upper portion of the opening 218 (the portion in the dielectric layer 216) can be wider (in directions Y and X) than the lower portion thereof (the portion in the dielectric layer 208) because the upper portion is where the wide upper metal line 140 ( Figure 1C ) and the lower part is where the passage 136 ( Figure 1C ). Thus, the removal of the portion of dielectric layer 216 and the portion of dielectric layer 208 may include etching / patterning dielectric layer 216 and dielectric layer 208 in the shape of wide upper metal line 140 and the shape of via 136, respectively.

[0042] like Figure 2J and Figure 3As shown, the wide upper metal line 140 and the via 136 can be formed by a dual damascene process, wherein the narrow lower portion ( Fig.2I ) and the wide upper portion of the opening 218 (block 328). For example, the metal layer 226 may include Cu and may be formed by Cu filling followed by Cu CMP.

[0043] In some embodiments, the dual damascene process may include conformally forming a barrier metal 224 in the opening 218 and then forming a metal layer 226 on the barrier metal 224. Thus, the barrier metal 224 may contact the uppermost surface 222 ( Fig.2I ), the lowermost surface of via 136, and the sidewalls of via 136 and wide upper metal line 140. Barrier metal 224 can prevent metal (e.g., Cu) from diffusing from via 136 and wide upper metal line 140 into adjacent materials. As an example, barrier metal 224 can include Cr, nickel (Ni), nickel-chromium alloy, tantalum (Ta), hafnium (Hf), niobium (Nb), zirconium (Zr), vanadium (V), or tungsten (W). In contrast, there can be no barrier metal (neither barrier metal 224 nor any other barrier metal) between via 134 and lower metal line 132 b because via 134 can include a non-Cu metal that is less likely to diffuse than Cu. In addition, the dual damascene process can include forming a barrier metal such as with respect to Fig.2I Opening 218 is depicted.

[0044] According to the embodiments of the present invention, the IC device 100 ( Figure 1A ) can provide several advantages. These advantages include combining the benefits of two different schemes for forming metal vias in a single via layer. The first scheme is a top via scheme (e.g., subtractive Ru top via patterning), and the second scheme is a damascene via scheme (e.g., for Cu trench vias). Embodiments herein can combine these two schemes by forming a first via (i) by a subtractive (e.g., metal etching) process and (ii) by a damascene process in a single via layer. The combination of these two schemes may be referred to herein as a "dual via scheme."

[0045] The two approaches combined can be used with different metals to benefit from the properties of those metals that can vary with metal line width. For example, due to electron scattering, for narrow upper metal line 138b ( Figure 1B ), Ru can benefit from lower resistance than Cu, and for the wide upper metal line 140 ( Figure 1B ), Cu can benefit from lower resistance than Ru. Therefore, embodiments herein can advantageously reduce the BEOL area 130 ( Figure 1A ) in the interconnect wire. In addition, Cu can be used for both the wide upper metal line 140 and the (wide) via 136 connected thereto, and Ru can be used for both the narrow upper metal line 138b and the (narrow) via 134 connected thereto.

[0046] Compared to the embodiments herein, conventional BEOL technology may not perform both the subtractive metal process and the damascene process at the same upper level for the upper metal line (and / or at the same intermediate level for the via) to reduce resistance. Furthermore, conventional BEOL technology may lack the two different metals at the same level and does not realize the low resistivity benefit of using Ru in narrow areas and Cu in wide areas.

[0047] The scheme using subtractive Ru is a promising next generation device candidate for achieving the challenging narrow pitch of some BEOL interconnect wires. Another challenge in the BEOL region 130 is to achieve low resistance upper metal lines and vias. For the wide pitch area of ​​the BEOL region 130, the resistance of Ru can be relatively high. However, embodiments herein can reduce the overall chip resistance and improve chip performance by using subtractive metal processes and damascene processes at the same level with different metals (e.g., Ru and Cu) at different metal line widths, respectively.

[0048] Example embodiments are described herein with reference to the accompanying drawings. Many different forms and embodiments are possible without departing from the teachings of the present disclosure, and therefore the present disclosure should not be construed as being limited to the example embodiments set forth herein. On the contrary, these example embodiments are provided to make the present disclosure thorough and complete, and to convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals always refer to the same elements.

[0049] Example embodiments are described herein with reference to cross-sectional illustrations that are schematic representations of idealized embodiments and intermediate structures of example embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are anticipated. Thus, the embodiments herein should not be construed as limited to the particular shapes illustrated herein but are to include deviations in shapes that may result, for example, from manufacturing.

[0050] It should also be noted that in some alternative implementations, the function / action indicated in the flowchart frame of this paper may not occur in the order indicated in the flowchart. For example, two frames shown in succession can actually be performed substantially simultaneously, or frames can sometimes be performed in reverse order, depending on the function / action involved. In addition, the function of a given frame of a flowchart and / or block diagram can be divided into multiple frames and / or flowcharts, and / or the function of two or more frames of a flowchart and / or block diagram can be combined at least in part. Finally, without departing from the scope of the present invention, other frames can be added / inserted between the frames shown, and / or frames / operations can be omitted.

[0051] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0052] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "one", "an" and "the" are intended to also include plural forms, unless the context clearly states otherwise. It will be further understood that when used in this specification, the terms "include", "includes ... ", "includes" and / or "includes ... " specify the presence of the features, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, steps, operations, elements, parts and / or their groups.

[0053] It should be understood that when an element is referred to as being "coupled," "connected," or "responsive to" another element or "on another element," it may be directly coupled, connected, or responsive to another element or on another element, or there may be intermediate elements. In contrast, when an element is referred to as being "directly coupled," "directly connected," or "directly responsive to" another element or "directly on" another element, there are no intermediate elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In addition, the symbol " / " (for example, when used in the term "source / drain") will be understood to be equivalent to the term "and / or."

[0054] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teaching of this embodiment, the first element may be referred to as the second element.

[0055] For ease of description, spatially relative terms, such as "below", "below", "lower", "above", "upper", etc., may be used herein to describe the relationship between one element or feature as shown in the figure and another one or more elements or features. It should be understood that in addition to the orientation shown in the figure, the spatially relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the accompanying drawings is turned over, the elements described as "below" or "below" other elements or features will be oriented as "above" other elements or features. Therefore, the term "below" can cover both above and below orientations. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein can be interpreted accordingly.

[0056] Many different embodiments have been disclosed herein in conjunction with the above description and accompanying drawings. It should be understood that literally describing and illustrating every combination and sub-combination of these embodiments would be overly repetitive and confusing. Therefore, this specification (including the accompanying drawings) should be interpreted as constituting a complete written description of all combinations and sub-combinations of the embodiments described herein and the manner and process of making and using them, and should support claims to any such combination or sub-combination.

[0057] The subject matter disclosed above is considered to be illustrative and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the scope of the invention. Therefore, to the maximum extent allowed by law, the scope is to be determined by the broadest permissible interpretation of the appended claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

[0058] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 598,597, filed on November 14, 2023, entitled “Integrated Circuit Device Including Dual Interconnect Scheme and Method for Forming Same,” the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An integrated circuit (IC) device comprising a back-end-of-line (BEOL) region, The back-end process area includes: a first lower metal line and a second lower metal line extending parallel to each other in a first direction; a first via and a second via, on the first lower metal line and the second lower metal line, respectively; as well as A first upper metal line and a second upper metal line extending in a second direction perpendicular to the first direction, wherein the first upper metal line is coupled to the first lower metal line through the first via, wherein the second upper metal line is coupled to the second lower metal line through the second via, wherein the first upper metal line and the first via each include a first metal, wherein the second upper metal line and the second via each include a second metal different from the first metal, and The second upper metal line is wider than the first upper metal line in the first direction.

2. The integrated circuit device according to claim 1, wherein the first metal comprises ruthenium, and The second metal comprises copper. 3 . The integrated circuit device of claim 1 , wherein the first via and the second via are collinear in the second direction. 4 . The integrated circuit device of claim 1 , wherein a widest portion of the second via is wider than a widest portion of the first via in the first direction.

5. The integrated circuit device according to claim 1, wherein the width of the second via in the second direction tapers toward the second lower metal line, wherein the second via is narrower than the second upper metal line in the first direction, wherein the first passage has a constant width in the second direction, and The first via has the same width as the first upper metal line in the first direction. 6 . The integrated circuit device of claim 1 , wherein the second upper metal line is at least twice as wide as the first upper metal line in the first direction.

7. The integrated circuit device according to claim 1, wherein the back-end process area further includes a third lower metal line extending in parallel with the first lower metal line and the second lower metal line in the first direction, wherein the third lower metal line is between the first lower metal line and the second lower metal line, and in, Except for the third lower metal line, there are no other lower metal lines between the first lower metal line and the second lower metal line.

8. The integrated circuit device of claim 1, wherein the first upper metal line is at the same vertical level as the second upper metal line.

9. The integrated circuit device of claim 1, wherein the first via is at the same vertical level as the second via.

10. The integrated circuit device of claim 1 , wherein the back-end process region further comprises a third upper metal line and a fourth upper metal line, the third upper metal line and the fourth upper metal line extending in parallel with the first upper metal line in the second direction and being at the same vertical level as the first upper metal line. 11 . The integrated circuit device of claim 1 , wherein the first lower metal line and the second lower metal line each include a first metal.

12. The integrated circuit device according to claim 1, wherein the back-end process region further includes a barrier metal between the second via and the second lower metal line, and There is no barrier metal between the first via and the first lower metal line. 13 . The integrated circuit device of claim 1 , wherein the first upper metal line is spaced apart from the second upper metal line in the second direction.

14. An integrated circuit (IC) device comprising a back-end-of-line (BEOL) region, The back-end process area includes: a first lower metal line and a second lower metal line extending parallel to each other at a first vertical level; a ruthenium via at a second vertical level and on said first lower metal line; a copper via at the second vertical level and on the second lower metal line; as well as a ruthenium upper metal line and a copper upper metal line collinear at a third vertical level and in a direction in which the first lower metal line and the second lower metal line are spaced apart from each other; wherein the ruthenium upper metal line is coupled to the first lower metal line through the ruthenium via, wherein the copper upper metal line is coupled to the second lower metal line through the copper via, and The copper upper metal line is wider than the ruthenium upper metal line in a direction in which the first lower metal line and the second lower metal line extend in parallel.

15. The integrated circuit device of claim 14, wherein the first lower metal line and the second lower metal line comprise respective ruthenium lower metal lines.

16. A method of forming an integrated circuit device, the integrated circuit device including a back end of line (BEOL) region, the method comprising: forming a first metal layer; forming a first lower metal line, a second lower metal line, and a first via by performing a subtractive etch of the first metal layer; forming a second metal layer on the first lower metal line, the second lower metal line, and the first via; forming a first upper metal line by removing a portion of the second metal layer located on the second lower metal line, the first upper metal line being coupled to the first lower metal line through the first via, wherein the first upper metal line and the first via each include a first metal; as well as forming a second upper metal line and a second via by a dual damascene process, the second upper metal line and the second via each including a second metal different from the first metal, The second upper metal line is coupled to the second lower metal line through the second via.

17. The method according to claim 16, wherein the first metal comprises ruthenium, and The second metal comprises copper. 18 . The method of claim 16 , wherein the first lower metal line and the second lower metal line each comprise the first metal.

19. The method of claim 16, wherein the second upper metal line and the second via are formed after forming the first upper metal line.

20. The method of claim 19, further comprising forming an insulating material on an uppermost surface of the second lower metal line and on side surfaces of the first upper metal line, The dual damascene process comprises: removing a portion of the insulating material to expose the uppermost surface of the second lower metal line; forming a barrier metal on the exposed uppermost surface of the second lower metal line; as well as The second upper metal line and the second via are formed on the barrier metal.

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