Gate drive circuit with multi-segment current drive

Abstract

The invention discloses a gate drive circuit with multi-segment current drive. The self-bias current source unit is used for generating reference current; the current mirror unit is connected with the self-bias current source unit and is used for copying the reference current; the plurality of current generation units are connected with the current mirror unit and are used for generating multiple sections of different gate driving currents according to the reference current; wherein the grid driving circuit realizes segmented control on the grid voltage of the power tube by adjusting the magnitude of the multiple sections of grid driving current, so that the conduction and cut-off processes of the power tube are optimized, the electromagnetic interference is reduced, and the conversion efficiency is improved. The grid driving circuit driven by multiple sections of current is used for controlling the voltage and current conversion rate of a power tube switch so as to effectively suppress EMI, meanwhile, compared with a traditional grid driving circuit, the power tube is driven by large current after the grid voltage of the power tube is larger than the voltage of a Miller platform, the conduction loss is further reduced, and the reliability of the power tube is improved. And the efficiency of the DC-DC converter is improved.

Description

Technical Field

[0001] The invention relates to a gate driving circuit, in particular to a gate driving circuit with multi-segment current driving. Background Art

[0002] DC-DC converter, or direct current-to-direct current converter, is an important circuit device for power conversion. It is widely used in various electronic devices to convert DC power into DC power of different voltage levels. In the design of DC-DC converter, the gate drive circuit plays a vital role. It is responsible for controlling the conduction and cutoff of power semiconductor switches (such as lateral double diffused metal oxide semiconductor field effect transistor LDMOS, gallium nitride high electron mobility transistor GaN HEMT, etc.), thereby achieving efficient conversion of electrical energy.

[0003] like Figure 1 The figure shows the power tube turn-on process and the gate-source voltage V GS , gate voltage I G , source-drain current I D , source-drain voltage V DS Change process. At time A, the drive passes through R G C GS Charging, voltage V GS Rising exponentially; at time B V GS When the threshold voltage of the power tube is reached, the power tube enters the linear region until it reaches saturation. During this period, the source and drain stages still bear almost the entire voltage V DD , C moment I D Reach saturation and maintain a stable value, the power tube works in the saturation area, V GS Enter Miller Terrace, V GS Maintain the Miller platform voltage V MT , voltage V DS Start to decline, during this period C GS No longer consumes charge, V DD Start giving C GD Provides discharge current; voltage V at time D DS drops to 0, V DD Continue to give C GS Charge until V GS =V DD , the power tube completes the conduction process.

[0004] However, as the switching frequency continues to increase, the dI / dt caused by time B and the dV SW / dt continues to increase, which will cause serious electromagnetic interference (EMI) to the DC-DC converter.

[0005] Taking the Buck converter as an example, in order to reduce EMI, the traditional gate driver usually adds a gate resistor (such as Figure 2 Medium R GH , R GL As shown), it is used to reduce the gate charging current. Although this method can reduce dVsw / dt and dI MH / dt can improve EMI, but after the gate voltage of the power tube is greater than the Miller platform voltage, the gate is still charged with a smaller charging current, which will increase the conduction loss of the power tube and reduce the efficiency of the converter. Summary of the invention

[0006] The present invention aims at addressing the deficiencies of the prior art and provides a gate drive circuit with multi-stage current drive.

[0007] The present invention provides a gate drive circuit with multi-stage current drive, comprising:

[0008] A self-biased current source unit for generating a reference current;

[0009] a current mirror unit, connected to the self-biased current source unit, and used to replicate a reference current;

[0010] A plurality of current generating units, connected to the current mirror unit, and configured to generate a plurality of different gate driving currents according to the reference current;

[0011] The gate drive circuit realizes segmented control of the gate voltage of the power tube by adjusting the magnitude of the multiple segments of gate drive current, so as to optimize the conduction and cutoff process of the power tube, reduce electromagnetic interference and improve conversion efficiency.

[0012] The present invention also provides a control method for a gate drive circuit with multi-segment current drive, comprising the following steps:

[0013] generating a reference current by a self-biased current source unit;

[0014] Using a current mirror unit to copy the reference current to a plurality of current generating units;

[0015] When the gate voltage of the power tube is less than the Miller platform voltage, the gate of the power tube is charged with a first gate driving current through the first current generating unit;

[0016] When the gate voltage of the power tube reaches the Miller platform voltage, the gate of the power tube is charged with a second gate driving current through the second current generating unit;

[0017] When the gate voltage of the power tube exceeds the Miller platform voltage, the gate of the power tube is charged with a third gate driving current through the third current generating unit;

[0018] By adjusting the magnitudes of the first gate drive current, the second gate drive current and the third gate drive current, segmented control of the gate voltage of the power tube is achieved to optimize the on and off process of the power tube, reduce electromagnetic interference and improve conversion efficiency.

[0019] Beneficial effects of the present invention: The present invention adopts a multi-stage current-driven gate drive circuit to control the voltage and current conversion rate of the power tube switch to effectively suppress EMI. At the same time, compared with the traditional gate drive circuit, the power tube is driven by a large current after the power tube gate voltage is greater than the Miller platform voltage, which can further reduce the conduction loss and improve the efficiency of the DC-DC converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 : Power tube conduction process and current and voltage changes;

[0021] Figure 2 :Traditional gate drive circuit;

[0022] Figure 3 : Buck converter system block diagram;

[0023] Figure 4 : Gate drive circuit with multi-stage current drive;

[0024] Figure 5 : Schematic diagram of MH gate charging current. DETAILED DESCRIPTION

[0025] The technical solution in this application is described below in conjunction with the accompanying drawings.

[0026] like Figure 3 The system block diagram of the entire Buck converter, where the gate drive voltage range of the power tube MH is V BST ~V SW , the gate drive voltage range of the lower power tube ML is V DD ~ GND, the main structure of the gate drive circuit is the same. This embodiment takes the gate drive circuit of the power tube on the Buck converter as an example. Figure 4 The schematic diagram of the gate drive circuit of the upper power tube multi-stage current drive is shown, which is divided into five units: A, B, C, D, and E. (In this application, M N Represents NMOS, M P Represents PMOS, M DN Represents NLDMOS, M DP stands for PLDMOS).

[0027] The dotted line A unit is a self-biased current source, which generates a current source for the gate drive circuit.

[0028] M P5 The source is connected to VDD, and the gate and drain are shorted to M N11 The gate and drain of M N12 The gate and drain are shorted to M N11 The gate and drain of M N11 The source is connected to M P6 The drain, M N13 The drain and M N14 The gate of P6 The source is connected to VDD and the gate is connected to M P7 The gate and drain of M N14 The drain of N13 The source is connected to GND, and the gate is connected to M N14 The source, R3, and M DN1 The gate of P7 The source of R3 is connected to VDD; the other end of R3 is connected to GND.

[0029] The dotted line B unit is the current mirror part, which copies the current generated by the self-biased current source to the C unit and the D unit. The connection relationship is as follows:

[0030] M DP1 The source is connected to VBST, and the gate and drain are connected to M DN1 The drain and M P8 The gate of DN1 The source of M is connected to GND; P8 The source is connected to V BST , drain connected to M N15 The gate and drain, M N2 The gate, M N4 The gate, M N8 The gate of N15 The source is connected to V SW .

[0031] The dashed line C unit is I G1 The generated circuit has the following connection relationship:

[0032] M P1 The gate is connected to V DRV , source connected to V BST , drain connected to M N1 The drain, R1, and M P5 The gate of N1 The gate is connected to V DRV , source connected to M N2 The drain, M N3 The drain of N2 The source is connected to V SW ;M N3 The gate is connected to MN5 The source of the inverter INV1, the input of M N6 The drain of the N4 The drain of N4 The source is connected to V SW ; The other end of R1 is connected to V BST ;M P2 The source is connected to V BST , drain connected to M N6 's gate and the gate of the power tube MH.

[0033] The dotted line D unit is the IG2 generation circuit, and its connection relationship is as follows:

[0034] M N5 The gate and drain are connected to V BST ;M N6 The source is connected to V SW ; The output of inverter INV1 is connected to M P3 The gate and M N7 The gate of P3 The source is connected to V BST , drain connected to M N7 Drain, R2, M P4 The gate of N7 The source is connected to M N8 The drain of N8 The source is connected to V SW ; The other end of R2 is connected to V BST ;M P4 The source is connected to V BST , drain connected to M N10 's gate and the gate of the power tube MH.

[0035] The dashed line E unit is I G3 The generated circuit has the following connection relationship:

[0036] M N9 The gate and drain are connected to V BST , the source is connected to the input of inverter INV2, M N10 The drain of N10 The source is connected to V SW ; The output end of the inverter INV2 is connected to the input end of the buffer Buffer; The output end of the buffer Buffer is connected to the gate of the power tube MH (Buffer is composed of an inverter chain).

[0037] Based on the above circuit structure, the control method of the gate drive circuit with multi-stage current drive of the present application: In the dotted line A unit, in order to get rid of the degenerate point existing in the circuit when starting, it is necessary to add a startup circuit to the self-biased current source. P5 ,MN11 ,M N12 For the startup circuit part, when the circuit starts, V GSN11 >V thN11 , at this time M N11 conduction, giving the left branch (M P6 , M N13 ) introduces current to break the zero current balance point. When the current source works normally, M N11 In the off state.

[0038] During the conduction period of the power tube MH (V DRV is in high level state), the X node is in high level state, and M N1 , M N2 , M N3 , M N4 On, M P1 The currents I1 and I2 generated by the self-biased reference current source flow through resistor R1, and the voltage across R1 is (I1+I2)*R1, while M P2 The gate-source voltage V GSP2 Equal to the voltage across the resistor R1, define gm1 as M P2 The transconductance of the tube, V thP2 M P2 The threshold voltage of the tube, then M P2 The current of the tube is That is, the gate drive circuit starts with The current of large and small magnitude charges the gate of the power tube MH.

[0039] When the gate voltage of the power tube MH reaches the Miller platform voltage V MT When adjusting M N6 The width-to-length ratio of the tube, let M N6 The threshold voltage of the tube is V thN6 Slightly smaller than V MT , that is, at this time M N6 The tube is turned on, pulling the potential of the X node down to V SW , and then M N3 The tube is turned off, so M P2 The current of the tube is The output of inverter INV1 is high level. P3 Shutdown, M N7 、M N8 I3 generated by the self-biased reference current source flows through R2, that is, the voltage across R2 is I3*R2, and M P4 The gate-source voltage V GSP4 Equal to the voltage across R2, define gm2 as M P4 The transconductance of the tube, V thP4 M P4 The threshold voltage of the tube, then MP4 The current of the tube is That is, the gate drive circuit is The current of large and small magnitude charges the gate of the power tube MH.

[0040] When the gate voltage of the power tube MH exceeds the Miller platform voltage V MT When adjusting M N10 The width-to-length ratio of the tube, let M N10 The threshold voltage of the tube is V thN10 Slightly larger than V MT , that is, at this time M N10 The tube is turned on, the input end of the inverter INV2 is at a low level, and the output end is at a high level. The buffer Buffer generates a sufficiently large current I4 to charge the gate of the power tube MH. At this time, the gate drive circuit uses I G3 =I G2 The current of +I4 charges the gate of the power tube MH.

[0041] By adjusting the currents of I1, I2, I3, and I4, the gate drive circuit will eventually charge the power tube as follows: Figure 5 As shown, when the V GS Less than V MT Previously, with a medium current I G1 Charging the gate of MH can, on the one hand, drive the power tube MH to reach the threshold voltage at a faster speed to optimize efficiency, and on the other hand, reduce dI / dt to reduce EMI. GS Equal to V MT When the small current I G2 Charging the gate of MH can reduce dV SW / dt to reduce EMI, when the V GS Greater than V MT When the large current I G3 The gate of MH is charged, thereby reducing the conduction loss of the power tube to improve efficiency.

[0042] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A gate drive circuit with multi-stage current drive, characterized in that: include: A self-biased current source unit for generating a reference current; a current mirror unit, connected to the self-biased current source unit, and used to replicate a reference current; A plurality of current generating units, connected to the current mirror unit, and configured to generate a plurality of different gate driving currents according to the reference current; The gate drive circuit realizes segmented control of the gate voltage of the power tube by adjusting the magnitude of the multiple segments of gate drive current, so as to optimize the conduction and cutoff process of the power tube, reduce electromagnetic interference and improve conversion efficiency.

2. The gate driving circuit with multi-stage current driving according to claim 1, characterized in that: The self-bias current source unit comprises: The first PMOS transistor M P5 , its source is connected to the power supply voltage VDD, and the gate and drain are short-circuited; The first NMOS transistor M N11 , whose gate and drain are connected to the gate and drain of the first PMOS transistor, and whose source is connected to the second NMOS transistor M N12 The drain; The second NMOS transistor M N12 , whose source is grounded GND and whose gate is connected to the first NMOS transistor M P5 The gate of is connected; The second PMOS transistor M P6 , whose source is connected to the power supply voltage VDD and whose gate is connected to the third PMOS transistor M P7 A gate and a drain, the drain being connected to the source of the first NMOS transistor; The third PMOS transistor M P7 , whose source is connected to the power supply voltage VDD; The third NMOS transistor M N13 , whose drain is connected to the source of the first NMOS transistor, the source is grounded GND, and the gate is connected to the fourth NMOS transistor M N14 The source of The fourth NMOS transistor M N14 , whose drain is connected to the gate of the second PMOS transistor, and whose gate is connected to one end of the resistor R3; The other end of the resistor R3 is grounded GND.

3. The gate driving circuit with multi-stage current driving according to claim 1, characterized in that: The current mirror unit comprises: The first LDMOS transistor M DP1 , whose source is connected to a first voltage V BST , the gate and drain are connected; The first NLDMOS transistor M DN1 , whose source is grounded GND and whose drain is connected to the first LDMOS transistor M DP1 The gate and drain of The fourth PMOS transistor M P8 , whose source is connected to the first voltage V BST , the drain is connected to the fifth NMOS transistor M N15 The gate and drain of the first NLDMOS transistor M DP1 The drain; The fifth NMOS transistor M N15 , whose source is connected to a second voltage V SW .

4. The gate driving circuit with multi-stage current driving according to claim 1, characterized in that: The plurality of current generating units include: The first current generating unit is used to generate a first gate driving current I G1 ; The second current generating unit is used to generate a second gate driving current I G2 ; The third current generating unit is used to generate a third gate driving current I G3 ; Wherein, the first current generating unit is when the gate voltage of the power tube is less than the Miller platform voltage V MT When the second current generating unit is working, the gate voltage of the power tube is equal to the Miller platform voltage V MT When the gate voltage of the power tube is greater than the Miller platform voltage V MT Working at the same time.

5. The gate driving circuit with multi-stage current driving according to claim 4, characterized in that: The first current generating unit comprises: The fifth PMOS transistor M P1 , whose source is connected to the first voltage V BST , the drain is connected to the sixth NMOS transistor M N1 A drain electrode and one end of a first resistor R1; The sixth NMOS transistor M N1 , whose gate is connected to the drive voltage V DRV , the source is connected to the seventh NMOS transistor M N2 The drain; The seventh NMOS transistor M N2 , whose source is connected to the second voltage V SW ; The other end of the first resistor R1 is connected to the first voltage V BST ; The sixth PMOS transistor M P2 , whose source is connected to the first voltage V BST , the drain is connected to the gate of the power tube MH.

6. The gate driving circuit with multi-stage current driving according to claim 4, characterized in that: The second current generating unit comprises: The eighth NMOS transistor M N6 , whose gate is connected to the ninth NMOS transistor M N9 The drain of the tenth NMOS transistor M N10 The drain; The seventh PMOS transistor M P3 , whose source is connected to the first voltage V BST , a drain electrode connected to the drain electrode of the tenth NMOS transistor; A second resistor R2, one end of which is connected to the first voltage V BST , the other end of which is connected to the gate of the seventh PMOS transistor; The eighth PMOS transistor M P4 , whose source is connected to the first voltage V BST , the drain is connected to the gate of the power tube MH.

7. The gate driving circuit with multi-stage current driving according to claim 4, characterized in that: The third current generating unit comprises: The ninth NMOS transistor M N9 , whose gate is connected to the first voltage V BST , the drain is connected to the input terminal of the inverter INV2; The inverter INV2, an output end of which is connected to an input end of the buffer Buffer; The output end of the buffer Buffer is connected to the gate of the power tube MH.

8. The gate driving circuit with multi-stage current driving according to claim 1, characterized in that: The gate drive circuit is used to drive the power tube MH to be turned on and off. The power tube MH is a lateral double diffused metal oxide semiconductor field effect transistor LDMOS or a gallium nitride high electron mobility transistor GaN HEMT.

9. The gate driving circuit with multi-stage current driving according to claim 1, characterized in that: The gate drive circuit is applied to a DC-DC converter to control the switching process of a power tube to achieve efficient conversion of electric energy.

10. A control method for a gate drive circuit with multi-stage current drive, characterized in that: The following steps are involved: generating a reference current by a self-biased current source unit; Using a current mirror unit to copy the reference current to a plurality of current generating units; When the gate voltage of the power tube is less than the Miller platform voltage, the gate of the power tube is charged with a first gate driving current through the first current generating unit; When the gate voltage of the power tube reaches the Miller platform voltage, the gate of the power tube is charged with a second gate driving current through the second current generating unit; When the gate voltage of the power tube exceeds the Miller platform voltage, the gate of the power tube is charged with a third gate driving current through the third current generating unit; By adjusting the magnitudes of the first gate drive current, the second gate drive current and the third gate drive current, segmented control of the gate voltage of the power tube is achieved to optimize the on and off process of the power tube, reduce electromagnetic interference and improve conversion efficiency.

Images