Low-mismatch low-power-consumption charge pump circuit with locking detection module

Abstract

The invention belongs to the field of integrated circuits, and particularly relates to a low-mismatch low-power-consumption charge pump circuit with a locking detection module. On the premise of realizing the normal function of the charge pump, the negative feedback circuit is introduced into the traditional charge pump structure to control the charge and discharge current, the switching speed of the charge pump is improved by introducing the current copying circuit, and the suppression capability on the spurious phase-locked loop is improved; and meanwhile, a locking detection module is introduced into the charge pump structure to control the charge-discharge current of the charge pump, so that the power consumption of the charge pump circuit is greatly reduced. Finally, the problem that an existing charge pump circuit is relatively poor in noise, stray performance and power consumption is effectively solved.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuits, and in particular relates to a low-mismatch and low-power consumption charge pump circuit with a lock detection module. Background Art

[0002] With the rapid development of wireless communication technology, the demand for high-speed, large-capacity, low-latency and low-power communications is growing. Therefore, communication systems need to use high-quality frequency sources as a benchmark to handle higher data rates and more complex signal processing tasks. The charge-pump phase-locked loop (CPPLL), with its excellent performance and stability, has become an ideal choice for achieving high-quality frequency sources. Since the performance of the charge pump circuit is directly related to the phase noise and spurious performance of the entire CPPLL system, optimizing the charge pump circuit design, suppressing spurious and improving its phase noise, while balancing its power consumption requirements, plays an important role in improving the performance of the communication system.

[0003] At present, the scheme commonly adopted in the design of CMOS charge pump circuit is: PMOS tube and NMOS tube respectively undertake the charging and discharging functions, and the charge pump charging and discharging process is controlled by the output signal of the phase detector of the charge pump pre-stage circuit in the phase-locked loop. Since the output signal of the phase detector reflects the phase difference between the reference clock signal and the feedback clock signal of the phase-locked loop, when the phase difference between the reference clock signal and the feedback clock signal of the phase-locked loop is too small, a "dead zone" effect will be generated, making it impossible for the charge pump to obtain a stable charging and discharging current. Therefore, at the beginning of the design of the phase-locked loop system, a certain delay will be introduced into the phase detector so that the output signal of the phase detector is high or low at the same time to reduce the "dead zone" effect, which will cause the charge pump to still be periodically turned on after the phase-locked loop is locked. If the charge pump switching speed is too slow and the conduction time is long, the phase difference between the reference clock signal and the feedback clock signal will be large after the phase-locked loop is locked, which will deteriorate the phase noise and spurious performance of the phase-locked loop. At the same time, since the charge and discharge currents of PMOS and NMOS tubes change in opposite trends with the drain voltage, it is difficult to achieve good consistency of the charge and discharge currents, which will also increase the phase difference between the reference clock signal and the feedback clock signal after the phase-locked loop is locked, thereby deteriorating the spurious performance of the phase-locked loop. In addition, although the phase noise performance of the phase-locked loop can be optimized by increasing the charge and discharge current of the charge pump, this will sharply increase the power consumption of the charge pump.

[0004] With the advancement of integrated circuit process nodes and the demand for miniaturization and low power consumption, balancing the phase-locked loop noise performance and charge pump power consumption requirements, as well as suppressing the phase-locked loop spurious by reducing the charge pump current mismatch and increasing the switching speed, have become technical problems that need to be solved urgently. Summary of the invention

[0005] In view of the above-mentioned problems or deficiencies, and in order to solve the problems of noise, spurious performance and relatively poor power consumption in the existing charge pump circuit, the present invention provides a low-mismatch and low-power charge pump circuit with a lock detection module. Under the premise of realizing the normal function of the charge pump, the present invention controls the size of the charge and discharge current by introducing a negative feedback circuit in the traditional charge pump structure, and increases the switching speed of the charge pump by introducing a current replication circuit, thereby improving the ability to suppress the spurious of the phase-locked loop; at the same time, by introducing a lock detection module in the charge pump structure, the size of the charge and discharge current of the charge pump is controlled, thereby greatly reducing the power consumption of the charge pump circuit.

[0006] A low-mismatch and low-power consumption charge pump circuit with a lock detection module comprises a charge pump main body module, a current tracking module, an auxiliary charge and discharge module and a lock detection module.

[0007] The charge pump main body module adjusts the charging and discharging time of the loop filter load capacitor of the charge pump post-stage circuit in the phase-locked loop according to the output signal of the frequency detector and phase detector of the charge pump pre-stage circuit in the phase-locked loop, and converts the phase difference between the reference clock signal and the feedback clock signal of the phase-locked loop into a charge quantity signal.

[0008] The current tracking module detects the change of the charging current of the charge pump main module, and adjusts the discharge current of the charge pump main module to be the same as the charging current.

[0009] The auxiliary charge and discharge module provides a second path for the charge and discharge current of the charge pump main module, so that the charge and discharge current source transistor in the charge pump main module always remains in an on state; at the same time, the charge and discharge current source transistor of the second path is set to have the same current as the charge and discharge current source transistor of the charge pump main module, thereby reducing the voltage difference between the drain node and the output node of the charge and discharge current source transistor of the charge pump main module and reducing the charge pump current mismatch.

[0010] The lock detection module determines whether the phase-locked loop is locked according to the output voltage of the charge pump main module, thereby controlling the charge pump main module, the current tracking module and the auxiliary charge and discharge module to simultaneously flow a larger current before the phase-locked loop is locked or a smaller current after the phase-locked loop is locked.

[0011] Furthermore, the charge pump main body module includes transistors MP4, MP5, MN3, MN4, MP10, MN9 and switches SW2 and SW5.

[0012] The gates of MP4 and MP5 are connected and connected to the bias current IREF, the sources of MP4 and MP5 are connected to the power supply potential VDD, and the drains of MP4 and MP5 are respectively connected to the two ends of the switch SW2; the drain of MP4 is also connected to the source of MP10, the gate of MP10 is connected to the output signal UP of the frequency detector and phase detector of the previous stage circuit, the drain of MP10 is connected to the drain of MN9 and serves as the output node VCTRL; the gate of MN9 is connected to the output signal DN of the frequency detector and phase detector of the previous stage circuit, the source of MN9 is connected to one end of the switch SW5 and the drain of MN3; the gates of MN3 and MN4 are connected and connected to the output end of the operational amplifier OP in the current tracking module, the sources of MN3 and MN4 are both connected to the ground potential GND, and the drains of MN3 and MN4 are respectively connected to the two ends of the switch SW5.

[0013] Transistors MP4 and MP5 are charging current sources, and transistors MN3 and MN4 are discharging current sources. Transistors MP10 and MN9 are controlled on and off by the output signals UP and DN of the frequency detector and phase detector of the charge pump pre-stage circuit in the phase-locked loop, thereby controlling the on and off of the charging current path composed of MP4, MP5, SW2 and MP10 and the discharging current path composed of MN3, MN4, SW5 and MN9.

[0014] Switches SW2 and SW5 are two transmission gate switches, which are controlled by the lock detection module output signals VCLK and VCLKB to set a larger current value before the phase-locked loop is locked or a smaller current value after the phase-locked loop is locked for the charge pump main module to charge and discharge the output node VCTRL.

[0015] Furthermore, the current tracking module includes transistors MP6, MP7, MN5, MN6, MP11, MN10, switches SW3, SW6 and an operational amplifier OP.

[0016] The gates of MP6 and MP7 are connected to the gate of MP5 and connected to the bias current IREF. The sources of MP6 and MP7 are connected to the power supply potential VDD. The drains of MP6 and MP7 are connected to the two ends of the switch SW3 respectively. The drain of MP6 is also connected to the source of MP11. The gate of MP11 is connected to the ground potential GND. The drain of MP11 is connected to the drain of MN10 and the positive input terminal of the operational amplifier OP. The gate of MN10 is connected to the power supply potential VDD. The source of MN10 is connected to one end of the switch SW6 and the drain of MN5. The gates of MN5 and MN6 are connected to the gates of MN3 and MN4 and connected to the output terminal of the operational amplifier OP. The sources of MN5 and MN6 are connected to the ground potential GND. The drains of MN5 and MN6 are connected to the two ends of the switch SW5 respectively. The negative input terminal of the operational amplifier OP is connected to the drains of MP10 and MN9.

[0017] Transistors MP6 and MP7 are charging current sources, and transistors MN5 and MN6 are discharging current sources. The drains of transistors MP11 and MN10 are connected to the ground potential GND and the power supply potential VDD, respectively, so as to control the charging current path composed of MP6, MP7, SW3 and MP11 and the discharging current path composed of MN5, MN6, SW6 and MN10 to be always on. Switches SW3 and SW6 are two transmission gate switches, which are controlled on and off by the output signals VCLK and VCLKB of the lock detection module, so as to set the current tracking module with the same larger current value before the phase-locked loop is locked or the smaller current value after the phase-locked loop is locked as the charge pump main module. The operational amplifier OP provides negative feedback to force the actual charging and discharging current size of the charge pump main module to be consistent with the current tracking module.

[0018] Furthermore, the auxiliary charge and discharge module includes transistors MP1, MP2, MP3, MP8, MN8, MN1, MN2, MN7, MP9 and switches SW1, SW4.

[0019] The gates of MP1, MP2 and MP3 are connected to the gate of MP4 and then connected to the bias current IREF. The sources of MP1, MP2 and MP3 are all connected to the power supply potential VDD. The drains of MP2 and MP3 are respectively connected to the two ends of the switch SW1. The gate and drain of MP1 are short-circuited and then connected to the bias current IREF. The drain of MP2 is also connected to the source of MP8. The gate of MP8 is connected to the ground potential GND. The drain of MP8 is connected to the drain of MN8. The gate of MN8 is connected to the output signal DNB of the frequency detector of the previous stage circuit. The source of MN8 is connected to the drain of MN3 and the source of MN9. The gate of MN7 is connected to the power supply potential VDD. The source of MN7 is connected to one end of the switch SW4 and the drain of MN1. The drain of MN7 is connected to the drain of MP9. The gate of MP9 is connected to the output signal UPB of the frequency detector of the previous stage circuit. The source of MN9 is connected to the drain of MP4 and the source of MP10. The sources of MN1 and MN2 are both connected to the ground potential GND, the drains of MN1 and MN2 are respectively connected to the two ends of the switch SW4, and the gates of MN1, MN2, MN3, MN4, MN5 and MN6 are connected to the output end of the operational amplifier OP.

[0020] Among them, MP1 is a current mirror transistor with a gate and drain short-circuited, which is responsible for receiving the bias current IREF and copying it to the charge pump main module, the current tracking module and the charge pump main module.

[0021] Transistors MP2, MP3, MP8, MN8 and switch SW1 constitute an auxiliary charging circuit. This branch is connected to the drain nodes of transistors MN3 and MN4 in the charge pump main module, and is responsible for providing a current path for transistors MN3 and MN4 under the control of the output signal DNB of the frequency detector of the charge pump front-stage circuit in the phase-locked loop, so that they always remain in the open state.

[0022] Transistors MN1, MN2, MN7, MP9 and switch SW4 constitute an auxiliary discharge circuit, which is connected to the drain nodes of transistors MP4 and MP5 in the charge pump main module and is responsible for providing a current path for transistors MP4 and MP5 under the control of the output signal UPB of the frequency detector and phase detector of the charge pump front-stage circuit in the phase-locked loop, so that they always remain in the open state.

[0023] Furthermore, the lock detection module includes comparators COM1 and COM2, logic gates AND1, AND2, and NOT1, and a D flip-flop chain DFF1-DFF10.

[0024] Wherein the negative input terminal of comparator COM1 and the positive input terminal of comparator COM2 are both connected to the output node VCTRL of the charge pump main module, the positive input terminal of COM1 is connected to the reference voltage VREF- which is lower than VCTRL after the phase-locked loop is locked, and the negative input terminal of COM2 is connected to the reference voltage VREF+ which is higher than VCTRL after the phase-locked loop is locked; the input terminal of AND1 is connected to the output terminals of COM1 and COM2, and the output terminal of AND1 is connected to the D input terminal of DFF1;

[0025] The Q output terminals of DFF1-DFF9 are connected to the D input terminals of DFF2-DFF10 respectively and one by one, and the Q output terminals of DFF1-DFF10 are connected to the input terminal of AND2, and the clock terminals of DFF1-DFF10 are connected to the reference clock signal CLK of the phase-locked loop; the input terminal of NOT1 is connected to the output terminal of AND2, and the input terminal of NOT1 generates a locking flag signal VLCK; the output terminal of NOT1 generates a locking flag signal VLCKB.

[0026] The lock detection module determines whether the phase-locked loop is locked by comparing the output voltage of the charge pump main module with the reference voltages VREF+ and VREF-, as well as the output signal level of the D-type flip-flop chain, and turns the lock flag signals VLCK and VLCKB on or off through the control switches SW1-SW6 to set the larger current value before the phase-locked loop is locked or the smaller current value after the phase-locked loop is locked in the charge pump main module, the current tracking module and the charge pump main module.

[0027] In summary, the present invention controls the charge and discharge current by introducing a negative feedback circuit, and increases the switching speed of the charge pump by introducing a current replication circuit, thereby improving the ability to suppress the spurious signals of the phase-locked loop; at the same time, by introducing a lock detection module into the charge pump structure, the charge and discharge current of the charge pump is controlled, thereby greatly reducing the power consumption of the charge pump circuit. The present invention effectively solves the problems of relatively poor noise, spurious performance and power consumption of the existing charge pump circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a module block diagram of the present invention.

[0029] Figure 2 A circuit diagram of an embodiment.

[0030] Figure 3 FIG. 4 is an equivalent circuit diagram of the embodiment during the charging process before the phase-locked loop is locked.

[0031] Figure 4 FIG. 4 is an equivalent circuit diagram of the embodiment after the phase-locked loop is locked.

[0032] Figure 5 The following is a working condition of the lock detection module in the embodiment.

[0033] Figure 6 The embodiment is compared with the charging and discharging current mismatch of the conventional drain switch charge pump.

[0034] Figure 7 The embodiment compares the phase difference between the reference clock signal and the feedback clock signal and the charge pump output voltage ripple of the conventional drain switch charge pump after the phase-locked loop is locked. DETAILED DESCRIPTION

[0035] The technical solution of the present invention is described in more detail below in conjunction with the embodiments and drawings.

[0036] Reference Figure 2 , Figure 3 and Figure 4 , the working process of the charge pump before and after the phase-locked loop is locked will now be described.

[0037] Reference Figure 2 , is a specific circuit structure diagram of this embodiment; before the phase-locked loop is locked, when the charge pump is in the charging process, the output signal UP of the frequency detector of the charge pump front-stage circuit in the phase-locked loop is low, DN is low, UPB is high, and DNB is high. At this time, MP9 and MN9 tubes are turned off, and MP10 and MN8 tubes are turned on. At the same time, it is believed that before the phase-locked loop is locked, the charge pump output voltage VCTRL voltage will not remain in the range of VREF-~VREF+ in 10 consecutive reference clock signal cycles. That is, the AND gate AND1 will output low in at least 1 reference clock signal cycle in 10 consecutive reference clock signal cycles, so that at least 1 of the Q output signals of the 10 DFFs is low, which makes the AND gate AND2 output low. Therefore, the lock detection module outputs a low VLCK signal and a high VLCKB signal, indicating that the phase-locked loop is not locked, so that switches SW1-SW6 are all closed. Therefore, when the charge pump is in the charging process, Figure 2 The circuit shown can be equivalent to Figure 3 The circuit shown.

[0038] Reference Figure 3, MP4 and MP5 tubes charge the output node a. Due to the negative feedback of the operational amplifier OP, the voltages of node a and node b are equal under ideal conditions. MP6 and MP4, MP5 and MP7, MP10 and MP11 tubes have the same width and length, so it can be considered that the current flowing through MP10 is the same as the current flowing through MP11. Because of the "virtual disconnection" effect at the positive input of the operational amplifier, a current path cannot be formed, and the current flowing through MP11 is the same as the sum of the currents flowing through MN5 and MN6.

[0039] When the voltage of node a changes due to charging the load capacitor of the loop filter in the post-stage circuit of the charge pump in the phase-locked loop, it will affect the drain voltage of the charging current source tubes MP4 and MP5, causing the charging current of the charge pump main module to change. Since the voltage of node b remains equal to the voltage of node a, the current flowing through MP11 and the current flowing through MP10 and MN10 will remain equal, so the current of the current tracking module will change accordingly. At the same time, the voltage of the op amp output node e will also change to adapt to the voltage changes of nodes a and b. Figure 2 It can be seen that the op amp output node e is connected to the gate of MN1-MN6, so the voltage change of node e will adjust the current of MN1-MN6. Since MN1, MN3, and MN5 have the same size, and MN2, MN4, and MN6 have the same size, Figure 3 The sum of the currents flowing through MN5 and MN6 is the same as the sum of the currents flowing through MN3 and MN4, thus achieving a high degree of matching between the charging current and the discharging current of the charge pump main module. Figure 6 It can also be seen from the simulation results of the mismatch of charge and discharge current that within a wider range of charge pump output voltage, the maximum mismatch of the charge pump structure proposed by the present invention is much smaller than that of the traditional drain switch charge pump structure.

[0040] In addition, since the sum of the currents of MN3 and MN4 is the sum of the currents flowing through MP2 and MP3, and MP6 and MP2, MP7 and MP3, MP11 and MP8 have the same width and length, the voltage at node c will be consistent with the voltage at node b, and the voltage at node d is lower than the voltage at node c by the drain-source voltage Vds of MN8. NN8 ,Right now

[0041] V d =V c -Vds MN8 =V b -Vds MN8 =VCTRL-Vds MN8

[0042] Since the MN8 tube is generally in the deep linear region when it is turned on, its drain-source voltage Vds MN8is small, and the voltage at node d is the drain node voltage of the discharge current source MN3 and MN4 tubes of the charge pump main module. Therefore, when the charge pump is in the charging process, there is a small voltage difference between the discharge current source drain node and the output node. When the traditional drain switch charge pump is in the charging process, the discharge current source drain node will be discharged to the ground potential, so there is a large voltage difference between the discharge current source drain node and the output node. This will cause the discharge current source drain node capacitor and the output node capacitor to share charge at the beginning of the charge pump discharge process, thereby causing a certain error in the charge amount on the load capacitor of the loop filter of the charge pump post-stage circuit in the phase-locked loop, aggravating the mismatch of the charge pump. In addition, since the traditional drain switch charge pump needs a certain time to charge the discharge current source drain node before the discharge current source can provide the required discharge current, the charge pump switching speed is also reduced. Therefore, the introduction of the auxiliary charge and discharge module further reduces the charge pump mismatch and improves the switching speed of the charge pump.

[0043] Before the phase-locked loop is locked, when the charge pump is in the charging process, the operating principle of the charge pump circuit is similar to the above process.

[0044] Further, refer to Figure 2 After the phase-locked loop is locked, ideally, the frequency detector output signals UP and DN are periodically high or low at the same time, and correspondingly, the frequency detector output signals UPB and DNB are periodically low or high at the same time. At this time, MP10 and MN9 are periodically turned on or off at the same time, and correspondingly, MP9 and MN8 are periodically turned off or on at the same time. At the same time, it is considered that when the charge pump is locked, the charge pump output voltage VCTRL voltage is maintained in the range of VREF-~VREF+ within 9 consecutive reference clock signal cycles and when the rising edge of the 10th reference clock signal arrives, that is, the AND gate AND1 outputs high within 10 consecutive reference clock signal cycles, so that the Q output signals of the 10 DFFs are all high, making the AND gate AND2 output high. Figure 5 The circuit simulation results of the lock detection module in the above process show that the lock detection module functions correctly. Therefore, the lock detection module outputs a high VLCK signal and a low VLCKB signal, indicating that the phase-locked loop is locked, and switches SW1-SW6 are all turned off, and then Figure 2 The circuit shown can be equivalent to Figure 4 The circuit shown.

[0045] Reference Figure 4 When switches SW1-SW6 are all turned off, the charge and discharge current of the charge pump is set to a smaller current value determined by the ratio of the width-to-length ratio of MP4 and MP1 and the bias current IREF. Assume Figure 2 middle

[0046]

[0047] Where n is a real number greater than 1, then ideally the static power consumption of the charge pump after locking can be reduced to

[0048] After the phase-locked loop is locked, when the frequency detector output signals UP and DN are both high, and the corresponding UPB and DNB signals are both low, there is a slight deviation in the charge pump charge and discharge current, and the voltage of the charge pump output voltage VCTRL produces ripples. After adjustment by the phase-locked loop, there will be a small phase difference between the reference clock signal and the feedback clock signal to stabilize the charge pump output voltage VCTRL. Due to the introduction of the current tracking module and the auxiliary charge and discharge module, the charge pump charge and discharge current deviation proposed by the present invention is smaller than that of the traditional drain switch charge pump, and the charge pump charge and discharge current is reduced to before locking. So the charge pump

[0049] The output voltage VCTRL ripple and the phase difference between the reference clock signal and the feedback clock signal are greatly reduced compared to traditional drain switches.

[0050] Reflected in the phase-locked loop, assuming that the loop filter is of second-order form, the signal acting on both ends of the loop filter resistor R is of strength I cp R, duty cycle is The angular frequency is ω ref If only the first-order harmonic component of the signal is considered and other harmonic components are ignored, the signal is filtered by the loop filter of the charge pump post-stage circuit in the phase-locked loop and acts on the input end of the voltage-controlled oscillator of the loop filter post-stage circuit in the phase-locked loop, modulating the output signal frequency of the voltage-controlled oscillator, thereby generating spurious. Since the amplitude of the first-order harmonic component can be expressed as Therefore, the spurious value of the pulse voltage at a frequency that deviates from the phase-locked loop output signal frequency by 1 times the reference signal frequency can be expressed as:

[0051]

[0052] Among them, ω p1 It is the first low-pass pole of the loop filter. From the above formula, it can be seen that reducing the phase difference between the reference clock signal and the feedback clock signal after the loop is locked can suppress the spurious signal of the phase-locked loop.

[0053] In the charge pump structure proposed in the present invention, the phase difference between the reference clock signal and the feedback clock signal caused by the change in the charge pump output voltage VCTRL is:

[0054]

[0055] in, It indicates the charge error on the load capacitor of the loop filter in the post-charge pump circuit of the phase-locked loop caused by non-ideal effects such as switch mismatch, charge sharing and clock feedthrough. cp T ref Represents the charge and discharge current I cp In the reference clock signal period T ref The amount of charge generated by charging the charge pump output node. represents the charge error caused by the mismatch of the charge pump charging and discharging current source, where ∈ represents the charge and discharge current relative to I cp The mismatch degree, t turn-on It indicates the time that the charge pumps are turned on simultaneously after the phase-locked loop is locked. From the above formula, it can be seen that reducing the current mismatch of the charge pump and increasing the switching speed of the charge pump can reduce the phase difference between the reference clock signal and the feedback clock signal after the loop is locked.

[0056] Reference Figure 7 From the simulation results of the phase difference between the reference clock signal and the feedback clock signal and the charge pump output voltage ripple of the charge pump proposed in the present invention and the traditional drain switch charge pump after the phase-locked loop is locked, it can be seen that compared with the traditional drain switch charge pump structure, the charge pump structure proposed in the present invention has better improvements in voltage ripple and the phase difference between the clock signal and the feedback clock signal.

Claims

1. A low mismatch and low power consumption charge pump circuit with a lock detection module, characterized in that: It includes a charge pump main body module, a current tracking module, an auxiliary charge and discharge module and a lock detection module; The charge pump main body module adjusts the charging and discharging time of the load capacitor of the loop filter of the charge pump post-stage circuit in the phase-locked loop according to the output signal of the frequency detector and phase detector of the charge pump pre-stage circuit in the phase-locked loop, and converts the phase difference between the reference clock signal and the feedback clock signal of the phase-locked loop into a charge quantity signal; The current tracking module detects the change of the charging current of the charge pump main module, and adjusts the discharge current of the charge pump main module to be the same as the charging current; The auxiliary charge and discharge module provides a second path for the charge and discharge current of the charge pump main module, so that the charge and discharge current source transistor in the charge pump main module is always kept in an on state; at the same time, the charge and discharge current source transistor of the second path is set to have the same current as the charge and discharge current source transistor of the charge pump main module; The lock detection module determines whether the phase-locked loop is locked according to the output voltage of the charge pump main module, thereby controlling the charge pump main module, the current tracking module and the auxiliary charge and discharge module to simultaneously flow a larger current before the phase-locked loop is locked or a smaller current after the phase-locked loop is locked.

2. The low mismatch and low power consumption charge pump circuit with a lock detection module as claimed in claim 1, characterized in that: The charge pump main body module includes transistors MP4, MP5, MN3, MN4, MP10, MN9 and switches SW2 and SW5; The gates of MP4 and MP5 are connected and connected to the bias current IREF, the sources of MP4 and MP5 are connected to the power supply potential VDD, and the drains of MP4 and MP5 are connected to the two ends of the switch SW2 respectively; the drain of MP4 is also connected to the source of MP10, the gate of MP10 is connected to the output signal UP of the frequency detector of the previous stage circuit, and the drain of MP10 is connected to the drain of MN9 and serves as the output node VCTRL; the gate of MN9 is connected to the output signal DN of the frequency detector of the previous stage circuit, and the source of MN9 is connected to one end of the switch SW5 and the drain of MN3; the gates of MN3 and MN4 are connected and connected to the output end of the operational amplifier OP in the current tracking module, the sources of MN3 and MN4 are connected to the ground potential GND, and the drains of MN3 and MN4 are connected to the two ends of the switch SW5 respectively; Transistors MP4 and MP5 are charging current sources, and transistors MN3 and MN4 are discharging current sources; transistors MP10 and MN9 are controlled on and off by the output signals UP and DN of the frequency detector and phase detector of the charge pump pre-stage circuit in the phase-locked loop, thereby controlling the on and off of the charging current path composed of MP4, MP5, SW2 and MP10 and the discharging current path composed of MN3, MN4, SW5 and MN9; Switches SW2 and SW5 are two transmission gate switches, which are controlled by the lock detection module output signals VCLK and VCLKB to set a larger current value before the phase-locked loop is locked or a smaller current value after the phase-locked loop is locked for the charge pump main module to charge and discharge the output node VCTRL.

3. The low mismatch and low power consumption charge pump circuit with a lock detection module as claimed in claim 2, characterized in that: The current tracking module includes transistors MP6, MP7, MN5, MN6, MP11, MN10, switches SW3, SW6 and an operational amplifier OP; The gates of MP6 and MP7 are connected to the gate of MP5 and connected to the bias current IREF, the sources of MP6 and MP7 are connected to the power supply potential VDD, and the drains of MP6 and MP7 are connected to the two ends of the switch SW3 respectively; the drain of MP6 is also connected to the source of MP11, the gate of MP11 is connected to the ground potential GND, and the drain of MP11 is connected to the drain of MN10 and the positive input terminal of the operational amplifier OP; the gate of MN10 is connected to the power supply potential VDD, and the source of MN10 is connected to one end of the switch SW6 and the drain of MN5; the gates of MN5 and MN6 are connected to the gate of MN4 and connected to the output terminal of the operational amplifier OP, the sources of MN5 and MN6 are connected to the ground potential GND, and the drains of MN5 and MN6 are connected to the two ends of the switch SW5 respectively; the negative input terminal of the operational amplifier OP is connected to the drains of MP10 and MN9; Transistors MP6 and MP7 are charging current sources, and transistors MN5 and MN6 are discharging current sources; The drains of transistors MP11 and MN10 are connected to the ground potential GND and the power supply potential VDD respectively, thereby controlling the charging current path composed of MP6, MP7, SW3 and MP11 and the discharging current path composed of MN5, MN6, SW6 and MN10 to be always turned on; switches SW3 and SW6 are two transmission gate switches, which are controlled on and off by the output signals VCLK and VCLKB of the lock detection module, thereby setting a larger current value before the phase-locked loop is locked or a smaller current value after the phase-locked loop is locked, which is the same as that of the charge pump main module, for the current tracking module; the operational amplifier OP provides negative feedback to force the actual charging and discharging current size of the charge pump main module to be consistent with that of the current tracking module.

4. The low mismatch and low power consumption charge pump circuit with a lock detection module as claimed in claim 3, characterized in that: The auxiliary charge and discharge module includes transistors MP1, MP2, MP3, MP8, MN8, MN1, MN2, MN7, MP9 and switches SW1, SW4; The gates of MP1, MP2 and MP3 are connected to the gate of MP4 and then connected to the bias current IREF. The sources of MP1, MP2 and MP3 are all connected to the power supply potential VDD. The drains of MP2 and MP3 are respectively connected to the two ends of the switch SW1. The gate and drain of MP1 are short-circuited and then connected to the bias current IREF. The drain of MP2 is also connected to the source of MP8. The gate of MP8 is connected to the ground potential GND. The drain of MP8 is connected to the drain of MN8. The gate of MN8 is connected to the output signal DNB of the frequency detector and phase detector of the previous stage circuit. The source of MN8 is connected to the drain of MN3 and MN9. The source of MN7; the gate of MN7 is connected to the power supply potential VDD, the source of MN7 is connected to one end of the switch SW4 and the drain of MN1, and the drain of MN7 is connected to the drain of MP9; the gate of MP9 is connected to the output signal UPB of the frequency detector and phase detector of the previous stage circuit, and the source of MN9 is connected to the drain of MP4 and the source of MP10; the sources of MN1 and MN2 are both connected to the ground potential GND, and the drains of MN1 and MN2 are respectively connected to the two ends of the switch SW4, and the gates of MN1, MN2, MN3, MN4, MN5 and MN6 are connected and connected to the output end of the operational amplifier OP; Among them, MP1 is a current mirror transistor with a gate and drain short-circuited, which is responsible for receiving the bias current IREF and copying it to the charge pump main module, the current tracking module and the charge pump main module; Transistors MP2, MP3, MP8, MN8 and switch SW1 form an auxiliary charging circuit, which is connected to the drain nodes of transistors MN3 and MN4 in the charge pump main module, and is responsible for providing a current path for transistors MN3 and MN4 under the control of the output signal DNB of the phase detector of the charge pump front circuit in the phase-locked loop, so that they are always kept in an open state; Transistors MN1, MN2, MN7, MP9 and switch SW4 constitute an auxiliary discharge circuit, which is connected to the drain nodes of transistors MP4 and MP5 in the charge pump main module and is responsible for providing a current path for transistors MP4 and MP5 under the control of the output signal UPB of the frequency detector and phase detector of the charge pump front-stage circuit in the phase-locked loop, so that they always remain in the open state.

5. The low mismatch and low power consumption charge pump circuit with a lock detection module as claimed in claim 1, characterized in that: The lock detection module includes comparators CMO1, COM2, logic gates AND1, AND2, NOT1, and a D flip-flop chain DFF1-DFF10; Wherein the negative input terminal of comparator COM1 and the positive input terminal of comparator COM2 are both connected to the output node VCTRL of the charge pump main module, the positive input terminal of COM1 is connected to the reference voltage VREF- which is lower than VCTRL after the phase-locked loop is locked, and the negative input terminal of COM2 is connected to the reference voltage VREF+ which is higher than VCTRL after the phase-locked loop is locked; the input terminal of AND1 is connected to the output terminals of COM1 and COM2, and the output terminal of AND1 is connected to the D input terminal of DFF1; The Q output terminals of DFF1-DFF9 are connected to the D input terminals of DFF2-DFF10 in sequence and one by one, and the Q output terminals of DFF1-DFF10 are connected to the input terminal of AND2, and the clock terminals of DFF1-DFF10 are connected to the reference clock signal CLK of the phase-locked loop; the input terminal of NOT1 is connected to the output terminal of AND2, and the input terminal of NOT1 generates a locking flag signal VLCK; the output terminal of NOT1 generates a locking flag signal VLCKB; The lock detection module determines whether the phase-locked loop is locked by comparing the output voltage of the charge pump main module with the reference voltages VREF+ and VREF-, as well as the output signal level of the D-type flip-flop chain, and turns the lock flag signals VLCK and VLCKB on or off through the control switches SW1-SW6 to set the larger current value before the phase-locked loop is locked or the smaller current value after the phase-locked loop is locked in the charge pump main module, the current tracking module and the charge pump main module.

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