Analog front-end chip for ultrasonic imaging digital beam forming

Abstract

The invention discloses an analog front-end chip for ultrasonic imaging digital beam forming. The circuit comprises a low noise amplifier (LNA) and an analog-to-digital converter (ADC). The noise amplifier LNA comprises a programmable gain amplifier PGA and an output stage amplifier; the main structure of the PGA is a pseudo-differential capacitance feedback amplifier, and the function of time gain compensation TGC is achieved by changing the proportion of input capacitance and output capacitance. The output-stage amplifier is a two-stage amplifier, and the first-stage operational transconductance amplifier OTA is of an Inver-Based structure; the OTA at the second stage adopts a class-AB structure; the OTA of the first stage and the OTA of the second stage use independent common-mode feedback; a closed-loop structure of the output-stage amplifier is realized by adopting a split capacitor structure; according to the invention, digital-to-analog conversion of a single channel is realized by adopting the SAR ADC, and the analog front end for ultrasound with a high dynamic range and a high signal-to-noise ratio is realized with relatively small power consumption and area.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular, relates to an analog front-end chip for digital beamforming of ultrasonic imaging. Background Art

[0002] Ultrasound imaging technology has become the fastest-growing and most widely used medical imaging tool in recent years due to its advantages such as non-invasiveness, high sensitivity and low cost. With the changes in clinical needs and the advancement of electronic technology, ultrasound imaging modalities have evolved from early one-dimensional A-type and M-type imaging to today's mature real-time two-dimensional B-type imaging. Real-time three-dimensional ultrasound imaging can intuitively display the depth relationship of organs and the direction of dynamic blood flow, allowing doctors to more accurately measure structural parameters and locate diseased tissues. It is recognized as the development direction of the next generation of ultrasound imaging technology. However, real-time three-dimensional ultrasound imaging relies on a large-scale two-dimensional transducer array, and the number of array elements required is often thousands or even tens of thousands, which poses a huge technical challenge to the real-time lossless acquisition and image processing of ultrasound signals. The key to solving this challenge lies in how to design and integrate high-performance large-scale front-end dedicated cores for traditional passive ultrasound transducer arrays, achieve high-precision signal acquisition and efficient data compression under limited physical channel resources and strict power consumption constraints, and at the same time give it edge image processing capabilities.

[0003] The digitization of 3D ultrasound probes is an important driving force for the development of on-chip ultrasound. Figure 1 As shown, the traditional ultrasound front end performs local analog domain beam synthesis and outputs analog signals. Although only a single ADC is required at the system level, array ultrasound chips often require multiple output cables, which is not conducive to the miniaturization of ultrasound equipment. Secondly, analog beam synthesis is insufficient in accuracy and flexibility. Analog beam synthesis requires delaying and adding the original analog signals of multiple channels in the analog domain, so that information in one direction can be obtained, but information in other directions will be lost. In order to obtain information in other directions, the transducer needs to be driven again to generate ultrasonic waves and wait for the reflected ultrasonic waves, which wastes time and power and leads to a decrease in imaging frame rate. Finally, analog signals are easily interfered when transmitted through cables, resulting in a decrease in signal quality.

[0004] There are two main approaches to achieve digital beamforming at the transducer element level. The first is to use SAR ADC for analog-to-digital conversion, but due to the limited area of ​​ADC, it is often difficult to use a single ADC for each channel. A common approach is to combine multiple transducers (4-9) into a transducer subarray. [4]-[7], each sub-array shares one ADC. This approach can increase transducer density and reduce the average power consumption of each channel, but it limits the flexibility of imaging. Another approach is to use Sigma-delta ADC for digital-to-analog conversion. Since Sigma-delta ADC does not require a DAC array that takes up a large area, it can achieve the use of one ADC per channel, but it is difficult to achieve the low power consumption and high precision of SAR ADC. Summary of the invention

[0005] In view of the above-mentioned deficiencies in the prior art, the object of the present invention is to provide an analog front-end chip for digital beamforming of ultrasound imaging; the present invention adopts SAR ADC to realize single-channel digital-to-analog conversion, and realizes an analog front end for ultrasound with high dynamic range and high signal-to-noise ratio with smaller power consumption and area.

[0006] The present invention provides an analog front-end chip for ultrasonic imaging digital beamforming, which comprises a low noise amplifier LNA and an analog-to-digital converter ADC; wherein:

[0007] The low noise amplifier LNA includes a programmable gain amplifier PGA and an output stage amplifier; the programmable gain amplifier PGA adopts a pseudo-differential capacitor feedback amplifier structure, wherein the operational transconductance amplifier OTA adopts an inverter-based structure, i.e., NMOS and PMOS are used as input terminals at the same time, and the operational transconductance amplifier OTA is a common source and common gate cascode structure, and the differential structure uses common mode feedback to determine its output common mode voltage; the capacitor feedback is implemented using a split capacitor feedback structure, i.e., the operational transconductance amplifier OTA is regarded as having two positive input terminals and two negative input terminals, and then the input capacitor and the output capacitor are divided into two pairs of equal capacitors to implement the feedback structure; the output stage amplifier is a two-stage amplifier, and the first-stage operational transconductance amplifier OTA adopts an inverter-based structure, which improves the energy efficiency of the circuit; the second-stage operational transconductance amplifier OTA adopts a class-AB structure; the first-stage and second-stage operational transconductance amplifiers OTA use separate common mode feedback, and the static operating point of the second-stage Class-AB structure is determined by the common mode level of the first stage; the closed-loop structure of the output stage amplifier is also implemented using a split capacitor feedback structure;

[0008] The analog-to-digital converter ADC adopts SAR ADC to realize single-channel digital-to-analog conversion.

[0009] In the present invention, the gate length of the NMOS tube is greater than the gate length of the PMOS tube.

[0010] In the present invention, in the low noise amplifier LNA, for the differential input pair of PMOS tubes, the DC level is determined by connecting to a fixed potential using a pseudo resistor, and for the differential input pair of NMOS tubes, the DC level is determined by connecting to the output end using a pseudo resistor.

[0011] In the present invention, during operation, a dynamic power control method is adopted so that the direct current of the programmable gain amplifier PGA increases synchronously when the gain increases.

[0012] In the present invention, the SAR ADC is mainly composed of a sampling switch, a DAC capacitor array, a comparator, a digital error correction DEC, a SAR logic and an output buffer; wherein: the sampling switch adopts a bootstrap switch, the comparator adopts an improved Elzakker type comparator, which includes a preamplifier and a latch, the current sources of the two are independent of each other, and the comparator input uses a copy input pair tube technology; the capacitance of the DAC capacitor array is a unit-length structure, which uses the difference between the interdigital capacitances as the unit capacitance value.

[0013] In the present invention, the capacitor of the unit-length structure includes two unit capacitor structures; the Binary unit realizes the binary change of its unit capacitance by adjusting the relative length of two interdigitated capacitor metals, and the Unary unit controls its binary change by using the Binary unit in proportion.

[0014] In the present invention, binary compensation redundancy is used to design the capacitance weight of the DAC array.

[0015] In the present invention, the analog-to-digital converter ADC adopts a dynamic control logic method to determine the conversion time of each bit according to the size of the input signal, and the specific steps include:

[0016] 1) When the SAR ADC is in the sampling phase, the combinational logic controls the comparator to enter the reset phase;

[0017] 2) When the SAR ADC enters the conversion phase, the potential of the sampling clock changes from V DD Convert to V SS , the combinational logic controls the comparator to start comparing the MSB bit; when the comparison of the comparator is completed, the comparator controls the VALID signal from V SS Switch to V DD , the combinational logic controls the comparator to enter the reset phase;

[0018] 3) When the comparator reset is completed, the comparator controls the VALID signal from V DD Switch to V SS , the combinational logic controls the comparator to perform the next comparison;

[0019] 4) Repeat the second and third steps above until all conversions are completed and the LOGIC_END signal is V SS Switch to V DD , the combinational logic controls the comparator to stop working and remain in a reset state until the next conversion begins.

[0020] In the present invention, the switching timing used in the analog-to-digital converter ADC is a monotonic switching timing, and the MSB capacitor bottom plate is initially connected to V SS After the first comparison is completed, the voltage on the bottom plate of the MSB capacitor at the lower end of the control potential changes from V SS Switch to V REF .

[0021] In the present invention, it is used to convert the single-channel transducer analog input into a 10-bit digital output.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] The analog front end of the present invention has very low noise: the binary redundancy compensation technology is used to reduce the bit error rate of ADC conversion; the comparator input uses the copy input pair technology to reduce the kickback noise; the low noise amplifier LNA adopts a capacitor feedback structure to avoid the noise caused by resistor feedback; dynamic logic control is adopted to avoid the interference of high-frequency clock; dynamic power consumption control technology is adopted to make the current of the amplifier stage determined by the gain, avoiding the noise caused by large current under small gain.

[0024] The analog front end of the present invention has a very small area: the unit-length structure DAC capacitor is significantly smaller than the conventional MIM capacitor, MOM capacitor, and MOS capacitor. In addition, the minimum value of the unit-length capacitor is also smaller than other capacitors. For example, the minimum unit capacitance in the present invention is 0.62fF, while the MIM capacitor in [4] is 26fF and the MOM capacitor in [5] is 23fF. The array of 1024 units in the present invention occupies only 0.0034mm 2 .

[0025] The analog front end of the present invention has very low power consumption: by improving the classic monotonic switch timing, the input common-mode voltage of the comparator changes less, so a comparator with a smaller current (slower speed) can be used, thereby reducing power consumption; the gain stage of the LNA part adopts an Inverter-based and Class-AB structure, and the static power consumption is low; dynamic logic control is adopted to avoid the occurrence of high power consumption of the synchronous circuit; dynamic power consumption control technology is adopted, so that the current of the amplifier stage is determined by the gain, and the noise requirement under large gain can be appropriately relaxed, thereby reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Figure 2 shows digital beamforming (upper left) and analog beamforming (upper right).

[0027] Figure 2a This is the entire circuit structure diagram of the low noise amplifier LNA.

[0028] Figure 2b for Figure 2a Structural diagram of A1.

[0029] Figure 2c for Figure 2a The structure diagram of A2 in .

[0030] Figure 2d for Figure 2a A3 structure diagram.

[0031] Figure 3 This is the structural diagram of SAR ADC.

[0032] Figure 4 This is the schematic diagram of the bootstrap switch.

[0033] Figure 5 This is the schematic diagram of the improved Elzakker comparator.

[0034] Figure 6 is the DAC capacitor array weight.

[0035] Figure 7 It is the specific implementation of Unit-length capacitor.

[0036] Figure 8 This is the schematic diagram of the Unit-length capacitor.

[0037] Fig. 9 This is the schematic diagram of dynamic control logic technology.

[0038] Fig.10 This is the capacitor switch timing in the present invention.

[0039] Fig.11 The common mode level of the comparator input is compared with the conventional monotonic switching timing.

[0040] Fig.12 This is a real picture of the chip of the present invention under a microscope

[0041] Fig.13 The present invention provides an overall circuit structure of an analog front-end chip for ultrasonic imaging digital beamforming. DETAILED DESCRIPTION

[0042] The technical solution of the present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0043] The present invention is an analog front end for ultrasonic imaging, which is mainly composed of a low noise amplifier LNA and an analog-to-digital converter ADC ( Fig.13 ), whose function is to convert the single-channel transducer analog input into a 10-bit digital output. The supply voltage is 1.8V. The 20MHz sampling clock of the ADC is input from outside the chip.

[0044] The structure of the low noise amplifier LNA is shown in Figure 2a , which can be divided into PGA (Programmable Gain Amplifier) ​​and output stage amplifier. C1~C4 are the input capacitors of A1, C5~C8 are the feedback capacitors of A1, and A1 is PGA.

[0045] The structure of the programmable gain amplifier PGA is as follows Figure 2b As shown, Ma1~Ma4 are input tubes, Ma5~Ma8 are common-gate tubes, Ia1 controls the bias current of the circuit, and the size of Ia1 is dynamically controlled according to the gain. Ma9 and Aa1 form a CMFB common-mode feedback loop. All the resistors in the figure use pseudo-resistors to achieve a larger resistance value in a smaller area; the programmable gain amplifier PGA can achieve a variable gain of 0-30, with a step size of 6dB, and the size of the gain is controlled by a three-digit digital signal. Its main structure is a pseudo-differential capacitor feedback amplifier, which realizes the function of TGC (Time Gain Compensation) by changing the ratio of input capacitance and output capacitance. At the same time, in order to reduce the power consumption of the receiver during the entire receiving cycle, the present invention adopts dynamic power control technology, that is, the DC current of the PGA is controlled to increase synchronously when the gain increases. The operational transconductance amplifier OTA in this structure adopts an inverter-based structure, that is, NMOS and PMOS are used as input terminals at the same time, so its equivalent transconductance increases to twice the original. In order to improve the open-loop gain, the structure adopts a cascode structure. Additionally, the differential structure requires common-mode feedback to determine its output common-mode voltage.

[0046] Capacitor feedback is implemented using a split capacitor feedback structure, that is, the operational transconductance amplifier OTA is regarded as having two positive input terminals and two negative input terminals, and then the input capacitor and the output capacitor are divided into two pairs of equal capacitors to implement the feedback structure. In addition, in the present invention, for the differential input pair of PMOS tubes, its DC level is determined by connecting to a fixed potential using a pseudo resistor; for the differential input pair of NMOS tubes, its DC level is determined by connecting to the output terminal using a pseudo resistor.

[0047] In the capacitor feedback structure, the parasitic capacitance of the MOS tube gate will cause the input reference noise of the closed-loop amplifier to be higher than the noise level of the open-loop amplifier. Taking noise performance and area efficiency into consideration, the unit capacitance in the present invention is designed to be 40fF.

[0048] From the perspective of noise, it is also feasible to use dynamic power control technology. This is because when the closed-loop gain is low, even if the circuit can achieve a very low noise level, the weak echo signal cannot be recognized by the ADC after being amplified, so the receiving system does not have high requirements for noise at this time; when the gain is high, the circuit needs to receive very weak echo signals, and only then will higher requirements be placed on the circuit's noise level.

[0049] It should be noted that within the frequency range of ultrasound applications, the flicker noise of NMOS still has a certain impact. Therefore, when designing, for NMOS, a larger gate length L is selected so that the contribution of its flicker noise can be ignored; and for PMOS, the minimum gate length L is selected to reduce the capacitance of its input parasitic capacitance.

[0050] Since the common-mode signal generates the same interference at the output of the differential amplifier and has no effect on the difference of the output signals, the differential amplifier has a stronger ability to resist power supply interference.

[0051] The output stage amplifier is a two-stage amplifier, such as Figure 2c As shown in the figure, the first-stage operational transconductance amplifier OTA adopts an Inverter-Based structure. Mb5 and the common-mode feedback CMFB1 module together form a common-mode feedback loop, and the resistor is also composed of a pseudo resistor. The output OUT+ / - of this stage is connected to the IN+ / - of A3. The Inverter-Based structure improves the energy efficiency of the circuit; Figure 2d As shown in the figure, the second stage adopts a class-AB structure. Mc5, Mc10, and the common-mode feedback CMFB2 module together form the common-mode feedback structure of A3. Mc1~Mc4, Mc6~Mc10 form the class-AB output. The output of this stage is directly connected to the input of the ADC. The static operating point of the second-stage Class-AB structure is determined by the common-mode level of the first stage. Therefore, this structure requires the use of separate common-mode feedback for the first and second stages of the op amp. The output stage amplifier, with a fixed gain of 12dB, is responsible for providing the output swing and strong driving capability of the rail for the subsequent ADC.

[0052] The closed-loop structure of the output stage amplifier is also implemented using the split capacitor structure used in the programmable gain amplifier PGA. For the differential input pair of PMOS tubes, its DC level is determined by connecting to a fixed potential using a pseudo resistor; for the differential input pair of NMOS tubes, its DC level is determined by connecting to the output terminal using a pseudo resistor.

[0053] The main structure of SAR ADC is as follows Figure 3 It is mainly composed of sampling switch, DAC capacitor array, comparator, DEC (Digital Error Correction), SAR logic and output buffer; its sampling rate is 20MHz.

[0054] The present invention adopts top plate sampling, and the sampling switch uses Figure 4 The bootstrap switch shown. Md1 is a switch tube.

[0055] In the hold phase, CLK_HOLD=1, CLK_SAMPLE=0, the gate of the switch is grounded through Md9 and Md10, and the switch is disconnected. Cd1 is a bootstrap capacitor, which is implemented using a MOS capacitor. At this time, one end of Cd1 is grounded and the other end is connected to the power supply, and the voltage across the two ends is approximately VDD.

[0056] In the sampling phase, CLK_HOLD=0, CLK_SAMPLE=1, Md2 is turned on. Since the voltage across the capacitor cannot change suddenly, the voltage at node X is VIN+VDD, and Md8 is also turned on. Therefore, the gate voltage of the switch tube is VIN+VDD. After turning on, its source voltage is VIN, so its drain-source voltage VGS=VDD maintains a fixed value.

[0057] The advantages of this structure are: 1) in the sampling stage, the gate-source voltage of the switch tube is a fixed value, which improves the linearity of the sampling switch; 2) the influence of charge injection is weakened, and only the third harmonic introduced by the NMOS bias effect exists in the differential structure.

[0058] like Figure 4 The sampling switches shown in the figure use two in the circuit, one at the positive input and the other at the negative input of the ADC. The input of the sampling switch is the input of the ADC, and the output of the sampling switch is connected to the DAC capacitor and the comparator input.

[0059] The comparator in the present invention adopts an improved Elzakker type comparator, such as Figure 5 The comparator includes a pre-amplification stage (left figure) and a latch (right figure). Since the current sources of the two are independent of each other, the amplification time of the pre-amplification stage and the regeneration time of the latch are independent of each other.

[0060] The operation of this structure can be divided into the reset phase and the regeneration phase. When CLK_CMP=0,CLK_RES=1, the comparator is in the reset phase. At this time, DP and DN are charged to V DD , Me 10 、Me 11 Shut down. 10 、Me 11 The leakage voltage OUTP, OUTN is discharged to V SS , the source voltage is charged to V DD , so when the latch starts working, Me 10 、Me 11 will be in the saturation zone.

[0061] When CLK_CMP=1,CLK_RES, the comparator is in the comparison stage. At this time, Me5 and Me6 are turned off, Me7 is turned on, and the DN and DP nodes are discharged quickly. The discharge rate depends on the input differential voltage. When the voltage of the DN or DP node drops to the level that makes Me 10 、Me 11 When turned on, the operation of the latch will play a leading role, further amplifying the voltage difference of the previous stage.

[0062] In addition to thermal noise, kickback noise in the dynamic comparator will also affect the performance of the ADC. Kickback noise refers to the following: when the drain voltage of the input tube changes, the existence of the gate-drain parasitic capacitance will cause the change in the drain voltage to couple back to the input. The voltage difference at the differential input of the comparator will cause the difference in the output voltage change rate and the size of the parasitic capacitance, which will cause the voltage coupled back to the input to be different, thus affecting the output result of the comparator.

[0063] To reduce the effect of kickback noise, a technique of duplicating the input pair of tubes can be used, such as Figure 5 As shown in Me3 and Me4 in Figure 1, short-circuiting the source and drain of the two and setting their size to half of Me1 and Me2 can make the voltages of the DN and DP nodes coupled back to the output differential end the same, which will not affect the output of the comparator.

[0064] In the binary search algorithm with redundant bits, the same number corresponds to multiple different digital output codes. Therefore, the introduction of redundant bits can correct the flip errors of the high bits, which may be caused by insufficient DAC settling time or comparator input offset changes with input voltage. To correct the flip error of the nth bit, it is necessary to ensure that the capacitor weight of the nth bit is less than the total weight of the first n-1 bits.

[0065] The present invention adopts binary compensation redundancy design to design the capacitance weight of the DAC array, and its specific weight is as follows: Figure 6 shown.

[0066] Using a DAC capacitor ratio of 240:128:64:36:20:10:6:3:2:1:1, the comparator will have a 12-bit output, all 12 bits are 0 or 1, and the weight of each bit is 240:128:64:36:20:10:6:3:2:1:1. In the DEC module, it is converted into a 10-bit number consisting of 0 or 1, which is a binary number, that is, the weight of each bit is 256:128:64:32:16:8:4:2:1, which is the final ADC 10-bit output.

[0067] In summary, the advantage of using the binary compensation redundancy technology is that the technology is relatively simple to implement, does not require additional compensation capacitors, and does not increase hardware overhead and the area of ​​the DAC array.

[0068] The DAC capacitor in the present invention adopts Unit-length technology. Figure 7 For the layout implementation of this structure, Figure 8 The schematic diagram of the structure is shown in Figure 2. P0 and D N0 Take this as an example to explain the working principle of this technology: when D P0 When switching, the top plate voltage changes (ΔD P0 ×C P0 ) / C DAC , while D N0 The top plate voltage changes (ΔD N0 ×C N0 ) / C DAC , the voltage change of the top plate can be calculated as

[0069]

[0070] Among them, C Δ is the parasitic capacitance corresponding to the metal with a length of Δ, C tot is the total capacitance of the single-sided DAC array. As can be seen from the above formula, the Unit-Length capacitor technology uses the difference between the interdigital capacitances as the unit capacitance value, thus eliminating the influence of the edge capacitance. However, this also causes an attenuation coefficient for the full swing of the input voltage relative to the reference voltage.

[0071] In this technology, there are two unit capacitor structures. The Binary unit achieves binary changes in its unit capacitance by adjusting the relative lengths of the two interdigital capacitor metals, while the Unary unit controls its binary changes by using the Binary unit in proportion. It should be noted that due to the use of binary compensation redundancy technology, when using the Unary unit to achieve high-bit weights, it is necessary to adjust the relative length of the metal in the Binary unit capacitor used in the Unary unit and the number of Binary capacitor units at the same time.

[0072] The present invention uses dynamic control logic technology, that is, the conversion time of each bit is determined according to the size of the input signal. This technology avoids the introduction of high-frequency clocks and can avoid the waste of high-bit conversion time.

[0073] The schematic diagram of dynamic control logic technology is as follows Fig. 9 As shown in the figure, its working principle is as follows: 1) When the SAR ADC is in the sampling stage, the combinational logic controls the comparator to enter the reset stage; 2) When the SAR ADC enters the conversion stage, the potential of the sampling clock changes from V DD Convert to V SS , the combinational logic controls the comparator to start comparing the MSB bit. When the comparison of the comparator is completed, the comparator controls the VALID signal from V SS Switch to V DD , the combinational logic controls the comparator to enter the reset phase; 3) When the comparator reset is completed, the comparator controls the VALID signal from V DD Switch to V SS , the combinational logic controls the comparator to perform the next comparison; 4) Repeat the second and third steps above until all conversions are completed, and the LOGIC_END signal is V SS Switch to V DD , the combinational logic controls the comparator to stop working and remain in a reset state until the next conversion begins.

[0074] The switching timing used in the present invention is based on the classic monotonic switching timing. The number of DAC capacitors required by this timing is half of that of the traditional timing method, thus greatly reducing the power consumption and area of ​​the DAC array. However, there are two problems with using monotonic switching timing: 1) The common-mode voltage at the comparator input will change from 1 / 2V REF It starts to decrease gradually until it approaches 0, which may cause the comparator to not work properly. Even if the comparator can work properly, it will take a long time to get the result of the last few comparisons; 2) As mentioned above, the input offset voltage of the comparator is related to the input common-mode voltage. This means that when using this timing, nonlinearity related to the input voltage may occur in the system.

[0075] The present invention adopts two methods to reduce the impact of common mode voltage changes: 1) Initially, the bottom plate of the MSB capacitor is connected to V SS After the first comparison is completed, the voltage on the bottom plate of the MSB capacitor at the lower end of the control potential changes from V SS Switch to V REF This method can avoid the problem of the comparator working time being prolonged due to excessive reduction of the common mode voltage ( Fig.10 ); 2) Adding redundant bits to the binary DAC array can correct the comparison errors that may be caused when the high-bit common-mode voltage changes too much.

[0076] Fig.11 The present invention is compared with the traditional monotonic switch timing for the input common mode level of the comparator. For the traditional switch timing, each switching of the DAC switch will cause the DAC and comparator input common mode level to decrease, and the input common mode level will decrease from 1 / 2Vref until it approaches Vss. When the input common mode level is too low, the comparator comparison speed will slow down or even malfunction. In the present invention, the first switching of the DAC switch will increase the common mode level of the DAC and the comparator, so after 12 comparisons are completed, the common mode level will not decrease to the point where the comparator loses its normal working function.

[0077] The present invention uses SAR ADC to realize single-channel digital-to-analog conversion, and realizes an analog front end for ultrasound with high dynamic range and high signal-to-noise ratio with small power consumption and area. The results are shown in Table 1:

[0078] Table 1 Comparison of the most advanced ultrasound analog front-end parameters so far

[0079]

[0080] *Peak SNDR**Only LNA

[0081] ***Equivalent Single-channel DR=Multiple-channel DR-10logN(N is the number of channels)

[0082] #Only RX circuit

[0083] References

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Claims

1. An analog front-end chip for digital beamforming of ultrasonic imaging, characterized in that: It includes a low noise amplifier LNA and an analog-to-digital converter ADC; wherein: The low noise amplifier LNA includes a programmable gain amplifier PGA and an output stage amplifier; the programmable gain amplifier PGA adopts a pseudo-differential capacitor feedback amplifier structure, wherein the operational transconductance amplifier OTA adopts an inverter-based structure, i.e., NMOS and PMOS are used as input terminals at the same time, and the operational transconductance amplifier OTA is a common source and common gate cascode structure, and the differential structure uses common mode feedback to determine its output common mode voltage; the capacitor feedback is implemented using a split capacitor feedback structure, i.e., the operational transconductance amplifier OTA is regarded as having two positive input terminals and two negative input terminals, and then the input capacitor and the output capacitor are divided into two pairs of equal capacitors to implement the feedback structure; the output stage amplifier is a two-stage amplifier, and the first-stage operational transconductance amplifier OTA adopts an inverter-based structure, which improves the energy efficiency of the circuit; the second-stage operational transconductance amplifier OTA adopts a class-AB structure; the first-stage and second-stage operational transconductance amplifiers OTA use separate common mode feedback, and the static operating point of the second-stage Class-AB structure is determined by the common mode level of the first stage; the closed-loop structure of the output stage amplifier is also implemented using a split capacitor feedback structure; The differential output of the low noise amplifier is directly connected to the differential input of the ADC, which uses the SAR ADC to achieve single-channel digital-to-analog conversion.

2. The analog front-end chip for ultrasonic imaging digital beamforming according to claim 1, characterized in that: The gate length of the NMOS tube is greater than the gate length of the PMOS tube.

3. The analog front-end chip for ultrasonic imaging digital beamforming according to claim 1, characterized in that: In the low noise amplifier LNA, for the differential input pair of PMOS tubes, the DC level is determined by connecting to a fixed potential using a pseudo resistor, and for the differential input pair of NMOS tubes, the DC level is determined by connecting to the output terminal using a pseudo resistor.

4. The analog front-end chip for ultrasonic imaging digital beamforming according to claim 1, characterized in that: During operation, a dynamic power control method is adopted so that the direct current of the programmable gain amplifier PGA increases synchronously when the gain increases.

5. The analog front-end chip for ultrasonic imaging digital beamforming according to claim 1, characterized in that: SAR ADC is mainly composed of sampling switch, DAC capacitor array, comparator, digital error correction DEC, SAR logic and output buffer; among them: the sampling switch adopts bootstrap switch, the comparator adopts improved Elzakker comparator, which includes a pre-amplifier and a latch, the current sources of the two are independent of each other, and the comparator input uses replica input pair technology; the capacitance of the DAC capacitor array is Unit-length structure, which uses the difference between the interdigital capacitances as the unit capacitance value.

6. The analog front-end chip for ultrasonic imaging digital beamforming according to claim 5, characterized in that: The unit-length capacitor includes two unit capacitor structures; the Binary unit achieves binary variation of its unit capacitance by adjusting the relative lengths of the two interdigitated capacitor metals, while the Unary unit controls its binary variation by using the Binary unit in proportion.

7. The analog front-end chip for ultrasonic imaging digital beamforming according to claim 5, characterized in that: Binary compensation redundancy is used to design the capacitance weights of the DAC array.

8. The analog front-end chip for ultrasonic imaging digital beamforming according to claim 1, characterized in that: The analog-to-digital converter ADC uses a dynamic control logic method to determine the conversion time of each bit according to the size of the input signal. The specific steps include: 1) When the SAR ADC is in the sampling phase, the combinational logic controls the comparator to enter the reset phase; 2) When the SAR ADC enters the conversion phase, the potential of the sampling clock changes from V DD Convert to V SS , the combinational logic controls the comparator to start comparing the MSB bit; when the comparison of the comparator is completed, the comparator controls the VALID signal from V SS Switch to V DD , the combinational logic controls the comparator to enter the reset phase; 3) When the comparator reset is completed, the comparator controls the VALID signal from V DD Switch to V SS , the combinational logic controls the comparator to perform the next comparison; 4) Repeat the second and third steps above until all conversions are completed and the LOGIC_END signal is V SS Switch to V DD , the combinational logic controls the comparator to stop working and remain in a reset state until the next conversion begins.

9. The analog front-end chip for ultrasonic imaging digital beamforming according to claim 1, characterized in that: The switching timing used in the analog-to-digital converter ADC is a monotonic switching timing. Initially, the bottom plate of the MSB capacitor is connected to V SS After the first comparison is completed, the voltage on the bottom plate of the MSB capacitor at the lower end of the control potential changes from V SS Switch to V REF .

10. The analog front-end chip for ultrasonic imaging digital beamforming according to claim 1, characterized in that: It is used to convert the single-channel transducer analog input into a 10-bit digital parallel output.

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